®
Component
Selector Guide
February 2003
Altera Corporation
S
SOPC Solutions
The world’s pioneer in system-on-a-programmable-chip
(SOPC) solutions, Altera Corporation offers a complete
range of programmable logic device (PLD) products with
the flexibility, functionality, package types, and time-tomarket advantages to meet almost any design need.
Combined with Altera’s integrated design software,
comprehensive intellectual property (IP) portfolio,
embedded processors, peripherals, and extensive customer
training program, Altera® PLDs provide the flexibility,
ease-of-use, and short development cycles you need to
turn your design concepts into solid design solutions.
in the industry—are the foundation of Altera’s SOPC
solutions, which include everything you need to quickly
and easily deliver the most competitive and distinctive
products in your market. Advanced, smart, and ready to
tackle your biggest design challenges, Altera’s SOPC tools
include the Quartus® II design software—the only PLD
design tool that offers a block-based design methodology—
and a variety of sophisticated IP MegaCore® and Altera
Megafunction Partners Program (AMPPSM) megafunctions,
optimized, customizable functions that are ready to drop
into your design. Additionally, you can pair FPGAs with
the 16- or 32-bit Nios® embedded soft processor, a
Altera offers two types of PLDs: FPGAs and CPLDs. Altera
configurable, general-purpose RISC processor with memory
FPGAs are high-density, feature-rich devices that deliver the
and peripherals that can be tailored to the requirements of
flexibility and performance needed for a comprehensive,
virtually any system.
high-performance SOPC solution, while CPLDs offer nonvolatile, instant-on capabilities for power-on and reset, I/O
expansion, and bridging applications.
Altera CPLDs offer many features for systems that require
simple yet high-performance logic integration at a low
price. CPLDs are ideal for low-density control and glue
From simple glue logic to complex SOPC solutions, Altera's
logic integration in end-systems ranging from
device solutions include:
communication infrastructure and data processing to
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Altera FPGAs—the most advanced programmable devices
High-density FPGAs: delivering the best possible system
integration for high-bandwidth systems (page 3)
consumer applications. This combination of performance,
Low-cost/high-volume FPGAs: bringing the lowestcost FPGAs to price-sensitive, volume-driven systems
(page 7)
design solution for simple programmable logic integration.
FPGAs with embedded high-speed transceivers:
providing a low-risk path to high-speed transceiver
applications (page 9)
As a world leader in FPGA technology, all Altera devices
FPGAs with embedded processors: providing the tools
needed to integrate an entire system on a single PLD
(page 12)
CPLDs: offering high-performance,
low-cost solutions for a wide variety
of digital applications (page 13)
Configuration devices:
enabling fast remote
system upgrades and insystem programmability (ISP) for all
Altera FPGAs
(page 15)
flexibility, and ease of use makes Altera CPLDs the ideal
Altera CPLDs are supported by the Quartus II and
MAX+PLUS® II design software.
use the most advanced CMOS processes. The newest
product families—including Stratix™, Stratix GX, and
Cyclone™ FPGAs—are manufactured on an all-layer-copper
0.13-µm process, the state-of-the-art in
fabrication. In addition, Altera devices are
available in a broad range of spacesaving package options, including
thin quad flat pack (TQFP), the
innovative and area-efficient
1.0-mm ball-pitch
FineLine BGA® packages,
and 0.8-mm ball-pitch
Ultra FineLine BGA
packages.
Altera Corporation
Stratix FPGAs
Altera’s high-density FPGAs deliver the unsurpassed
Altera’s Stratix device family breaks the performance and
flexibility, core performance, memory capacity, digital
density barriers for high-density programmable logic, pow-
signal processing (DSP) capabilities, bandwidth, and time-
ering complex designs to new levels of system integration.
to-market advantages required for complex SOPC solutions.
The Stratix family is the first FPGA family designed to
Incorporating customer feedback on real system design
enable a comprehensive block-based design methodology.
requirements, Altera developed high-density FPGAs—Stratix
In conjunction with the Quartus II LogicLock™ incremental
and APEX™ devices—to address the increasingly complex
design feature, designers can optimize and lock the perfor-
bandwidth requirements of SOPC applications in
mance of individual design blocks even when blocks are
communications, industrial, automotive, electronic data
moved or integrated with other optimized functions. In
processing, and digital consumer end-markets. Altera’s
addition, Stratix devices offer system-level features that
high-density FPGA families range from 1,200 to 114,140
give designers the performance, memory bandwidth,
logic elements (LEs), and provide the innovative
digital signal processing (DSP) functionality, and I/O
architectures and rich feature sets needed to reach your
performance necessary for sophisticated SOPC solutions.
next-generation performance and bandwidth targets.
High-Densty FPGAs
H
High-Density FPGAs
Stratix devices are based on
a 1.5-V, 0.13-µm, all-layercopper SRAM process, with
Applications
■ High-End Routers & Switches
■ IC Testers
■ Medical Imaging Equipment
densities ranging from 10,570 to 114,140 LEs. Stratix
devices feature the TriMatrix™ memory structure, an array
of three different-sized memory blocks, each optimized to
target a different class of applications. The integration of
the 512-Kbit M-RAM blocks with hundreds of smaller
M512 and M4K blocks provides a unique solution to
applications requiring large amounts of on-chip memory
For system designers who need a cost-
bits or high memory bandwidth (see Figure 1 on page 4).
reduction path for high-volume produc-
Offering up to 10 Mbits of RAM and up to 12 terabits per
tion, Altera offers an easy, risk-free
second of device memory bandwidth, Stratix devices
migration solution from high-density
feature the highest memory-to-logic ratio and the highest
FPGAs to low-cost, custom-built
memory bandwidth in the industry. All memory blocks
HardCopy™ devices. HardCopy devices preserve the func-
include extra parity bits for error control, embedded shift
tionality and timing of the design, providing a timesaving
register functionality, mixed width mode, and mixed clock
alternative to ASICs for high-volume production.
mode support.
Table 1. Stratix Highlights
FEATURE
BENEFIT
High-Performance Architecture
Performance-optimized MultiTrack™ interconnect with DirectDrive™ technology for block-based
design methodology
TriMatrix Memory
Three sizes of embedded memory blocks with up to 1,650 memory bocks, 10 Mbits of RAM, up to
12 terabits per second of memory bandwidth, and data transfer rates of over 300 MHz
DSP Blocks
Predictable 333-MHz performance for data throughput of up to 2.6 GMACS per DSP block
High-Bandwidth I/O Standards
and High-Speed Interfaces
Support for high-speed I/O standards and high-speed interfaces such as the 10-Gigabit Ethernet
(XSBI), SFI-4, POS-PHY Level 4, HyperTransport™, RapidIO™, and UTOPIA Level 4 interfaces at up to
840 Mbps, as well as support for advanced external memory device interfaces
Clock Management Circuitry
Up to 12 phase-locked loops (PLLs) and up to 40 system clocks with features such as clock switchover,
PLL reconfiguration, spread-spectrum clocking, frequency synthesis, and programmable phase and
delay shift
Terminator™ Technology
On-chip serial, parallel, and differential termination
Remote System Upgrades
Real-time updates to PLDs from remote locations
Cost-Reduction Migration Path
Cost-reduction migration path to HardCopy devices supported for high-density Stratix devices
Altera Corporation
3
High-Densty FPGAs
Ideal for the wireless communication, telecommunication,
Figure 2. Stratix Architecture
video, and image processing markets, Stratix devices offer
up to 28 DSP blocks (high-performance embedded
arithmetic units) that eliminate the performance
bottlenecks in arithmetic applications. Comprised of
Logic
Array
Blocks
DSP
Blocks
multiply and accumulate circuitry, the DSP blocks provide
predictable performance and significant resource savings
for complex applications that require high data
throughput. These DSP blocks can implement a variety of
M-RAM
Blocks
PhaseLocked
Loops
I/O
Elements
typical DSP functions, such as finite impulse response
(FIR) filters, fast Fourier transform (FFT) functions,
correlators, and encryption/decryption functions, as well as
M512
RAM
Blocks
M4K
RAM
Blocks
mathematically intensive functions. DSP blocks in Stratix
devices can run at over 333 MHz to provide data
throughput performance of up to 2.6 GMACS per DSP
block. The 28 DSP blocks in the largest Stratix device can
standards such as the LVDS, LVPECL, PCML, differential
provide a combined throughput that is more than 12 times
SSTL, differential HSTL, LVTTL, LVCMOS, SSTL, HSTL,
the data throughput available from leading digital signal
PCI-X, CTT, AGP, GTL, GTL+, 10 Gigabit Ethernet (XSBI),
processors today.
SFI-4, POS-PHY Level 4, HyperTransport, RapidIO, and
UTOPIA IV standards. This comprehensive support for
Supporting a variety of single-ended and differential I/O
standards, Stratix devices offer designers an aggregate
device bandwidth of up to 600 Gbps and access to up to
high-speed I/O interfaces and high-bandwidth protocols
makes Stratix devices an ideal solution for complete
system integration.
116 high-speed differential I/O channels. Each of these I/O
channels includes dedicated serializer/deserializer (SERDES)
Stratix devices are based on an innovative high-
circuitry for high-speed standards. Stratix devices support
performance architecture (see Figure 2). With as many as
12 PLLs, up to 40 system clocks for systemlevel clocking management, support for many
Figure 1. TriMatrix Memory Structure
differential and single-ended I/O electrical
More Bits for Larger Memory Buffering
M512 Blocks
M4K Blocks
M-RAM Blocks
standards, high-speed interfaces, on-chip
termination, and remote system upgrade
capabilities, Stratix devices bring new levels
of system integration to SOPC designs.
Table 1 on page 3 describes some Stratix
device highlights.
More Data Ports for Greater Memory Bandwidth
• 512 bits per block + parity
• Up to 1,118 blocks
• 4 Kbits per block + parity
• Up to 520 blocks
• 512 Kbits per block + parity
• Up to 12 blocks
Applications
• Rake receiver correlator
• Shift register
• Small FIFO buffers
• Finite impulse response
(FIR) filter delay line
4
• ATM cell packet processing
• Header/cell storage
• Channelized functions
• Program memory for
processors
• IP packet buffering
• System cache
• Video frame buffers
• Echo canceller data storage
• Processor code storage
Altera Corporation
High-Densty FPGAs
APEX FPGAs
Figure 3. APEX Device Features
With densities of 1,200 to 51,840 LEs and data transfer
MultiCore Architecture
ESB
rates up to 840 Mbps per channel, APEX FPGAs offer
LUT
Memory
complete system-level integration on a single device.
ESB
Designed to be 64-bit, 66-MHz PCI-compliant, APEX
Dual-Port RAM
ROM
CAM
devices feature the innovative MultiCore™ architecture (see
Figure 3), which combines and enhances the strengths of
the earlier Altera device architectures.
The APEX devices consist of three families: APEX 20KC,
APEX 20KE, and APEX 20K devices. Featuring all-layer-
I/O Features
True-LVDS SSTL-2/-3
GTL+
HSTL
CTT
LVPECL
AGP
MultiVoltTM I/O
copper interconnects, APEX 20KC FPGAs offer the highest
APEX performance. APEX 20KE FPGAs offer tremendous
breadth in density, I/O capability, and package options at
cost-effect price points.
Clock Management
Up to 4 PLLs
ClockShift Circuitry
ClockBoost Circuitry
ClockLock Circuitry
The APEX MultiCore architecture features embedded
system blocks (ESBs) that can implement several types of
I/O interface solution, and is supported via the use of
memory structures, including dual-port RAM, content-
dedicated serial-to-parallel conversion circuitry and
addressable memory (CAM), first in first out (FIFO) buffers,
LVDS-optimized PLLs.
and ROM. The direct implementation of CAM in embedded
silicon provides significant performance improvements for
any pattern-matching or data-searching applications.
To increase system clock rates, APEX devices feature up to
four PLLs with output frequencies up to 335 MHz. These
PLLs can provide improvements within an APEX device or
APEX devices meet system performance demands and offer
in the interactions of an APEX device with other system
lower supply voltages by supporting multiple I/O
components, or can serve as the clock management
interfacing standards, including LVTTL, LVPECL, LVCMOS,
circuitry for an entire board-level system, providing
GTL+, SSTL-2/-3, AGP, HSTL, CTT, and LVDS with
improvements for unrelated system components. Table 2
performance up to 840 Mbps. True-LVDS™ support has
describes some APEX device highlights.
been specifically incorporated as a key high-performance
Table 2. APEX Highlights
FEATURE
BENEFIT
840-MHz True-LVDS Interface
High-speed I/O interface to provide a true system-level programmable solution
All-Layer-Copper Interconnect
Improves performance by 25% over 0.18-µm aluminum-based devices
MultiCore Architecture
Integrates look-up table (LUT) logic and dual-port RAM memory into a single architecture
PCI and PCI-X Compliance
Meets all specifications for 64-bit, 66-MHz PCI compliance and 66-MHz PCI-X support
Support for Emerging I/O Standards
Supports LVDS, LVPECL, LVTTL, LVCMOS, GTL+, CTT, AGP, HSTL, and SSTL-2/-3 I/O standards
Density up to 1.5 Million Gates
(2.4 Million System Gates)
Addresses system-level density needs
1.8-V and 2.5-V Operation
Reduces power consumption
Up to Four PLLs
Supports ClockLock®, ClockBoost®, and ClockShift™ circuitry, 1x to 160x clock multiplication, and
1 to 256 clock division with an extended frequency range
FineLine BGA Packaging
Offers area-optimized, high-pin-count BGA packages and packaging migration flexibility
with better thermal characteristics
Altera Corporation
5
High-Densty FPGAs
APEX II FPGAs
data synchronization (CDS) circuitry, enable high-speed
The APEX II device family offers advanced I/O features
to support a complete SOPC solution. APEX II devices
support a host of emerging network communications
applications and I/O protocols, such as the UTOPIA IV,
RapidIO, CSIX, and POS-PHY Level 4 protocols, and are
built on a 0.15-/0.13-µm all-layer-copper interconnect
technology. APEX II devices offer versatility and
flexibility for SOPC applications requiring extended I/O
data transfers. APEX II devices are fully 64-bit, 66-MHz
PCI and PCI-X compliant. APEX II devices feature four
general-purpose PLLs that can drive eight different global
clock networks and circuit signals for comprehensive
clock management and synthesis needs. Additionally,
all APEX II devices include 36 input and 36 output
True-LVDS channels that can achieve data transfer rates
of up to 1 Gbps per channel. EP2A15 and EP2A25
devices have 56 input and 56 output Flexible-LVDS™
standard support.
channels, and EP2A40 and EP2A70 devices feature 88
APEX II device densities range from 16,640 to 67,200 LEs
input and 88 output Flexible-LVDS channels.
and offer 4 Kbits of memory per ESB with a total device
memory of up to 1.1 Mbit. The APEX II device family
supports a wide range of high-speed I/O standards such
as LVDS, PCML, LVPECL, HyperTransport, HSTL, and
SSTL, which, along with dedicated SERDES and clock-
New designs requiring high performance should
utilize Stratix (see page 3) and Stratix GX (see page 9)
FPGAs, which deliver today’s top performance and
feature attributes.
Table 3. APEX II Highlights
6
FEATURE
BENEFIT
1-Gbps True-LVDS Solution
Provides 36 input and 36 output high-speed channels for high-performance applications and
supports the LVDS, LVPECL, PCML, and HyperTransport standards
624-Mbps Flexible-LVDS Solution
Provides up to 88 input and 88 output channels for high-bandwidth needs and supports LVDS,
LVPECL, and HyperTransport
Clock-Data Synchronization (CDS)
Allows up to 36 independent LVDS data channels to interface with one APEX II device
Six Registers per I/O Element
Provides support for high-speed external memory interfaces such as ZBT-, DDR-, and
QDR-based memory devices
Enhanced PLLs
Supports ClockLock, ClockBoost, and ClockShift circuitry for flexible clock synthesis and clock
management with eight output taps and two off-chip outputs
Advanced Embedded System
Blocks (ESBs)
Implements true dual-port RAM, FIFO buffers, ROM, and CAM with 4 Kbits of memory per ESB
PCI and PCI-X Compliance
Meets all specifications of 64-bit, 66-MHz PCI and PCI-X
MultiVolt I/O Operation
Ideal for mixed voltage systems
FineLine BGA Packaging
Area-optimized, 1.0-mm ball pitch provides high pin count
Vertical Migration
Addresses changing device density without the need to re-spin the board
Altera Corporation
Extending the benefits of programmable logic to
customers in markets where innovation is key and being
first-to-market determines leadership.
Cyclone devices are built on a
applications currently driven by cost and time-to-market
cost-optimized, all-copper 1.5-V
pressures to standard products or ASICs, Altera's lowcost/high-volume Cyclone™ and ACEX® FPGA families
SRAM process, and offer powerful functionality at half the
provide the reprogramability of an FPGA at the cost of an
cost of competing FPGAs. With up to 20,060 LEs and
ASIC. These FPGAs deliver SOPC solutions to applications
288 Kbits of on-chip RAM, Cyclone devices can integrate
beyond that of any other low-cost programmable product
many complex functions. Cyclone devices offer multiple
in history and provide an optimized feature set and
full-featured PLLs to manage board-level clock networks
abundant on-chip resources specifically tuned for high-
and dedicated I/O interfaces for interfacing with industry-
volume applications.
standard external memory devices. Altera's Nios embedded
Low-Cost/High-Volume FPGAs
L
Low-Cost/High-Volume FPGAs
processor and a full IP portfolio are also available for
Applications
■ Digital Set-Top Boxes
■ DVD Player/Recorder System
■ Plasma Displays
■ Automotive Telematics
■ Industrial Automation Equipment
Cyclone FPGAs
Involving customers at the early development stages,
development with Cyclone devices. In fact, with a Nios
processor in a Cyclone device, a 32-bit, 50 Dhrystone
MIPS RISC processor costs less than US $2.00 for highvolume applications (see Figure 4.)
Figure 4. Nios Embedded Processor Solution
EP1C3T100 Device
Density: 2,910 LEs
Package: 100-Pin TQFP
Price: US $4.001
EP1C3T100
Available Programmable Logic
Altera built Cyclone devices from the ground up to meet
the specific features, density, performance, and price points
needed to make FPGAs viable in high-volume applications.
Less than
2
US $2.00
With new market trends such as worldwide standards,
platform convergence, interactivity, and improved
4K RAM
technology continuing to drive the need for cost-effective
solutions, Cyclone devices—the lowest-cost FPGAs ever—
offer the price points and functionality necessary for
Notes:
1
2
UART
Ethernet Interface
Serial
Peripheral
Interface
Multiply Unit
Pricing for 250K units in 2004.
Nios processor and peripherals use about 1,400 LEs.
Table 4. Cyclone Highlights
FEATURE
BENEFIT
Embedded Memory
Each Cyclone embedded memory block consists of columns of 4,608-bit memory blocks and supports multiple
configurations, including true dual-port and single-port RAM, ROM, and FIFO buffers
External Memory
Interfaces
Cyclone devices have dedicated interfaces to support high-speed memory devices including 133-MHz (266-Mbps)
double data rate (DDR) SDRAM, single data rate (SDR) SDRAM, and fast cycle RAM (FCRAM) devices
I/O Standard Support
Cyclone devices support both single-ended I/O standards—such as LVTTL, LVCMOS, PCI, SSTL-3, —as well as
differential I/O standards with up to 129 LVDS-compatible I/O pins that are capable of data transfer at up to
311 Mbps
Clock Management
Circuitry
For complete system clock management on- and off-chip, Cyclone devices feature eight low-skew, global
clock networks that span the entire device, fed by four dedicated input clock pins as well as PLLs that each have
three output taps, and feature frequency synthesis and phase-shifting capabilities
Nios Embedded
Processor
The industry’s most widely used embedded soft-core processor can be configured to suit the specific requirements
of low-cost, Cyclone device-based designs, and it consumes minimal logic, leaving plenty of resources for other
system functions
Intellectual Property
(IP)
Developed, tested, and licensed IP functions that accelerate system design—such as PCI, memory controllers,
FFTs—are available from AMPP partners
Serial Configuration
Devices
Designed to deliver the lowest possible total-solution cost, these devices can store configuration data while using
remaining resources for general-purpose storage
Altera Corporation
7
The Cyclone device family has the perfect mix of features,
markets at the lowest of costs. Table 4 on page 7 describes
density, and performance at less than $1.50 per 1,000 LEs—
some Cyclone device highlights.
half the cost of competing FPGAs. System designers
To fully realize the value of Cyclone devices in your SOPC
building high-volume applications in the consumer,
designs, Altera has developed a new cost-optimized serial
communications, computer peripheral, automotive, and
configuration device family (see page 15). Also, to reduce
industrial markets now have access to the flexibility,
overall development costs, Cyclone devices are fully
economic efficiencies, and time-to-market advantages of
Low-Cost/High-Volume FPGAs
programmable logic (see Figure 5). With Cyclone devices,
these advantages are accessible to the widest range of
supported in the free Quartus II Web Edition design
software available on the Altera web site
(www.altera.com).
Figure 5. Cyclone Device Target Applications
Consumer
■
Set-top box
■
■
■
DVD player
Communications & Wireless
■
Mid- to low-end router
Plasma display
■
DSL router
HDTV
■
Broadband fixed wireless
customer premise(s)
equipment (CPE)
■
Automotive
■
Gateway controller
■
Software radio
receiver
■
Wireless LAN access point
Computers &
Storage Devices
Industrial
■
Factory automation
■
Printer
■
Process control
■
Storage server
■
Network test
equipment
Telematics/
entertainment
controller
ACEX FPGAs
4,992 LEs. Operating at 2.5 V, ACEX devices are fully
The ACEX FPGA family provides value and performance
for cost-sensitive, volume-driven applications. Capable of
interfacing with 5.0-V, 3.3-V, and 2.5-V I/O circuitries,
these devices are ideal for the communications and consumer marketplaces in applications such as cable modems,
DSL modems, low-cost switches, and routers.
The ACEX family, which is based on an advanced,
cost-optimized 2.5-V SRAM process, ranges from 576 to
64-bit, 66-MHz PCI compliant and feature embedded dualport RAM and advanced packaging technologies. ACEX
devices support PLL circuitry and can drive two separate
ClockLock and ClockBoost circuitry-generated signals for
extensive clock management capability. Table 5 describes
some ACEX device highlights.
New designs requiring the lowest cost should utilize
Cyclone devices, the lowest-price FPGAs ever. (See page 7).
Table 5. ACEX Highlights
8
FEATURE
BENEFIT
Low Cost
Low cost-per-function
High-Volume Solution
Ideal for price-sensitive, high-volume applications
High Performance
High-performance capabilities to support your challenging applications
Targeted at Price-Sensitive
Markets
Supports features and performance needed in the price-sensitive marketplace
Altera Corporation
F
FPGAs with Embedded HighSpeed Transceivers
Stratix GX FPGAs
Ultra high-speed applications need reliable data transfer
3.125-Gbps transceiver technology with the industry's
technology that gets information from source to
fastest FPGA architecture. Including customer-defined
destination in picoseconds. Altera offers Stratix GX and
features for high-speed design implementation, Stratix GX
Mercury™ devices, FPGAs with embedded high-speed
devices give system architects—from communications to
transceiver technology that supports fast I/O signaling
high-end consumer electronics to mass storage systems—
rates and consumes minimal power. Using Altera’s
a low-risk path to 3.125-Gbps transceiver applications.
The Stratix GX device family is a powerful fusion of
embedded high-speed transceiver FPGAs, designers can
Built on a 1.5-V, 0.13-µm,
also implement specific interface protocols such as
all-layer-copper SRAM
10 Gigabit Ethernet XAUI or customized functions that
process, Stratix GX devices
are available in densities ranging from 10,570 to 41,250 LEs
based FPGAs bring the benefits of programmable logic
and with up to 3.3 Mbits of RAM. Based on the Stratix
and the capabilities of fast, reliable I/O technology to both
architecture, Stratix GX FPGAs feature dedicated gigabit
new and existing high-speed applications, including
transceiver blocks with encoded clock-data recovery (CDR)
bridging applications, switch fabrics, traffic management
technology to receive and transmit high-speed serial data
functions, wireless, and high-definition television (HDTV)
streams. Each Stratix GX transceiver block has four
broadcast applications.
independent, full-duplex channels that contain dedicated
FPGAs with Embedded
High-Speed Transceivers
require data rates up to 3.125 Gbps. Altera’s transceiver-
circuitry for speed-critical and logic-intensive physical
layer functions. The 3.125-Gbps transceiver blocks also
Applications
■ 10 Gigabit Ethernet XAUI & Fibre Channel
Backplane Systems
■ SONET/SDH Backplane Applications
■ SD & HD SDI Video Products
include 8B/10B encoder/decoder circuitry that provides
support for several high-speed protocols—including the
10 Gigabit Ethernet (XAUI and XSBI), SONET/SDH,
Gigabit Ethernet, InfiniBand, 1G and 2G Fibre Channels,
Serial RapidIO, SFI-5, SFI-4, SPI-5, POS-PHY Level 4
(SPI-4 Phase 2), HyperTransport, RapidIO, PCI Express,
SMPTE 292M, and UTOPIA IV standards. Figure 6 shows
Table 6. Stratix GX Highlights
FEATURE
BENEFIT
3.125-Gbps Transceiver Blocks
Embedded transceiver blocks including 8B/10B encoder/decoder circuitry provide support for highspeed applications such as 10 Gigabit Ethernet XAUI, Gigabit Ethernet, InfiniBand, 1G and 2G Fibre
Channels, Serial RapidIO, SONET/SDH, SFI-5, SPI-5, PCI Express, and SMPTE 292M standards
40-Inch Drive Strength
Capability
Transceiver capabilities, embedded programmable pre-emphasis, and embedded receiver equalization combine to enable a 40-inch signal drive capability across an FR4 backplane and two
backplane connectors
Low Power Consumption
450-mW power consumption per 4-channel transceiver block simplifies board design
Optimal Channel-to-Logic Ratio
Device densities ensure sufficient logic for system implementation
Source-Synchronous Differential
I/O Signaling with DPA1
Support for high-speed I/O standards and high-speed interfaces such as 10 Gigabit Ethernet XSBI,
SFI-4, SPI-4 Phase 2 (POS-PHY Level 4), HyperTransport, RapidIO, and CSIX streaming standards
at up to 1 Gbps to complement transceiver bandwidth
High-Performance Stratix
Device-Based Architecture
Highly optimized FPGA architecture provides innovative routing architecture for block-based
design and maximum system performance. Features such as TriMatrix memory, DSP blocks,
Terminator™ technology, and clock management circuitry enable full system implementation
Note: 1 DPA can be bypassed for protocols disallowing skews such as UTOPIA IV.
Altera Corporation
9
the Stratix GX device architecture, and
Figure 6. Stratix GX Architecture
Figure 7 shows the Stratix GX transceiver
EP1SGX25F
Logic Array
Blocks (LABs)
channel architecture.
SourceSynchronous I/O
Channels with
Dynamic
Phase
Alignment
To complement the transceiver blocks,
Stratix GX devices include a full suite of
source-synchronous differential I/O channels
with integrated dynamic phase alignment
(DPA). There are up to 45 receiver and
Transceiver
Channel
M512 Block
45 transmitter high-speed differential I/O
Gigabit
Transceiver
Block
PhaseLocked
Loops (PLLs)
channels, each running at up to 1 Gbps. These
channels support the LVDS, LVPECL, 3.3-V
SingleEnded I/O
Elements
(IOEs)
M4K Block
PCML, and HyperTransport I/O standards.
M-RAM Block
Stratix GX devices offer up to 3.3 Mbits of
DSP Blocks
embedded RAM with the TriMatrix memory
FPGAs with Embedded
High-Speed Transceivers
structure, up to 14 DSP blocks, a complete
clock management solution with a hierarchical
40-inch FR4 backplane drive strength capability, low-
clock structure and up to eight PLLs, as well as on-chip
power consumption, and an optimal channel-to-logic ratio.
Terminator technology to reduce reflection, improve signal
Table 6 on page 9 describes Stratix GX device highlights.
integrity, and simplify board layout. Other features include
Figure 7. Stratix GX Transceiver Channel Architecture
Serial-toParallel
Pattern
Detector &
Word Aligner
Clock
Recovery Unit
Reference
Clock
Reference
Clock
Rx PLL
Tx PLL
Parallelto-Serial
10
Recovered
Clock to
Programmable Logic
Rate Matcher
& Channel
Aligner
Synchronizer
8B/10B
Decoder
Receive
Transmit
8B/10B
Encoder
Synchronizer
Altera Corporation
Mercury FPGAs
Figure 8. Mercury Architecture
Altera’s Mercury FPGAs address a wide range of
serial backplane, chip-to-chip, and line-side
applications. Mercury devices integrate CDR
technology and a performance-optimized PLD
architecture into a single device (see Figure 8).
Data rates of up to 1.25 Gbps per channel and a
total CDR bandwidth of up to 45 Gbps provide
CDR at
1.25 Gbps
- LVDS
- LVPECL
- PCML
the solution for today’s demanding
communications requirements.
High-speed I/O functionality
and CDR circuitry are key
elements in highperformance communications links. The Mercury
CDR circuitry provides the clock management
Architecture Built
for Bandwidth
- High Core Performance
- Optimized for Speed
- Distributed Multiplier
Capability
Advanced I/O Support
- DDR SDRAM - SSTL-3/-2
- ZBT SRAM - HSTL
- PCI-X
- AGP
- GTL+
- LVTTL
FPGAs with Embedded
High-Speed Transceivers
required for complex serial backplane applications
Quad-Port ESB
- Quad-Port RAM
- CAM
- High-Speed FIFOs
Enhanced PLL
- 12 PLL Clocks
- ClockLock Circuitry
- ClockBoost Circuitry
- ClockShift Circuitry
and is suitable for use in systems using Gigabit
Ethernet, RapidIO, and POS-PHY L4 protocols.
These protocols are supported with up to 18 highspeed differential channels.
support solution, dedicated circuitry to interface with highspeed memories, and up to 6 PLLs. In addition, Mercury
Mercury devices complement this CDR capability with a
devices include high-performance logic optimized for
robust PLD architecture to support the high bandwidth
speed. This logic performance is enabled using a prioritized
generated by the CDR circuitry. The Mercury architecture
interconnect structure, dedicated multiplier circuitry, and
includes over 100 channels of Flexible-LVDS support on
quad-port ESBs on a 0.15-µm, 1.8-V all-layer-copper
regular I/O pins, a fully flexible advanced I/O standard
process. Table 7 describes some Mercury device highlights.
Table 7. Mercury Highlights
FEATURE
BENEFIT
CDR Circuitry
Data rates of up to 1.25 Gbps with LVDS, LVPECL, and PCML support
Advanced I/O Standard Support
Supports PCI, PCI-X, HSTL, GTL+, SSTL-2/-3, AGP, CTT, and LVTTL standards
External Memory Interface
Built-in support for external ZBT, DDR, and QDR RAM
Flexible-LVDS Support
Provides 624-Mbps LVDS support on up to 100 regular I/O pins
Enhanced PLLs
Provides up to 6 PLLs with support for ClockLock, ClockBoost, and ClockShift features
Quad-Port ESBs
Supports quad-port RAM, dual-port RAM, ROM, CAM, and FIFO buffers
Prioritized Interconnect Structure
Reduces routing delays for speed critical signals to increase performance
Distributed Multiplier Circuitry
Provides 100-MHz, 16 x 16 non-pipelined, push-button performance
Flip-Chip Technology
Increased I/O performance and I/O count, in board-space-saving FineLine BGA packages
Advanced 0.15-µm, 1.8-V
Copper Process
Improved performance over traditional aluminum process technologies
Altera Corporation
11
F
FPGAs with Embedded
Processors
Figure 9. Excalibur EPXA10 Device Features
Dual-Port RAM
Single-Port RAM ARM922T & Caches
Combining a high-density programmable architecture and a
high-performance hard processor core, Altera's Excalibur™
Stripe
devices give designers cost-effective access to advanced
processor technologies. Excalibur devices span the
performance domain up to 200 MHz, providing high-speed
processing power with FPGA flexibility, a true SOPC solution.
Applications
■ Industrial Control
■ Factory Automation
■ Medical Imaging
■ Wireless Basestations
Programmable Logic
Excalibur FPGAs
Removing processor guesswork and allowing engineers to
focus on the fast completion of complex system solutions,
provide interfaces to the logic portion of the devices.
Excalibur devices combine an industry-standard
Figure 9 shows the Excalibur EPXA10 device architecture.
ARM922T™ hard processor, along with memory and peripherals, with an APEX device-like programmable architecture.
FPGAs with Embedded Processors
Through partnership with ARM Ltd.,
The ARM processor core in Excalibur devices
operates at speeds of up to 200 MHz, equivalent
to 210 Dhrystone MIPS. The integrated SDRAM
Altera offers the ARM922T RISC
controller supports SDR or DDR SDRAM at up to 133 MHz
processor core embedded into a stripe
or 266 MHz, respectively, and the device supports up to
on the FPGA. The stripe contains the
512 Mbytes of SDRAM. In addition, the device offers an
processor with its associated caches
expansion bus interface (compatible with industry-stan-
and memory management units (MMUs), dual-port and
dard flash memory), SRAM, and memory-mapped peripher-
single-port SRAM memory, peripherals, and debugging
als. The expansion bus interface can support up to four
modules. The industry-standard AMBA™ high-performance
external devices, each up to 32 Mbytes. Table 8 describes
bus (AHB) architecture allows full operation speed through
some Excalibur device highlights.
the stripe, and dedicated bus bridges and dual-port SRAM
Table 8. Excalibur Highlights
12
FEATURE
BENEFIT
200-MHz ARM922T RISC CPU
with 8-Kbyte Instruction, 8-Kbyte
Data Caches, and an MMU
Optimizes industry-standard processor performance on a PLD; MMU support for multi-threaded
real-time operating systems (RTOS) applications running on Excalibur SOPC designs
Memory and Peripherals
Integrates ready-to-use SRAM/DPRAM, UART, 32-bit timer, watchdog timer, and memory controllers
Optimized Integration with FPGA
Provides access to Altera and third-party IP and I/O standards such as PCI, PCI-X, LVDS, SSTL-3,
and GTL+ for complex designs
JTAG and ETM9 Debug Interfaces
Allows on-chip debugging and tracing through dedicated signals
SOPC Builder Development Tool
Intuitive graphical user interface allows selection of peripherals, interfaces, processors, and
bridges, and generates custom design including on-chip bus logic and custom software library
Excalibur Solutions Pack
Supplements Altera development tools with third-party demonstration software support for
RTOS and debuggers, and reference designs for target applications
Vertical Migration from EPXA1 to
EPXA4 Devices and EPXA4 to
EPXA10 Devices
Addresses device density migration by leveraging existing design investments
Altera Corporation
C
CPLDs
switching time of outputs that are not speed-critical.
Additionally, a programmable power-saving feature allows
Altera CPLDs feature instant-on, non-volatility for simple
for 50% or greater power reduction.
logic integration for a wide variety of digital applications.
The easy-to-use Altera CPLDs contain deterministic routing
MAX 7000 devices are well-suited for mixed-voltage
that guarantees fast, fixed, and predictable pin-to-pin
environments, offering 2.5-V, 3.3-V, or 5.0-V core supply
(propagation) delays. These general-purpose devices range
operation and MultiVolt I/O operation to interface with
in density from 32 to 512 macrocells. A comparison of
1.8-V, 2.5-V, 3.3-V, and 5.0-V devices. Table 9 describes
MAX® device voltages and features is shown in Figure 10.
some MAX 7000 device highlights.
MAX 7000AE CPLDs
Applications
■ Infotainment
■ Set-Top Boxes
■ Storage Servers
■ 3G Basestations
The popular MAX 7000AE devices are the industrystandard 3.3-V CPLD family. Fabricated on a 0.3-µm,
four-layer-metal process, these devices provide very fast
propagation delays. MAX 7000AE devices include an
enhanced ISP algorithm for faster programming times, an
ISP done-bit to ensure complete programming, and a
pull-up resistor on the I/O pins during ISP.
MAX 7000 CPLDs
Fabricated on a sophisticated CMOS EEPROM process, the
Figure 10. MAX Device Features & Voltage Comparison
MAX 7000 family is a fast, easy-to-use programmable
logic solution. Because of its flexibility and simple
MAX 7000B
programming requirements, MAX 7000 devices are the
t PD = 3.5 ns
world's most popular CPLD architecture.
MAX 7000 devices provide a rich feature
MAX 7000AE
Features
t PD = 4.5 ns
set that includes global clocking, fast
MAX 3000A
input registers, and programmable slew-
MAX 7000S
t PD = 5.0 ns
t PD = 4.5 ns
rate control. High-speed global clocks
coupled with 3.5-ns propagation delays and fast clock-toout times create superior system performance with high-
2.5 V
3.3 V
5.0 V
Voltage
speed, device-to-device communication. The programmable
slew-rate control reduces system noise by slowing the
FPGAs with High-Speed
CPLDs
Processors
Table 9. MAX 7000 Highlights
FEATURE
BENEFIT
32 to 512 Macrocells
Offers density to meet a wide range of needs
3.5-ns Propagation Delays
Provides fast system performance
1.8-V I/O Interface
Supports emerging 1.8-V systems
Support for Advanced I/O Standards Supports GTL+ and SSTL-2/-3 I/O standards
Programmable Power-Saving Mode
Reduces power consumption by over 50%
Vertical and SameFrame™ Migration Addresses changing density and I/O needs without the need to re-spin the board
Altera Corporation
13
MAX 7000B CPLDs
MAX 7000S CPLDs
MAX 7000B devices feature a wide array of supported
MAX 7000S devices feature 5.0-V core supply operation
I/O standards in an instant-on CPLD. Fabricated on a
and are ideal for system-level integration. With 5.0-V ISP,
0.22-µm, four-layer-metal EEPROM process, MAX 7000B
these devices are pin-, function-, and programming-file-
devices offer 1.8-V I/O compatibility. Maintaining pin
compatible with all MAX 7000 family members.
compatibility with MAX 7000S and MAX 7000AE
devices, MAX 7000B devices offer designers a seamless
MAX 3000 CPLDs
path to lower voltages, faster propagation times, and
The cost-optimized MAX 3000 devices are the ideal
compatibility with new I/O standards. MAX 7000B
choice for high-volume systems. Featuring the packages,
devices offer propagation delays as fast as 3.5 ns and
densities, and propagation delays customers need,
counter-frequencies of over 300 MHz.
MAX 3000 devices provide designers with exceptional
Altera offers five high-performance MAX 7000B devices
performance at the lowest price per macrocell among
that feature 2.5-V ISP and support the following
MAX devices. The 3.3-V MAX 3000 devices have an
advanced I/O standards: LVCMOS, LVTTL, GTL+, SSTL-2,
enhanced ISP feature set and range in density from 32 to
and SSTL-3.
512 macrocells. Table 10 describes some MAX 3000A
device highlights.
Table 10. MAX 3000 Highlights
BENEFIT
Low Price per Macrocell
Ideal for low-cost, high-volume applications
4.5-ns Propagation Delays
Provides fast system performance
CPLDs
FEATURE
14
Altera Corporation
C
Configuration Devices
Altera's configuration devices provide flexible solutions for
configuring all Altera FPGAs and meet a broad array of
requirements. Altera’s configuration devices enable remote
system upgrades, provide ISP, allow unused memory to be
used as general-purpose memory, and dramatically reduce
The serial configuration device family provides memory
densities at 1 Mbits and 4 Mbits, and are offered in an 8-pin
small-outline package. Table 11 describes some serial
configuration device highlights.
Enhanced Configuration Devices
Altera’s configuration devices provide a simple and
configuration times.
complete solution for configuring its FPGA devices.
Serial Configuration Devices
Ideally suited to the Cyclone FPGA family, Altera's new
serial configuration devices enable an FPGA and configuration device combination that provides a total SOPC solution
at the lowest possible cost. Specifically engineered for maxi-
Manufactured on either an EPROM or a flash process,
these feature-rich devices offer ISP, dynamic configuration,
external flash interface, a programmable clock, parallel
programming, fast programming times, and small formfactor packages.
mum efficiency, they deliver an advanced feature set while
The enhanced configuration devices—EPC4, EPC8, and
minimizing costs. Featuring ISP and reprogramming capa-
EPC16—are based on a flash process and utilize a patented
bilities at a cost even lower than one-time-programmable
data compression technology to effectively double the
solutions, Altera’s serial configuration devices provide a
amount of configuration memory, providing up to 30 Mbits
significant advantage over other configuration solutions.
in a package that is less than 1 square centimeter. A single
Configuration devices have been relatively expensive compared to low-cost FPGAs, costing between 30 to 50% of
EPC16 device is sufficient to configure one Stratix EP1S80
device or up to seven APEX EP20K400C devices.
the FPGA cost. While the price of a low-cost FPGA may
All of Altera’s SRAM-based devices interface seamlessly
have been low enough to address most price-sensitive
with the configuration devices, allowing for a smooth
applications, the cost of an FPGA combined with a config-
configuration without the need for an external controller.
uration device has not been low, resulting in programmable
Through a MultiVolt interface, Altera configuration devices
logic being locked out of these price-sensitive markets.
support operating voltages from 1.8 V to 5.0 V. No matter
Altera's new serial configuration devices were built to
what the system requirements are, a configuration solution
address this issue. Costing on average 10% of the corre-
is available from Altera. Table 12 describes some enhanced
sponding FPGA, serial configuration devices and Cyclone
configuration device highlights.
devices are a perfect solution for cost-sensitive designs.
Table 11. Serial Configuration Device Highlights
FEATURE
BENEFIT
Low Cost
Designed for maximum efficiency; ideal complements to Cyclone FPGAs in creating the lowest
cost SOPC solution
ISP
Increases design flexibility by allowing design updates in-system and reduces costs by streamlining
the manufacturing process
Small Form Factor
Available in a space-saving 8-pin small-outline integrated circuit (SOIC) package
Memory Access
Active serial memory interface with Nios processors allows designers to use any of the memory not
consumed as configuration memory as general purpose memory
Table 12. Enhanced Configuration Device Highlights
BENEFIT
High Density
Provides up to 30 Mbits of configuration memory in less than 1 square centimeter
External Flash Interface
An external flash interface allows designers to use any of the memory not consumed for
configuration as general-purpose memory
Dynamic Configuration
Page mode feature allows dynamic PLD updates by storing multiple configuration files in up to 8
dynamically sized pages in a single configuration device
ISP
Compliant with IEEE Std. 1532, ISP increases design flexibility by allowing design updates in-system
and reduces costs by streamlining the manufacturing process
Altera Corporation
Configuration Devices
FEATURE
15
Device Selector Tables
Tables 13 through 25 list the LE and gate counts, pin/package options, I/O pin counts, supply voltage, RAM bits, and other devicespecific features of Altera PLDs, HardCopy devices, and configuration devices.
Table 13. Stratix Devices1
DEVICE
LOGIC
ELEMENTS
PIN/PACKAGE OPTIONS 2
I/O PINS 2
SUPPLY
VOLTAGE
RAM BITS
DSP
BLOCKS
EP1S10
10,570
484-Pin BGA3, 672-Pin BGA, 672-Pin BGA3, 780-Pin BGA3
335, 345, 345, 426
1.5 V
920,448
6
EP1S20
18,460
484-Pin BGA3, 672-Pin BGA, 672-Pin BGA3, 780-Pin BGA3
361, 426, 426, 586
1.5 V
1,669,248
10
EP1S25
25,660
672-Pin BGA, 672-Pin BGA3, 780-Pin BGA3, 1,020-Pin BGA3
473, 473, 597, 706
1.5 V
1,944,576
10
EP1S30
32,470
780-Pin BGA3, 956-Pin BGA, 1,020-Pin BGA3
589, 683, 726
1.5 V
3,317,184
12
EP1S40
41,250
780-Pin BGA3, 956-Pin BGA, 1,020-Pin BGA3, 1,508-Pin BGA3
615, 683, 773, 822
1.5 V
3,423,744
14
EP1S60
57,120
956-Pin BGA, 1,020-Pin BGA3, 1,508-Pin BGA3
683, 773, 1,022
1.5 V
5,215,104
18
683, 773, 1,203, 1,238
1.5 V
7,427,520
22
1,314
1.5 V
10,118,016
28
EP1S80
79,040
EP1S120
114,140
3
3
956-Pin BGA, 1,020-Pin BGA , 1,508-Pin BGA , 1,923-Pin BGA
3
1,923-Pin BGA3
Notes: 1 The ordering code for Stratix devices is based on the number of LEs; therefore, gate count numbers are not included.
2 Preliminary. Contact Altera for latest information.
3 Space-saving FineLine BGA package.
Table 14. APEX 20K Devices
DEVICE
GATES
PIN/PACKAGE OPTIONS
I/O PINS
SUPPLY
VOLTAGE
LOGIC
ELEMENTS
RAM BITS
EP20K30E
30,000
144-Pin TQFP
92
1.8 V
1,200
24,576
EP20K60E
60,000
144-Pin TQFP, 144-Pin BGA1, 208-Pin PQFP, 324-Pin BGA1,
92, 93, 148, 196, 196
1.8 V
2,560
32,768
144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP,
101, 159, 189,
2.5 V
4,160
53,248
324-Pin BGA1, 356-Pin BGA
252, 252
144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 324-Pin BGA1,
92, 151, 183, 246,
1.8 V
4,160
53,248
356-Pin BGA
246
144-Pin TQFP, 208-Pin PQFP, 240-Pin PQFP, 356-Pin BGA,
88, 143, 175, 271,
1.8 V
6,400
81,920
484-Pin BGA1
316
356-Pin BGA
EP20K100
EP20K100E
EP20K160E
EP20K200
EP20K200E
100,000
100,000
160,000
200,000
208-Pin RQFP, 240-Pin RQFP, 356-Pin BGA, 484-Pin BGA1
144, 174, 277, 382
2.5 V
8,320
106,496
200,000
BGA1,
136, 168, 271, 376,
1.8 V
8,320
106,496
208-Pin PQFP, 240-Pin PQFP, 356-Pin BGA, 484-Pin
652-Pin BGA, 672-Pin BGA1
376, 376
EP20K200C
200,000
208-Pin PQFP, 240-Pin PQFP, 356-Pin BGA, 484-Pin BGA1
136, 168, 271, 376
1.8 V
8,320
106,496
EP20K300E
300,000
240-Pin PQFP, 652-Pin BGA, 672-Pin BGA1
152, 408, 408
1.8 V
11,520
147,456
BGA1
EP20K400
400,000
652-Pin BGA, 672-Pin
502, 502
2.5 V
16,640
212,992
EP20K400E
400,000
652-Pin BGA, 672-Pin BGA1
488, 488
1.8 V
16,640
212,992
EP20K400C
400,000
652-Pin BGA, 672-Pin
BGA1
488, 488
1.8 V
16,640
212,992
EP20K600E
600,000
652-Pin BGA, 672-Pin BGA1, 1,020-Pin BGA1
488, 508, 588
1.8 V
24,320
311,296
BGA1
488, 508, 588
1.8 V
24,320
311,296
652-Pin BGA, 672-Pin BGA1, 1,020-Pin BGA1
488, 508, 708
1.8 V
38,400
327,680
488, 508, 708
1.8 V
38,400
327,680
488, 808
1.8 V
51,840
442,368
EP20K600C
EP20K1000E
600,000
1,000,000
652-Pin BGA, 672-Pin
BGA1,
BGA1,
1,020-Pin
EP20K1000C
1,000,000
652-Pin BGA, 672-Pin
EP20K1500E
1,500,000
652-Pin BGA, 1,020-Pin BGA1
1,020-Pin
BGA1
Note: 1 Space-saving FineLine BGA package.
16
Altera Corporation
Table 15. APEX II Devices1
DEVICE
PIN/PACKAGE OPTIONS
I/O PINS
SUPPLY
VOLTAGE
LOGIC
ELEMENTS
RAM BITS
EP2A15
724-Pin BGA, 672-Pin BGA2
492, 492
1.5 V
16,640
425,984
EP2A25
724-Pin BGA, 672-Pin BGA2
540, 492
1.5 V
24,320
622,592
EP2A40
724-Pin BGA, 672-Pin BGA2, 1,020-Pin BGA2
540, 492, 735
1.5 V
38,400
655,360
EP2A70
724-Pin BGA, 1,508-Pin BGA2
540, 1,060
1.5 V
67,200
1,146,880
Notes: 1 The ordering code for APEX II devices is based on the number of LEs; therefore, gate count numbers are not included.
2 Space-saving FineLine BGA package.
Table 16. HardCopy Devices1
DEVICE
GATES
PIN/PACKAGE OPTIONS
I/O PINS
SUPPLY
VOLTAGE
LOGIC
ELEMENTS
RAM BITS
HC20K400
400,000
652-Pin BGA, 672-Pin BGA2
488, 488
1.8 V
16,640
212,992
HC20K600
600,000
652-Pin BGA, 672-Pin BGA2
488, 508
1.8 V
24,320
311,296
HC20K1000
1,000,000
652-Pin BGA, 672-Pin
BGA2,
488, 508, 708
1.8 V
38,400
327,680
HC20K1500
1,500,000
652-Pin BGA, 1,020-Pin BGA2
488, 808
1.8 V
51,840
442,368
622,592
1,020-Pin
BGA2
HC2A25
900,000
724-Pin BGA, 672-Pin BGA2, 1,020-Pin BGA2
536, 492, 612
1.5 V
24,320
HC2A40
1,500,000
724-Pin BGA, 672-Pin BGA2, 1,020-Pin BGA2
536, 492, 735
1.5 V
38,400
655,360
HC2A70
3,000,000
724-Pin BGA, 1,508-Pin BGA2
536, 1,060
1.5 V
67,200
1,146,880
Note: 1 Stratix HardCopy™ devices to be added in Q3 2003.
2 Space-saving FineLine BGA package.
Table 17. Cyclone Devices
DEVICE
LOGIC ELEMENTS
2,910
EP1C3
PIN/PACKAGE OPTIONS
I/O PINS
100-Pin TQFP, 144-Pin TQFP
1
SUPPLY
VOLTAGE
RAM BITS
65, 104
1.5 V
59,904
EP1C6
5,980
98, 185, 185
1.5 V
92,160
EP1C12
12,060
240-Pin PQFP, 256-Pin Fineline BGA1, 324-Pin Fineline BGA1
173, 185, 249
1.5 V
239,616
EP1C20
20,060
324-Pin Fineline BGA1, 400-Pin Fineline BGA1
233, 301
1.5 V
294,912
Note:
1
144-Pin TQFP, 240-Pin PQFP, 256-Pin Fineline BGA
Space-saving FineLine BGA package.
Table 18. ACEX Devices
DEVICE
GATES
PIN/PACKAGE OPTIONS
I/O PINS
SUPPLY
VOLTAGE
LOGIC
ELEMENTS
RAM BITS
EP1K10
10,000
100-Pin TQFP, 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA1
66, 92, 120, 136
2.5 V
576
12,288
EP1K30
30,000
144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA1
102, 147, 171
2.5 V
1,728
24,576
EP1K50
50,000
144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA1, 484-Pin BGA1
102, 147, 186, 249
2.5 V
2,880
40,960
EP1K100
100,000
208-Pin PQFP, 256-Pin BGA1, 484 Pin BGA1
147, 186, 333
2.5 V
4,992
49,152
Note:
1
Space-saving FineLine BGA package.
Altera Corporation
17
Table 19. Stratix GX Devices
DEVICE
LOGIC
ELEMENTS
TRANSCEIVER
CHANNELS
PIN/PACKAGE
OPTIONS
I/O PINS
SUPPLY
VOLTAGE
RAM BITS
SOURCE-SYNCHRONOUS
CHANNELS
EP1SGX10C
10,570
4
672-Pin BGA1
330
1.5 V
920,488
22
EP1SGX10D
10,570
8
672-Pin BGA1
330
1.5 V
920,488
22
BGA1
426
1.5 V
1,944,576
39
426, 542
1.5 V
1,944,576
39
BGA1
EP1SGX25C
25,660
4
672-Pin
EP1SGX25D
25,660
8
672-Pin BGA1, 1,020-Pin BGA1
EP1SGX25F
25,660
16
542
1.5 V
1,944,576
39
EP1SGX40D
41,250
8
1,020-Pin BGA1
544
1.5 V
3,423,744
45
20
BGA1
544
1.5 V
3,423,744
45
EP1SGX40G
Note:
1
41,250
1,020-Pin
1,020-Pin
Space-saving FineLine BGA package.
Table 20. Mercury Devices
DEVICE
GATES
EP1M120
120,000
484-Pin BGA1
303
1.8 V
8
4,800
49,152
EP1M350
350,000
780-Pin BGA1
486
1.8 V
18
14,400
114,688
I/O PINS
PIN/PACKAGE OPTIONS
SUPPLY
VOLTAGE
CDR
CHANNELS
LOGIC
ELEMENTS
RAM BITS
Note: 1 Space-saving FineLine BGA package.
Table 21. Excalibur Devices
DEVICE
GATES
EPXA1
100,000
EPXA4
400,000
EPXA10
I/O PINS
PIN/PACKAGE OPTIONS
1,000,000
484-Pin BGA1, 672-Pin BGA1
672-Pin
BGA1,
1,020-Pin
SUPPLY
VOLTAGE
LOGIC
ELEMENTS
1.8 V
186, 246
BGA1
1,020-Pin BGA1
RAM
BITS
EMBEDDED
PROCESSOR
4,160
53,248
32-bit ARM922T
32-bit ARM922T
32-bit ARM922T
434, 496
1.8 V
16,640
212,992
711
1.8 V
38,400
327,680
Note: 1 Space-saving FineLine BGA package.
Table 22. MAX 7000 Devices
DEVICE
EPM7032S
EPM7032AE
MACROCELLS
PIN/PACKAGE OPTIONS
I/O PINS
SUPPLY
VOLTAGE
SPEED GRADE
32
44-Pin PLCC/TQFP
36
5.0 V
-5, -6, -7, -10
36
3.3 V
-4, -7, -10
32
44-Pin PLCC/TQFP
EPM7032B
32
44-Pin PLCC/TQFP, 49-Pin BGA2
36, 36
2.5 V
-3, -5, -7
EPM7064S
64
44-Pin PLCC/TQFP, 84-Pin PLCC, 100-Pin TQFP
36, 68, 68
5.0 V
-5, -6, -7, -10
EPM7064AE
64
44-Pin PLCC/TQFP, 100-Pin TQFP, 100-Pin BGA1
36, 68, 68
3.3 V
-4, -7, -10
EPM7064B
64
44-Pin TQFP, 49-Pin BGA2, 100-Pin TQFP, 100-Pin BGA1
36, 41, 68, 68
2.5 V
-3, -5, -7
EPM7128S
128
84-Pin PLCC, 100-Pin PQFP/TQFP, 160-Pin PQFP
68, 84, 100
5.0 V
-6, -7, -10, -15
EPM7128AE
128
84-Pin PLCC, 100-Pin TQFP, 100-Pin BGA1, 144-Pin TQFP, 256-Pin BGA1
68, 84, 84, 100, 100
3.3 V
-5, -7, -10
EPM7128B
128
100-Pin TQFP, 100-Pin BGA1, 144-Pin TQFP, 256-Pin BGA1
84, 84, 100, 100
2.5 V
-4, -7, -10
EPM7160S
160
84-Pin PLCC, 100-Pin TQFP, 160-Pin PQFP
64, 84, 104
5.0 V
-6, -7, -10
EPM7192S
192
160-Pin PQFP
124
5.0 V
-7, -10, -15
256
208-Pin PQFP/RQFP
164
5.0 V
-7, -10, -15
256
100-Pin TQFP, 100-Pin BGA1, 144-Pin TQFP, 208-Pin PQFP, 256-Pin BGA1
84, 84, 120, 164, 164
3.3 V
-5, -7, -10
256
100-Pin TQFP, 144-Pin TQFP, 169-Pin BGA2, 208-Pin PQFP, 256-Pin BGA1
84, 120, 141, 164, 164
2.5 V
-5, -7, -10
120, 176, 212, 212
3.3 V
-7, -10, -12
120, 141, 176, 212, 212
2.5 V
-5, -7, -10
EPM7256S
EPM7256AE
EPM7256B
BGA1,
EPM7512AE
512
144-Pin TQFP, 208-Pin PQFP, 256-Pin
EPM7512B
512
144-Pin TQFP, 169-Pin BGA2, 208-Pin PQFP, 256-Pin BGA1, 256-Pin BGA
256-Pin BGA
Notes: 1 1.0-mm pitch FineLine BGA package.
2 0.8-mm pitch Ultra FineLine BGA package.
18
Altera Corporation
Table 23. MAX 3000 Devices
DEVICE
MACROCELLS
EPM3032A
32
44-Pin PLCC/TQFP
EPM3064A
64
44-Pin PLCC/TQFP, 100-Pin TQFP
EPM3128A
128
EPM3256A
EPM3512A
Note:
1
PIN/PACKAGE OPTIONS
I/O PINS
SUPPLY
VOLTAGE
SPEED GRADE
34
3.3 V
-4, -7, -10
34, 66
3.3 V
-4, -7, -10
100-Pin TQFP, 144-Pin TQFP
80, 96
3.3 V
-5, -7, -10
256
144-Pin TQFP, 208-Pin PQFP
116, 158
3.3 V
-7, -10
512
208-Pin PQFP, 256-Pin BGA1
172, 208
3.3 V
-7, -10
1.0-mm pitch FineLine BGA package.
Table 24. Configuration Devices for Stratix, Stratix GX, Cyclone, APEX II, APEX, Excalibur, FLEX, Mercury & ACEX Devices
DEVICE
PIN/PACKAGE OPTIONS
SUPPLY
VOLTAGE
DESCRIPTION
EPC1441
8-Pin PDIP, 20-Pin PLCC, 32-Pin TQFP
3.3 or 5.0 V
441-Kbit configuration device designed to configure all FLEX and ACEX devices
EPC1
8-Pin PDIP, 20-Pin PLCC
3.3 or 5.0 V
1-Mbit configuration device designed to configure APEX, FLEX, and ACEX devices
EPC2
20-Pin PLCC, 32-Pin TQFP
3.3 or 5.0 V
In-system programmable 1.6-Mbit configuration device designed to configure Stratix,
Stratix GX, Cyclone, APEX II, APEX, FLEX, Mercury, ACEX, and Excalibur devices
EPC4
100-Pin PQFP
3.3 V
In-system programmable 4-Mbit configuration device designed to configure
Stratix, Stratix GX, Cyclone, APEX II, APEX, FLEX, Mercury, ACEX, and Excalibur devices
EPC8
100-Pin PQFP
3.3 V
In-system programmable 8-Mbit configuration device designed to configure Stratix,
Stratix, Stratix GX, Cyclone, APEX II, APEX, FLEX, Mercury, ACEX, and Excalibur devices
EPC16
88-Pin BGA1, 100-Pin PQFP
3.3 V
In-system programmable 16-Mbit configuration device designed to configure Stratix,
Stratix, Stratix GX, Cyclone, APEX II, APEX, FLEX, Mercury, ACEX, and Excalibur devices
Note: 1 Ultra FineLine BGA package.
Table 25. Serial Configuration Devices for Cyclone Devices
DEVICE
PIN/PACKAGE
OPTIONS
SUPPLY
VOLTAGE
DESCRIPTION
EPCS1
8-Pin SOIC1
3.3 V
In-system programmable 1-Mbit serial configuration device designed to configure Cyclone devices
EPCS4
8-Pin SOIC
3.3 V
In-system programmable 4-Mbit serial configuration device designed to configure Cyclone devices
Note: 1 Small-outline integrated circuit (SOIC)
Altera Corporation
19
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