®
Features
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General
Description
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Functional
Description
Figure 1. APEX 20KE Development Board
General Purpose
Switches, SW1, SW2
SRAM
Socket, J6
General Purpose
LEDs, LED1, LED2
Alternate LVDS
Header, J1
PMC Connectors
JN1, JN2, JN3, JN4
JTAG Header, J2
External Power
Supply Connector, J3
Dipswitch
Options, S1
Altera
Daughter
Card
Header,
J4, J5, J7
Altera EPC4
Device #1, U5
33 MHz
Oscillator, Z1
RS232, JP1
Altera APEX
Device, U7
50 MHz
Oscillator, Z2
Flash
Memory
Module, U13
Altera
EPM3256A
Device, U9
JTAG/PCI
Options
Header, J8
Altera EPC4
Device #0, U4
APEX 20KE Pin Assignments
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Table 1. Pin Assignment Reference Definitions
Pin Name
Board Components
Definition
a_
p_
!""
s_
#
$%&'( f_
)
*+( lvds_
#,#-),#-
./%$"0
e_
#-,#-,#-),#-
$ '!""
epm3256a_
1
')2
3"4
led
.%,.%
044
0
0.%
pio_
#,#2,#
0
50
06$ 4+
"
""
6
rs232_
#
&$)
3"4
sw_
$7,$7
$8"+"" +
>%"$'$%"
&!".
!''$''&!!%',!& ,
Table 2. APEX 20KE PCI Development Board Pin Assignments (Part 1 of 7)
Signal Name
672-Pin
FineLine BGA
Signal Name
672-Pin
FineLine BGA
a_clk1p
f_d2
7
a_clk2p
-9
f_d3
/
a_clk3p
'1
f_d4
7
a_clk4p
&
f_d5
/
a_clklk_out1p
)
f_d6
7
a_clklk_out2p
:
f_d7
71
a_lock1
.
f_oen
:)
a_lock2
f_rdy_bsyn
:1
a_lock3
.9
f_reset
/9
a_lock4
7
f_sel_pgm0
:2
p_ack64n
;1
f_sel_pgm1
:
p_ad0
f_sel_pgm2
:)
p_ad1
)
f_sel_pgm3
p_ad10
/
f_wen
7
p_ad11
/1
lvds_deskew
p_ad12
7
lvds_rx_clk-
;
p_ad13
7)
lvds_rx_clk+
;2
p_ad14
7
lvds_tx_clk-
p_ad15
<
lvds_tx_clk+
p_ad16
lvds_tx_in_clk-
%
p_ad17
;
lvds_tx_in_clk+
%
p_ad18
7
lvds_tx+0
*
p_ad19
<
lvds_tx+1
=
p_ad2
lvds_tx+10
/
p_ad20
lvds_tx+11
7
p_ad21
;
lvds_tx+12
<
p_ad22
;9
lvds_tx+13
p_ad23
7
lvds_tx+14
;
p_ad24
2
lvds_tx+15
!
p_ad25
/2
lvds_tx+2
>
p_ad26
72
lvds_tx+3
#
p_ad27
<2
lvds_tx+4
p_ad28
;2
lvds_tx+5
.
!
Table 2. APEX 20KE PCI Development Board Pin Assignments (Part 2 of 7)
Signal Name
672-Pin
FineLine BGA
Signal Name
672-Pin
FineLine BGA
p_ad29
:
lvds_tx+6
'
p_ad3
lvds_tx+7
&
p_ad30
lvds_tx+8
:
p_ad31
/
lvds_tx+9
p_ad32
.
lvds_tx-0
*
p_ad33
.)
lvds_tx-1
=
p_ad34
.
lvds_tx-10
/
p_ad35
'
lvds_tx-11
7
p_ad36
')
lvds_tx-12
<
p_ad37
'
lvds_tx-13
p_ad38
'
lvds_tx-14
;
p_ad39
'9
lvds_tx-15
!
p_ad4
lvds_tx-2
>
p_ad40
'
lvds_tx-3
#
p_ad41
-)
lvds_tx-4
p_ad42
-
lvds_tx-5
.
p_ad43
-1
lvds_tx-6
'
p_ad44
-9
lvds_tx-7
&
p_ad45
-
lvds_tx-8
:
p_ad46
-
lvds_tx-9
p_ad46
-
e_ack64n
=)
p_ad47
e_ad0
.1
p_ad48
9
e_ad1
p_ad49
e_ad10
#
p_ad5
1
e_ad11
#
p_ad50
&
e_ad12
>
p_ad51
&)
e_ad13
>
p_ad52
&
e_ad14
>
p_ad53
&
e_ad15
>
p_ad54
&
e_ad16
=
p_ad55
&1
e_ad17
=
p_ad56
&9
e_ad18
=
p_ad57
&
e_ad19
=
p_ad58
:
e_ad2
)
p_ad59
:)
e_ad20
*
p_ad6
/
e_ad21
*
"
Table 2. APEX 20KE PCI Development Board Pin Assignments (Part 3 of 7)
Signal Name
672-Pin
FineLine BGA
Signal Name
672-Pin
FineLine BGA
p_ad60
:
e_ad22
p_ad61
:
e_ad23
)
p_ad62
:
e_ad24
%1
p_ad63
:1
e_ad25
!1
p_ad7
/)
e_ad26
%9
p_ad8
/
e_ad27
!9
p_ad9
/
e_ad28
;9
p_cben0
<
e_ad29
%
p_cben1
e_ad3
p_cben2
/
e_ad30
!
p_cben3
;
e_ad31
;
p_cben4
7
e_ad32
p_cben5
<
e_ad33/lvds_rx0-
p_cben6
<1
e_ad34/lvds_rx1-
<2
p_cben7
e_ad35/lvds_rx0+
2
p_devseln
<
e_ad36/lvds_rx1+
<
p_framen
e_ad37/lvds_rx2-
7
p_gntn
;)
e_ad38/lvds_rx3-
/2
p_idsel
;
e_ad39/lvds_rx2+
72
p_intan
:9
e_ad4
p_irdyn
<)
e_ad40/lvds_rx3+
/
p_lockn
1
e_ad41/lvds_rx4-
p_m66en
.
e_ad42/lvds_rx5-
:2
p_par
9
e_ad43/lvds_rx4+
2
p_par64
1
e_ad44/lvds_rx5+
:
p_perrn
<9
e_ad45/lvds_rx6-
&
p_req64n
;
e_ad46/lvds_rx7-
'2
p_reqn
;
e_ad47/lvds_rx6+
&2
p_rstn
>
e_ad48/lvds_rx7+
'
p_serrn
79
e_ad49/lvds_rx8-
.
p_stopn
7
e_ad5
p_trdyn
<
e_ad50/lvds_rx9-
2
s_a0
e_ad51/lvds_rx8+
.2
s_a1
9
e_ad52/lvds_rx9+
s_a10
>
e_ad53/lvds_rx10-
#
s_a11
=
e_ad54/lvds_rx11-
>2
#
Table 2. APEX 20KE PCI Development Board Pin Assignments (Part 4 of 7)
Signal Name
672-Pin
FineLine BGA
Signal Name
672-Pin
FineLine BGA
s_a12
>
e_ad55/lvds_rx10+
#2
s_a13
=
e_ad56/lvds_rx11+
>
s_a2
*1
e_ad57/lvds_rx12-
=
s_a3
*9
e_ad58/lvds_rx13-
*2
s_a4
=1
e_ad59/lvds_rx12+
=2
s_a5
1
e_ad6
1
s_a6
>
e_ad60/lvds_rx13+
*
s_a7
=
e_ad61/lvds_rx14-
s_a8
*
e_ad62/lvds_rx15-
%2
s_a9
e_ad63/lvds_rx14+
2
s_ba0
e_ad7
#
s_ba1
#
e_ad8
#)
s_casn
2
e_ad9
#
s_cke0
!
e_bm1
'
s_cke1
*
e_bm2
/
s_dq0
:9
e_bm3
2
s_dq1
&1
e_bm4
;2
s_dq10
-1
e_cben0
!)
s_dq11
-
e_cben1
;)
s_dq12
')
e_cben2
!
s_dq13
'
e_cben3
;
s_dq14
'2
e_cben4
*
s_dq15
'
e_cben5
*1
s_dq16
'9
e_cben6
*
s_dq17
'1
e_cben7
*)
s_dq18
'
e_devseln
s_dq19
.)
e_devseln
s_dq2
&
e_framen
%
s_dq20
.
e_gntn
s_dq21
.2
e_gntn
s_dq22
.
e_idsel
s_dq23
.
e_idsel
s_dq24
.9
e_intan
%
s_dq25
.1
e_intbn
s_dq26
)
e_intcn
9
s_dq27
e_intdn
1
$
Table 2. APEX 20KE PCI Development Board Pin Assignments (Part 5 of 7)
Signal Name
672-Pin
FineLine BGA
Signal Name
672-Pin
FineLine BGA
s_dq28
2
e_irdyn
!
s_dq29
e_lockn
s_dq3
&
e_m66en
s_dq30
e_par
)
s_dq31
9
e_par
)
s_dq32
#
e_par64
%
s_dq33
#2
e_perrn
!
s_dq34
#
e_req64n
>)
s_dq35
#
e_reqn
9
s_dq36
#9
e_reqn
9
s_dq37
>)
e_rstn
*)
s_dq38
>
e_sbo
%2
s_dq39
>2
e_sdone
%
s_dq4
&)
e_serrn
%
s_dq40
=2
e_stopn
;
s_dq41
=
e_trdyn
%
s_dq42
=
epm3256a_data
.
s_dq43
=9
epm3256a_status
2
s_dq44
*)
epm3256a_sync
#
s_dq45
)
led0
=
s_dq46
*
led1
>
s_dq47
led2
#
s_dq48
>1
led3
=9
s_dq49
*
led4
>9
s_dq5
led5
9
s_dq50
led6
=1
s_dq51
#
led7
#1
s_dq52
)
pio_activity
%
s_dq53
#
pio_addr0
s_dq54
pio_addr1
s_dq55
2
pio_addr2
*1
s_dq56
*2
pio_bale
!
s_dq57
=2
pio_chipsel0n
*
s_dq58
>2
pio_chipsel1n
*
s_dq59
#2
pio_d0
!
s_dq6
2
pio_d1
!2
%
Table 2. APEX 20KE PCI Development Board Pin Assignments (Part 6 of 7)
Signal Name
672-Pin
FineLine BGA
Signal Name
672-Pin
FineLine BGA
s_dq60
pio_d2
!
s_dq61
*
pio_d3
s_dq62
=
pio_d4
!
s_dq63
>
pio_d5
%
s_dq7
9
pio_d6
%9
s_dq8
1
pio_d7
%1
s_dq9
-2
pio_dack3
%9
s_dqmb0
>
pio_drq3
s_dqmb1
=)
pio_e
!)
s_dqmb2
*
pio_hostdata0
*
s_dqmb3
)
pio_hostdata1
s_dqmb4
>
pio_hostdata10
!2
s_dqmb5
=
pio_hostdata11
!
s_dqmb6
pio_hostdata12
%2
s_dqmb7
#)
pio_hostdata13
%
s_rasn
*2
pio_hostdata14
2
s_s0n
pio_hostdata15
*2
s_s1n
*
pio_hostdata2
%
s_scl
>)
pio_hostdata3
%
s_sda
pio_hostdata4
!
s_wen
%2
pio_hostdata5
;
f_a0
7
pio_hostdata6
f_a1
7)
pio_hostdata7
<
f_a10
;1
pio_hostdata8
)
f_a11
1
pio_hostdata9
;)
f_a12
<1
pio_iochrdy
!1
f_a13
;9
pio_iocs16n
1
f_a14
9
pio_iorn
!9
f_a15
<9
pio_iown
*
f_a16
;
pio_irq14
%1
f_a17
pio_reset_ide
<)
f_a18
<
pio_rs
!
f_a19
;
pio_rw
!
f_a2
;
rs232_cd
2
f_a20
rs232_cts
/)
f_a21
<
rs232_dsr
*)
&
Table 2. APEX 20KE PCI Development Board Pin Assignments (Part 7 of 7)
Signal Name
672-Pin
FineLine BGA
Signal Name
672-Pin
FineLine BGA
f_a3
<
rs232_dtr
*
f_a4
;
rs232_ri
7
f_a5
rs232_rts
7)
f_a6
<
rs232_rx
f_a7
;
rs232_tx
/2
f_a8
sw_gp0
&9
f_a9
<
sw_gp1
&2
f_cen
<2
sw_rsvd0
*
f_d0
/)
sw_rsvd1
*9
f_d1
)
LVDS-Capable Signals
9-:8'!&!''"$"!
%"
"'(&!"'@A+.@A0*"9-!"
(&!"@*,"
"!&%$"'
/0&
)''$!'"/ 9-!!!'! 9-,%"
"!&%$"'/
9-!!!'!9-,!&' +!0'
%"
"'+!0.!"'%"9-,
Table 3. PMC Connector 3 (LVDS RX) (Part 1 of 2)
Pin
Side B Signals
Side A Signals
Pin
reserved
gnd
)
gnd
reserved
2
reserved
reserved
reserved
gnd
9
1
+3.3v
lvds_rx15+
lvds_rx14+
lvds_rx15-
)
lvds_rx14-
gnd
2
gnd
lvds_rx13+
lvds_rx12+
lvds_rx13-
9
1
lvds_rx12-
gnd
+3.3v
lvds_rx11+
)
lvds_rx10+
lvds_rx11-
2
lvds_rx10-
gnd
Table 3. PMC Connector 3 (LVDS RX) (Part 2 of 2)
Pin
Side B Signals
Side A Signals
Pin
gnd
lvds_rx9+
9
1
lvds_rx8+
lvds_rx9-
)
)
lvds_rx8-
gnd
)
))
gnd
lvds_rx7+
)
)2
lvds_rx6+
lvds_rx7-
)
)
lvds_rx6-
gnd
)9
)1
+3.3v
lvds_rx5+
lvds_rx4+
lvds_rx5-
)
lvds_rx4-
gnd
2
gnd
lvds_rx3+
lvds_rx2+
lvds_rx3-
9
1
lvds_rx2-
gnd
2
2
gnd
lvds_rx1+
2
2)
lvds_rx0+
lvds_rx1-
2
22
lvds_rx0-
gnd
2
2
+3.3v
ad[32]
29
21
lvds_rx_clk+
lvds_deskew
lvds_rx_clk-
gnd
)
gnd
reserved
Table 4. PMC Connector 4 (LVDS TX) (Part 1 of 2)
Pin
Side B Signals
Side A Signals
Pin
reserved
gnd
)
gnd
reserved
2
reserved
reserved
reserved
gnd
9
1
gnd
lvds_tx15+
lvds_tx14+
lvds_tx15-
)
lvds_tx14-
gnd
2
gnd
lvds_tx13+
lvds_tx12+
lvds_tx13-
9
1
lvds_tx12-
gnd
gnd
lvds_tx11+
)
lvds_tx10+
lvds_tx11-
2
lvds_tx10-
gnd
gnd
lvds_tx9+
9
Table 4. PMC Connector 4 (LVDS TX) (Part 2 of 2)
Pin
Side B Signals
Side A Signals
Pin
1
lvds_tx8+
lvds_tx9-
)
)
lvds_tx8-
gnd
)
))
gnd
lvds_tx7+
)
)2
lvds_tx6+
lvds_tx7-
)
)
lvds_tx6-
gnd
)9
)1
gnd
lvds_tx5+
lvds_tx4+
lvds_tx5-
)
lvds_tx4-
gnd
2
gnd
lvds_tx3+
lvds_tx2+
lvds_tx3-
9
1
lvds_tx2-
gnd
2
2
gnd
lvds_tx1+
2
2)
lvds_tx0+
lvds_tx1-
2
22
lvds_tx0-
gnd
2
2
gnd
reserved
29
21
lvds_tx_clk+
reserved
lvds_tx_clk-
gnd
)
gnd
reserved
!"!9-!"'!!!&!''0 !0!!
!'! !',!"!!""'!''
9-'$!'$!
)!'!",1".
9-!"!#&'&#'!$"''"'
!"B'9-',9-&!""!'!"
2%"
9-,C'!$"''"''"
!"!9-!".
9-'$!'!&',!& 3
''%"!"!9-!",
Table 5. Alternate LVDS Header Pinout (Part 1 of 2)
Pin
Function
Function
Pin
+3.3v
gnd
)
+3.3v
gnd
2
lvds_rx+0
lvds_rx-0
lvds_rx+1
lvds_rx-1
9
1
gnd
gnd
lvds_rx+2
lvds_rx-2
)
lvds_rx+3
lvds_rx-3
Table 5. Alternate LVDS Header Pinout (Part 2 of 2)
Pin
Function
Function
Pin
2
gnd
gnd
lvds_rx_clk+
lvds_rx_clk-
9
1
gnd
deskew
reserved
gnd
)
lvds_tx_clk-
lvds_tx_clk+
2
gnd
gnd
lvds_tx-3
lvds_tx+3
9
1
lvds_tx-2
lvds_tx+2
)
)
gnd
gnd
)
))
lvds_tx-1
lvds_tx+1
)
)2
lvds_tx-0
lvds_tx+0
)
)
gnd
reserved
)9
)1
gnd
reserved
6$" ''!"!9-"''"!,
Figure 2. Alternate LVDS Option Resistor Placement
Alternate
APEXLVDS
Device
rx_data[3..0]
PMC
APEX
#3
Device
rx_clk
tx_data[3..0]
APEX
Device
tx_clk
PMC
APEX
#4
Device
rx_data[3..0]
rx_clk
tx_data[3..0]
tx_clk
Optional Resistors,
Not Installed by Default
Voltage Supply Circuit
&!"!''!!$'#
""#.!'''!"#,<-"'#&$"!
%"!+,+ -,B'"!""#"'
,< -!:8&!'"+,+ -,
&!"!!+,+-%""
""!
)"!"'#,
1
D'$)"!"'#
&!"'$$
"'
!#"''"&!"!!$E"''&#'#'!!$,
Programming and Configuration
!&%$"!!%$"!%'"
%&!"
0'.!%$"!%'"&!"
0>#%!'"#."&#!$!%$"!%
"$!'">!'":>#>!'"-!!&,C
%$"$%""!
0"!%!'
"#.%$"!"'''"&#!"!
+3/,F8>!"
%$"!6G,C
%$"$!!'">!'":>#>!'"-!".@H
!'',6""%"!@H%$"!!
'.'F@H
%$"!:"$"!$!>
!G!$
/,
On-Board Configuration File Selection
!%)&#%$"$.
%$"!%'!&'"&!""#.,,."
"!
0%$"!'"0>#%!'"#
,"!+3/''"%$"!
"''!'&!"%$"!%!,
6$" +''!&!$"!%&!"%$"!%
'",
!
Figure 3. Configuration Circuit Block Diagram
EPC4
Device
EP20K200E
EP20K400E
EP20K1000E
EPC4
Device
VCC VCC VCC VCC
EPM3256A
Configuration
Controller
Configuration
DIP Switches
GND GND GND GND
50-MHz OSC
Byte-Wide
32-MByte
Flash
!& /''''$!'"%"!&
!+3/%$"!"",'$!'
""%$"!%, Table 6. Reconfiguration Control Signals
Signal Name
Function
cfg_strobe
+
4 43cfg_strobe,
"34
8++0
(
3+
(4
"34?[46:+cfg_strobe40 06
cfg_sel_epc4_flashn
7+4","34
""
3
(+3+
((
5 "67+4","34
""
3
(3+! "6
cfg_sel_epc4_1_0n
7+4",+cfg_sel_epc4_1_0n"
! "@8+4",+
cfg_sel_epc4_1_0n"! "6
cfg_flash_pgm[3..0]
7+"34
43
(3+((
5,+
cfg_flash_pgm[3..0]4"++4+
3+3+((
5 "6:+
cfg_flash_pgm[3..0]4(A 5+
3
(
06
"
8".'%$"!%!%$"!
%'&#'$''''
(&!"@<*,C''8'.!FG'
'%",C''8%%'.!FG'
'%",!& 7'!"2''',
Table 7. Dipswitch Options
Dipswitch(s)
Function
def_flash_pgm[3..0]
%08"+B66C
:"30 33
"34
0
4
(,+
def_flash_pgm[3..0]"
++4+ 3+58 3+
((
56
sel_epc4_flashn
%08"+2
7+4",sel_epc4_flashn"08
"34
3
(+!
"67+4",sel_epc4_flashn"08
"34
3
(+
3+((
5 "6
epc4_sel1_0n
%08"+
:+epc4_sel1_0n"8+"+! " 4!08
"34
67+4",epc4_sel1_0n"! "(
67+
4",epc4_sel1_0n"! "(
6
%08"+B66C
&
3
3
6
D/%$"!%'!#&'
def_flash_pgm[3..0]'',def_flash_pgm3'
''$%!'!""''%!'"#!"''&
Idef_flash_pgm0'!''$%!'!
""''%!'"#!"''&<,!& <'''
'$'%"%%"'',
Table 8. Dipswitch Settings
APEX Device
Valid Switches
Number of Available Files
def_flash_pgm[3..0] def_flash_pgm[3..1] 9
def_flash_pgm3
JTAG Configuration/Programming and BST Chain
&!"''"$@H&!"#'!'$(>*
!"$"!@H!,
!'">!'":>#>!'"-!".
0'.+3/
%$"!""..!
!"''"
@H>,@H!4"'!"""'"
&#!''"'"!%@H'!,%!'
#'!#"'&!".'&@H!,
6$" 0''@H!&!$"!,'!
!!!&&#!''',
#
Figure 4. JTAG Chain Block Diagram
EPC4
Device #1
EPM3256A
Configuration
Controller
EPC4
Device #0
PMC
Headers
APEX
EP20K200E
EP20K400E
EP20K1000E
ByteBlasterMV
Header
@H"!'">!'":>#>!'"-!"''
""%$""""$"!
0''$
J!"'"K9D;'%!",
0!"'"'@H!
'(&!"
*,'<!"''%#@H'
&!"&@H!,!&' L''!!!&@H
',
Table 9. Jumper Settings for JTAG Options
Pin Numbers
State
Function
33
')2 "50
')2 "" )
33
! "D50
! "D" 2
33
! "D50
! "D" 9
33
'!50
'!" !!!!&
"%!!!&'.4"'!"
!!!&!"%$"!%//A!
!!&'
',!& ''4"'$'%"
', Table 10. Jumper Settings for PCI Options (Part 1 of 2)
PCI Interface Operation
Pin Numbers
State
!6))'>E0
1,)
33
!6'>E0
1
,)
33
$
Table 10. Jumper Settings for PCI Options (Part 2 of 2)
PCI Interface Operation
!'>E0
!'>E0
Pin Numbers
State
1,)
33
1,,)
33
Clock Selection and Configuration Options
!!!"!$%'"%$"!'.
&!""'%)&%$"!!
"''"', ''"'!&"'"$',
8'%"&'!'!'
'E"'#''E!"",
Clock Input Selection
''"' !"!!.)"!!'
(99*2"!#&%%".''"%"apex_clk2p
'$!,6$" 3'''!$"!!'!'
"''"',
Figure 5. APEX Clock Input Selection Diagram
clk_daughter_osc
VCC
APEX Source Clock Selection
A
GND
B
VCC
OE
clk_apex_clk0
Output
clk_osc_socket
C
clk_pci_edge
D
clk_apex_clk1
GND
GND
2clk_pci_edge
R
pll_clk_input
S
%
'!%"!',!& ''
'"',
Table 11. APEX Clock Input Source Selection
APEX Clock Input
Note (1)
Clock Source
')2"34
"
"
apex_clk1p
apex_clk2p
:+apex_clk2p4"34
8+
08+"+
F"+("(Gclk_osc_extra) " 3
(+
+
"
5"
+!""
6
7+
& ,"A0"" +"
5"
6
7+
$ ,"A0"" +!5(""A6
apex_clk3p
F"+("(Gclk_apex_clk0H
:+apex_clk3p4"34
8+
08+"+
" 3
(+
+
"
5"
+! 4
34
67+
,"A)0"" +"
5
"
67+
; ,"A)0"" +!
5(""A6
apex_clk4p
F"+("(Gclk_apex_clk1H
:+apex_clk4p4"34
8+
08+"+
" 3
(+
+
"
5"
+! 4
34
67+
! ,"A0"" +"
5
"
67+
% ,"A0"" +!
5(""A6
(*
&!
!"'H"B'(H*
!#%"''"'>.."!&'!,6$" 3,
f
"!%"''"'!& .'F!'G
!$/,
&
Clock Output Selection
"&!"$.'"'!#!:"!#B'
'!"!99""#&%"&$
99',"!"''"'!"%!%
'"&%%"',!)
%"?#'"&#&"%'!!'
"$,8"%"!'&!!B'
'"$!'$,6$" /''
'!$"!,
Figure 6. APEX Clock Output Selection Diagram
pll_clk_output
pll_clk_output
Module Source Clock Selection
clk_apex_clkout0
clk_apex_clkout1
E
clk_daughter_card
F
pll_clk_output
G
H
clk_pmc
J
K
clk_sodimm0
L
M
clk_sodimm1
N
C99'!"&$'(,$,.!
99'''!*."''"'"
apex_clkout0!apex_clkout1&'"%"!&!"
992"!#&%%",!& '''"', Table 12. On-Board Module Clock Source Selection
Module Clock Input
Clock Source
clk_daughter_card
:+clk_daughter_card4"34
8+
0
"
""A
"3
(+..""A04,apex_clkout0
apex_clkout167+
,clk_daughter"" apex_clkout067+
* ,clk_daughter"" apex_clkout1.
clk_pmc
:+clk_pmc4"34
8+
0
"""A
"
3
(+..""A04,apex_clkout0,
apex_clkout16
7+
= ,clk_pmc"" +..067+
> ,clk_pmc"" apex_clkout067+
#
,clk_pmc"" apex_clkout16
clk_sodimm0
:+clk_sodimm04"34
8+
0
"""A
"3
(+..""A04,apex_clkout0
apex_clkout167+
,clk_sodimm0"" apex_clkout067+
. ,clk_sodimm1"" apex_clkout16
clk_sodimm1
Theclk_sodimm14"34
8+
0
"""A
"3
(+..""A04,apex_clkout0
apex_clkout167+
' ,clk_sodimm0"" apex_clkout067+
- ,clk_sodimm1"" apex_clkout16
f
"!%"''"'!& .'F!'G
!$/,
Altera Daughter Card Socket
&!"!'!0..!0!"
'""!B'""!"#!$"!"%"%!",0
!""!"#!""''$!'!",!0
!"'!""#'#:8'$!',!&' +"$3'"!
!$"!"'', Table 13. LCD Module Pinout
Pin
Front
Back
Pin
gnd
vcc F-!H
)
vee F-!H
rs
2
r/w
e
d0
d1
9
1
d2
d3
d4
d5
)
d6
d7
Table 14. Blank Module Pinout
Pin
Front
Back
Pin
vunreg (-!)
gnd
)
vref (-!)
gnd
2
+3.3v
gnd
+3.3v
gnd
9
1
osc
gnd
clk
gnd
)
clk (-!)
gnd
2
nc
gnd
nc
gnd
9
1
nc
gnd
Table 15. IDE Module Pinout (Part 1 of 2)
Pin
Front
Back
Pin
reset ide
gnd
)
hostdata7
hostdata8
2
hostdata6
hostdata9
hostdata5
hostdata10
9
1
hostdata4
hostdata11
Table 15. IDE Module Pinout (Part 2 of 2)
Pin
Front
Back
Pin
hostdata3
hostdata12
)
hostdata2
hostdata13
2
hostdata1
hostdata14
hostdata0
hostdata15
9
1
gnd
key
drq3
gnd
)
i/o write
gnd
2
i/o read
gnd
iochrdy
bale
9
1
dack3
gnd
)
)
irq14
iocs16
)
))
addr1
gnd
)
)2
addr0
addr2
)
)
chipsel0
chipsel1
)9
)1
activity
gnd
Supported
Components
!& /''!''"&#
&!"I".!'!"'
&!",
Table 16. Supported Components (Part 1 of 2)
Component
Manufacturer Part Number
Quantity
Schematic Reference
!!:&,*,:-%
"G!$:#%&
!,!,!),!,!2,!,!
!!:&,6*,)
"G!#/;!
12
!1,!,!,!,!),!,
!2,!,!,!9,!1,!,
!,!),!,!2,!,!,
!9,!1,!),!),!),!)),
!),!)2,!),!),!)9,!)1,
!,!,!,!),!,!2,
!,!,!1,!2,!2,!2,
!2),!2,!22,!2,!29,!21,
!,!,!),!,!,!,
!9,!1,!,!,!,!),
!,!2,!,!,!9,!1,
!9,!9,!9),!9,!92,!9,
!9,!91,!1,!1,!1,!1),
!1,!12,!1,!1,!19,!11,
!,!,!,!,!2,
!,!1,!,!,!,
!)
!!:&,6*,)
"G!#/;>)
2
!,!2,!2,!99,!
!!:&,6*,)
"G!#/;>
!,!9
'!?&!:!.
'G2
#-,#-,#-),#-
%;1'.
'G2
#
>%&2,$>&%
$':!G:$:2$%
#
>%&?7&
'.G2
#)
>%&
$':!G:.7=%
#,#9
>%&
$':!G:.7=%
#2
>%&
$':!G:.7=%
#
$%''$!:
'G)1
#
.%I%,:>'
%.=>:G222)
.%,.%
&$$:&!9,
"G;>/)
)
&,&,&2
&$$:&!9,
"G;>/
&,&,&9,&1,&,
&,&,&),&,&,
&9,&,&),&
&$$:&!9,
"G;>/
)
&1,&,&
!
Table 16. Supported Components (Part 2 of 2)
Component
&$$:&,,)
Manufacturer Part Number
"G&#)=<#)
Quantity
)
Schematic Reference
&,&,&),&,&,&,&2,
&,&,&,&,&1,&),
&),&),&)),&),&)2,&),
&),&)9,&)1,&,&2,&9,
&21,&,&9,&19,&1,
&,&
&$$:&,,)
"G&#)=<#&
&2,&1,&,&9,&9,&1),&
&$$:&,,J,)
"G&#)*
)
&,&,&
&$$:&,,)
"G&#)=<#
2
&1,&,&),&2,&
&$$:&,,)
"G&#)=<#
&,&,&),&,&,&1,
&2,&9,&9,&9),&9,&1,
&1,&,&,&),&1
&$$:&,,J,)
"G&#)*
)
&,&,&1
&$$:&,,)
"G&#)=<#
&,&,&92,&99,&1,&12,
&1,&,&,&,&
&$$:&,6,)
"G&#)=<#
&),&
$7?-?''-:&<
'&-G;)*)2
$7,$7
$7?%
!:$G9.$:
$
'!12;,:)
'"
G'!12;
,
/>!2,$
:+G:!/>!2*-
,)
!?.!!
G!.!
,2
*!
G*!
!<)2,$9
!50
G!<)2$!>
9
')2:!
G')2:!
1
')),$97%
'K(G'))!7
$!$!:
G99
,
'1./))!1
'%G'1./))!1
)
$!))'>L
0G$=9%!!;
F))6'>EH
L
$!2'>L
0G$=9%!!;
F26'>EH
L
"
%"%$"!'%""%"!5
References
■
■
■
■
■
!"#$%&!#$'&!###
()*
+,-,+.(,/
+0+1(2.(,/
8""%"'5
■
■
H,
!
!"!.8"$5
!"'
H".&"LL<!&"LLL,
"$#.,!8 090/01.09</01!!,
KWWSZZZPLFURQFRP
!%'!"'''"$0,
Schematics
®
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
http://www.altera.com
Applications Hotline5
(800) 800-EPLD
Customer Marketing:
(408) 544-7104
Literature Services:
lit_req@altera.com
#
"!...69>H.>#>!'".>#>!'"-.
0.!'">!'".K9D.
$!
".!'%'$!'!""!!"'!:"'"!"'%"!
""!
D !' ! " "', "! !$' "!!"' % " "$!2!' %" "
"'"'"'"'',"!"'!""""'
D,, ! %"$ !' ! $ !!'. !'" "$'. ! #"$', "! !""!'
"%"! % ' '" "' "" '%!' !"! "!B' '!!"
!""!#.&"'"'"$!!$'!#"'!'"'!!#,"!
!'''"''&#"!&#!"'$%!!"'%!#%"!."."'"
'"& " ) !' )"''# !$" "$ &# "! ""!, "!
'"'!"!'&!!'"'%'%!'&%""#$
!#&'%"!!&%"!$""'%""'"'"',
#"$"!
""!,"$'"'",
Printed on Recycled Paper.
1
2
3
4
SPARES
A
1. Cover Page
2. PCI Edge Fingers
3. Altera APEX (1 of 2)
4. Altera APEX (2 of 2)
5. SDRAM SODIMM Socket
6. Miscellaneous. Bypass
7. Terminations and LVDS Hdr
8. PMC Expansion
9. Configuration PLD
10. JTAG Circuit
11. Clock Distribution
12. Daughter Card
13. Power Supplies
14. Miscellaneous
PAGE INDEX
A
B
B
C
MECHANICAL
Revision B03
PMC
1
PMC1
APEX PCI Development Kit PCB
C
D
E
1
D
PCI_MH
1
PCB
1
BRACKET
1
FID5
Z3
BR3
PCI_MH
1
OSC50MHZ
BRACKET
1
FID3
Z2
PCI_MH
1
FID1
BR1
1
OSC33MHZ
Z1
1
BRACKET
BR2
Date:
Size
C
Title
E
Monday, October 09, 2000
Document Number
APEX PCI Development Kit Board
PCI_MH
1
FID6
PCI_MH
1
FID2
PCI_MH
1
FID4
DNI IS USED TO INDICATE PARTS THAT ARE NOT TO BE INSTALLED.
Sheet
1
of
14
Rev
B03
UNLESS OTHERWISE NOTED, ALL INDIVIDUAL RESISTORS AND CAPACITORS ARE SIZE 0603.
1
2
3
4
1
2
3
4
PCI_REQ#
10 PCI_M66EN
4 PCI_ACK64#
4 PCI_SERR#
4 PCI_LOCK#
4 PCI_PERR#
4 PCI_IRDY#
4 PCI_DEVSEL#
C106
0.01UF
A
Layout: Place M66EN and PCIXCAP capacitors
within 0.25" of the associated pin.
C103
0.01UF, DNI
PCIXCAP
4
4 PCI_INTA#
4 PCI_TRDY#
10 PCI_PCIXCAP
A
C
B
C
GND
C/BE7#
C/BE5#
+3.3V
PAR64
AD62
GND
AD60
AD58
GND
AD56
AD54
+3.3V
AD52
AD50
GND
AD48
AD46
GND
AD44
AD42
+3.3V
AD40
AD38
GND
AD36
AD34
GND
AD32
RESERVED
GND
RESERVED
RESERVED
RST#
+3.3V
GNT#
GND
RESERVED
AD30
+3.3V
AD28
AD26
GND
AD24
IDSEL
+3.3V
AD22
AD20
GND
AD18
AD16
+3.3V
FRAME#
GND
TRDY#
GND
STOP#
+3.3V
SDONE
SBO#
GND
PAR
AD15
+3.3V
AD13
AD11
GND
AD9
GND
GND
C/BE0#
+3.3V
AD6
AD4
GND
AD2
AD0
+3.3V
REQ64#
+5V
+5V
TRST#
+12V
TMS
TDI
+5V
INTA#
INTC#
+5V
RESERVED
+3.3V
RESERVED
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
A83
A84
A85
A86
A87
A88
A89
A90
A91
A92
A93
A94
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
R123
R122
PCI_AD32
PCI_AD36
PCI_AD34
PCI_AD40
PCI_AD38
PCI_AD44
PCI_AD42
PCI_AD48
PCI_AD46
PCI_AD52
PCI_AD50
PCI_AD56
PCI_AD54
PCI_AD60
PCI_AD58
PCI_AD62
PCI_C/BE#7
PCI_C/BE#5
PCI_AD2
PCI_AD0
PCI_AD6
PCI_AD4
PCI_C/BE#0
PCI_AD9
PCI_AD13
PCI_AD11
PCI_AD15
4.7K
4.7K
PCI_AD18
PCI_AD16
PCI_AD22
PCI_AD20
PCI_AD24
PCI_AD28
PCI_AD26
PCI_AD30
PCI_C/BE#[7..0]
PCI_3V_APEX_SPECIAL
RESERVED
GND
C/BE6#
C/BE4#
GND
AD63
AD61
+3.3V
AD59
AD57
GND
AD55
AD53
GND
AD51
AD49
+3.3V
AD47
AD45
GND
AD43
AD41
GND
AD39
AD37
+3.3V
AD35
AD33
GND
RESERVED
RESERVED
GND
RESERVED
GND
CLK
GND
REQ#
+3.3V
AD31
AD29
GND
AD27
AD25
+3.3V
C/BE3#
AD23
GND
AD21
AD19
+3.3V
AD17
C/BE2#
GND
IRDY#
+3.3V
DEVSEL#
PCIXCAP
LOCK#
PERR#
+3.3V
SERR#
+3.3V
C/BE1#
AD14
GND
AD12
AD10
M66EN
GND
GND
AD8
AD7
+3.3V
AD5
AD3
GND
AD1
+3.3V
ACK64#
+5V
+5V
-12V
TCK
GND
TDO
+5V
+5V
INTB#
INTD#
PRSNT1#
RESERVED
PRSNT2#
P1
PCI_AD[63..0]
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
B83
B84
B85
B86
B87
B88
B89
B90
B91
B92
B93
B94
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
+3.3V
+5.0V
+12V
PCI_C/BE#[7..0]
-12V
PCI_TDI_TDO
PCI_AD[63..0]
PCI_AD35
PCI_AD33
PCI_AD39
PCI_AD37
PCI_AD43
PCI_AD41
PCI_AD47
PCI_AD45
PCI_AD51
PCI_AD49
PCI_AD55
PCI_AD53
PCI_AD59
PCI_AD57
PCI_AD63
PCI_AD61
PCI_C/BE#6
PCI_C/BE#4
PCI_AD1
PCI_AD5
PCI_AD3
PCI_AD8
PCI_AD7
PCI_AD12
PCI_AD10
PCI_C/BE#1
PCI_AD14
PCIXCAP
PCI_AD17
PCI_C/BE#2
PCI_AD21
PCI_AD19
PCI_C/BE#3
PCI_AD23
PCI_AD27
PCI_AD25
PCI_AD31
PCI_AD29
PRSNT1# and PRSNT2# strapped to
indicate 25W power requirement.
+3.3V
+5.0V
+3.3V
PCIX, 64-bit, +3.3V only PCI Edge Fingers
B
D
D
CLK_PCI_EDGE 11
Date:
Size
C
Title
C97
0.1UF
C98
0.1UF
C99
0.1UF
C111
0.1UF
-12V
PCIX
0.1UF
C96
C110
0.1UF
C112
0.1UF
C109
0.1UF
E
Monday, October 09, 2000
Document Number
PCI Edge Fingers
+12V
+5.0V
+3.3V
+3.3V
2.40"
0.75"
1.75"
0.75"
CLK Length
32-bit interface signal length
64-bit interface signal length
RST# Length
BYPASS
Min
Parameter
PCI_C/BE#[7..0] 4
PCI_AD[63..0] 4
PCI_PAR64 4
PCI_REQ64# 4
PCI_PAR 4
PCI_STOP# 4
PCI_FRAME# 4
PCI_IDSEL 4
PCI_GNT# 4
PCI_RST# 4
E
2.40"
-
Min
Sheet
C113
0.1UF
C101
0.1UF
2.60"
1.50"
2.75"
3.00"
Max
2
C100
0.1UF
of
Std PCI
14
2.60"
1.50"
2.00"
-
Max
Rev
B03
Layout: PCIX Trace Length Requirements
1
2
3
4
1
2
3
4
CFG_FLASH_PGM0
CFG_FLASH_PGM1
CFG_FLASH_PGM2
CFG_FLASH_PGM3
9 APEX_CONF_DONE
9 APEX_NSTATUS
9 APEX_NCONFIG
9 APEX_DATA0
10 JTAG_APEX_TDI
9,10 JTAG_APEX_TDO
8,9,10 JTAG_TCK
8,9,10 JTAG_TMS
+1.8V
A
VIO
+1.8V
+3.3V
TP
CLK50_APEX
APEX_TRST
TP
TP
AE23
T7
11 CLK_APEX_CLKOUT0
11 CLK_APEX_CLKOUT1
AF22
V7
AF18
N11
AC26
P10
K9
M11
N3
P12
T10
AF6
R13
U11
V10
AF13
T15
V17
AF21
N24
R16
U18
A21
L17
N15
A13
A16
K16
M14
A6
J10
L12
A3
A24
B3
B8
B19
B24
C1
C2
C25
C26
D3
D24
K11
L10
L15
M13
M16
N2
N12
P15
P24
P25
R11
R14
T12
T17
U9
U16
AC3
AC24
AD1
AD2
AD25
AD26
AE3
AE8
AE19
AE24
AF3
AF24
N21
N20
N6
N7
AA13
P21
P6
G14
AA12
P7
G13
AA14
AA15
F14
AE20
U8
L21
U6
L18
W7
P16
P20
N8
M19
R6
APEX DCLK is driven by the free running 50 MHz clock,
CLK50_APEX. This is possible because the APEX looks for
a startup pattern on DATA0 before starting configuration
so may receive DCLKs prior to the configuration cycle.
R45
10K
+3.3V
R81
10K
B
POWER_AND_CFG
VCC_CLKOUT0
VCC_CLKOUT1
VCC_CLKLK0
VCC_CLKLK1
VCC_CLKLK2
VCC_CLKLK3
VCCIO8
VCCIO8
VCCIO8
VCCIO7
VCCIO7
VCCIO7
VCCIO6
VCCIO6
VCCIO6
VCCIO6
VCCIO5
VCCIO5
VCCIO5
VCCIO4
VCCIO4
VCCIO4
VCCIO3
VCCIO3
VCCIO3
VCCIO2
VCCIO2
VCCIO2
VCCIO2
VCCIO1
VCCIO1
VCCIO1
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
VCCINT
MSEL0
MSEL1
DATA0
DCLK
nSTATUS
nCONFIG
nCE
nCEO
CONF_DONE
TDI
TDO
TCK
TMS
TRST
CLKLK_FB1p
CLKLK_FB2p
LOCK1
LOCK2
LOCK3
LOCK4
CLKLK_ENA
LED0
LED1
LED2
LED3
LED4
LED5
LED6
LED7
GND_CLKOUT0
GND_CLKOUT1
GND_CLKLK0
GND_CLKLK1
GND_CLKLK2
GND_CLKLK2
GND_CLKLK3
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VREF0 (CS)
VREF1
VREF2
VREF3
VREF4
SW_RSVD0
SW_RSVD1
SERIAL_SYNC
SERIAL_STATUS
SERIAL_DATA
FLASH_SEL_PGM0
FLASH_SEL_PGM1
FLASH_SEL_PGM2
FLASH_SEL_PGM3
SW_GP0 (DEV_OE)
SW_GP1
CLKLK_OUT1p
CLKLK_OUT2p (PMC_CLKOUT)
CLK1p (SERIAL_CLK)
CLK2p (UNUSED)
CLK3p (OSC_CLK)
CLK4p (PCI_CLK)
U7A
B
AE22
V6
AE18
P11
AC25
N25
R10
A2
A8
A14
A19
A25
B1
B2
B6
B21
B25
B26
C3
C13
C24
D4
D23
H8
H19
J9
J18
K10
K17
L11
L13
L16
M12
M15
N1
N4
N13
N14
N26
P1
P2
P3
P13
P14
P23
P26
R12
R15
T11
T16
U10
U17
V9
V18
W8
W19
AC4
AC23
AD3
AD13
AD24
AE1
AE2
AE6
AE21
AE25
AE26
AF2
AF8
AF14
AF15
AF19
AF25
T6
M6
J3
W5
U3
F17
F18
J16
K15
L14
T5
T4
T3
U7
R8
R5
G17
H17
J17
G18
H18
K18
G19
J19
VREF
DEF_FLASH_PGM0
DEF_FLASH_PGM1
DEF_FLASH_PGM2
DEF_FLASH_PGM3
LED#0
LED#1
LED#2
LED#3
LED#4
LED#5
LED#6
LED#7
7,8 LVDS_TX+[15..0]
9
9
9
9
9
9
14
14
14
14
14
14
14
14
LCD_RS
LCD_RW
LCD_E
LCD_D[7..0]
FLASH_RESET#
FLASH_WE#
FLASH_CE#
FLASH_RDY_BSY#
FLASH_OE#
FLASH_D[7..0]
12
12
12
12
7,8 CLK_LVDS_TX+
7,8 CLK_LVDS_TX-
SW_GP0 14
SW_GP1 14
DEF_FLASH_PGM[3..0] 9,10
LED#[7..0] 14
APEX_SW_RSVD0 10
APEX_SW_RSVD1 10
C
C
RS232_RX
RS232_TX
RS232_RTS
RS232_CTS
RS232_DSR
RS232_DTR
RS232_CD
RS232_RI
APEX 1 of 2
CFG_STROBE 9
CFG_SEL_EPC41_0# 9
CFG_SEL_EPC4_FLASH# 9
POWER, CLOCKS, CONFIGURATION
11 CLK50_APEX
11 CLK_OSC_EXTRA
11 CLK_APEX_CLK0
11 CLK_APEX_CLK1
9 CFG_FLASH_PGM[3..0]
+3.3V
A
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
FLASH_D0
FLASH_D1
FLASH_D2
FLASH_D3
FLASH_D4
FLASH_D5
FLASH_D6
FLASH_D7
LCD_D7
LCD_D6
LCD_D5
LCD_D4
LCD_D3
LCD_D2
LCD_D1
LCD_D0
LVDS_TX+0
LVDS_TX+1
LVDS_TX+2
LVDS_TX+3
LVDS_TX+4
LVDS_TX+5
LVDS_TX+6
LVDS_TX+7
LVDS_TX+8
LVDS_TX+9
LVDS_TX+10
LVDS_TX+11
LVDS_TX+12
LVDS_TX+13
LVDS_TX+14
LVDS_TX+15
A4
A5
A7
A9
A10
A11
A12
A15
B7
B13
B14
B15
B16
C7
C8
C9
C10
C11
C12
C14
C15
C16
D6
D7
D8
D9
D10
D11
D12
D13
Y23
V13
U13
W12
V12
W11
V11
W10
W9
V8
W6
Y5
T9
T13
U4
V5
W3
V3
AF23
AF20
U5
W4
AD19
AD18
AD17
AC17
AE16
AC16
AC15
AC14
AC11
AC12
AC13
E2
E1
F1
G2
H1
J2
K1
L2
M1
R2
T1
U2
V1
W2
Y1
AA2
AB1
AC2
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
FLASH_A0
FLASH_A1
FLASH_A2
FLASH_A3
FLASH_A4
FLASH_A5
FLASH_A6
FLASH_A7
FLASH_A8
FLASH_A9
FLASH_A10
FLASH_A11
FLASH_A12
FLASH_A13
FLASH_A14
FLASH_A15
FLASH_A16
FLASH_A17
FLASH_A18
FLASH_A19
FLASH_A20
FLASH_A21
IDE_HOSTDATA15
IDE_HOSTDATA14
IDE_HOSTDATA13
IDE_HOSTDATA12
IDE_HOSTDATA11
IDE_HOSTDATA10
IDE_HOSTDATA9
IDE_HOSTDATA8
IDE_HOSTDATA7
IDE_HOSTDATA6
IDE_HOSTDATA5
IDE_HOSTDATA4
IDE_HOSTDATA3
IDE_HOSTDATA2
IDE_HOSTDATA1
IDE_HOSTDATA0
IDE_ADDR2
IDE_ADDR1
IDE_ADDR0
IDE_ACTIVITY
IDE_IRQ14
IDE_DRQ3
IDE_DACK3
IDE_IOR#
IDE_IOW#
IDE_IOCS16#
IDE_IOCHRDY
IDE_BALE
IDE_CHIPSEL1#
IDE_CHIPSEL0#
IDE_RESET_IDE
LVDS_TX_IN_CLK+
LVDS_TX_IN_CLK-
LVDS_TX-0
LVDS_TX-1
LVDS_TX-2
LVDS_TX-3
LVDS_TX-4
LVDS_TX-5
LVDS_TX-6
LVDS_TX-7
LVDS_TX-8
LVDS_TX-9
LVDS_TX-10
LVDS_TX-11
LVDS_TX-12
LVDS_TX-13
LVDS_TX-14
LVDS_TX-15
LVDSTX_DAUGHTER_RS232_FLASH
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
FLASH_D0
FLASH_D1
FLASH_D2
FLASH_D3
FLASH_D4
FLASH_D5
FLASH_D6
FLASH_D7
FLASH_RESET
FLASH_WE#
FLASH_CE#
FLASH_RDY_BSY#
FLASH_OE#
RS232_RX
RS232_TX
RS232_RTS
RS232_CTS
RS232_DSR
RS232_DTR
RS232_CD
RS232_RI
LCD_D7
LCD_D6
LCD_D5
LCD_D4
LCD_D3
LCD_D2
LCD_D1
LCD_D0
LCD_RS
LCD_RW
LCD_E
LVDS_TX_CLK+
LVDS_TX_CLK-
LVDS_TX+0
LVDS_TX+1
LVDS_TX+2
LVDS_TX+3
LVDS_TX+4
LVDS_TX+5
LVDS_TX+6
LVDS_TX+7
LVDS_TX+8
LVDS_TX+9
LVDS_TX+10
LVDS_TX+11
LVDS_TX+12
LVDS_TX+13
LVDS_TX+14
LVDS_TX+15
U7D
Y24
AA23
AA24
AB23
AB24
AC18
AC19
AC20
AC21
AC22
AD11
AD12
AD14
AD15
AD16
AD20
AD21
AD22
AD23
AE12
AE13
AE14
AE15
AE17
AF12
AF16
AF17
W14
W13
AB12
Y12
AB11
AA11
Y11
AB10
AA10
Y10
AB9
AA9
Y9
AB8
AA8
Y8
AB7
AA7
Y7
AB6
AA6
Y6
AF5
AE5
AD7
AD5
AC7
AC5
AB3
AA3
Y4
AA4
AB4
AC6
AD4
AD6
AE4
AF4
AF9
AE10
AE11
AD10
AD9
AE7
AD8
AC8
AF7
AE9
AC9
AC10
AF11
AF10
Y3
D1
D2
F2
G1
H2
J1
K2
L1
M2
R1
T2
U1
V2
W1
Y2
AA1
AB2
AC1
D
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
TP
FLASH_A0
FLASH_A1
FLASH_A2
FLASH_A3
FLASH_A4
FLASH_A5
FLASH_A6
FLASH_A7
FLASH_A8
FLASH_A9
FLASH_A10
FLASH_A11
FLASH_A12
FLASH_A13
FLASH_A14
FLASH_A15
FLASH_A16
FLASH_A17
FLASH_A18
FLASH_A19
FLASH_A20
FLASH_A21
IDE_HOSTDATA15
IDE_HOSTDATA14
IDE_HOSTDATA13
IDE_HOSTDATA12
IDE_HOSTDATA11
IDE_HOSTDATA10
IDE_HOSTDATA9
IDE_HOSTDATA8
IDE_HOSTDATA7
IDE_HOSTDATA6
IDE_HOSTDATA5
IDE_HOSTDATA4
IDE_HOSTDATA3
IDE_HOSTDATA2
IDE_HOSTDATA1
IDE_HOSTDATA0
TP
TP
LVDS_TX-0
LVDS_TX-1
LVDS_TX-2
LVDS_TX-3
LVDS_TX-4
LVDS_TX-5
LVDS_TX-6
LVDS_TX-7
LVDS_TX-8
LVDS_TX-9
LVDS_TX-10
LVDS_TX-11
LVDS_TX-12
LVDS_TX-13
LVDS_TX-14
LVDS_TX-15
LVDS TX, LED, RS232, FLASH,
DAUGHTER CARD, NO CONNECTS
D
Date:
Size
C
Title
FLASH_A[21..0] 9
E
Monday, October 09, 2000
Document Number
APEX - 1 of 2
IDE_ADDR2 12
IDE_ADDR1 12
IDE_ADDR0 12
IDE_HOSTDATA[15..0] 12
IDE_ACTIVITY 12
IDE_IRQ14 12
IDE_DRQ3 12
IDE_DACK3 12
IDE_IOR# 12
IDE_IOW# 12
IDE_IOCS16# 12
IDE_IOCHRDY 12
IDE_BALE 12
IDE_CHIPSEL1# 12
IDE_CHIPSEL0# 12
IDE_RESET_IDE 12
LVDS_TX-[15..0] 7,8
E
Sheet
3
of
14
Rev
B03
1
2
3
4
1
2
3
4
8
7,8
8
7,8
7,8
7,8
7,8
7,8
8
7,8
7,8
7,8
7,8
7,8
7,8
7,8
7,8
PMC_AD0
PMC_AD1
PMC_AD2
PMC_AD3
PMC_AD4
PMC_AD5
PMC_AD6
PMC_AD7
PMC_AD8
PMC_AD9
PMC_AD10
PMC_AD11
PMC_AD12
PMC_AD13
PMC_AD14
PMC_AD15
PMC_AD16
PMC_AD17
PMC_AD18
PMC_AD19
PMC_AD20
PMC_AD21
PMC_AD22
PMC_AD23
PMC_AD24
PMC_AD25
PMC_AD26
PMC_AD27
PMC_AD28
PMC_AD29
PMC_AD30
PMC_AD31
PMC_C/BE#0
PMC_C/BE#1
PMC_C/BE#2
PMC_C/BE#3
PCI_IDSEL
PCI_DEVSEL#
PCI_PAR
PCI_FRAME#
PCI_IRDY#
PCI_TRDY#
PCI_LOCK#
PCI_STOP#
PCI_RST#
PCI_REQ#
PCI_GNT#
PCI_INTA#
PCI_PERR#
PCI_SERR#
PMC_IDSEL
PMC_DEVSEL#
PMC_PAR
PMC_FRAME#
PMC_IRDY#
PMC_TRDY#
PMC_LOCK#
PMC_STOP#
PMC_RST#
PMC_REQ#
PMC_GNT#
PMC_INTA#
PMC_INTB#
PMC_INTC#
PMC_INTD#
PMC_PERR#
PMC_SERR#
2
2
2
2
2
2
2
2
2
2
2
2
2
2
A
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_C/BE#0
PCI_C/BE#1
PCI_C/BE#2
PCI_C/BE#3
A
A20
A22
A23
D20
C21
D21
E20
B22
F13
A18
A17
D16
E17
E18
E19
C22
D22
L19
K24
K23
K22
K21
K20
K19
J24
J23
J22
J21
J20
H24
H22
H21
H20
G24
G22
G21
G20
F22
F21
E22
E23
D19
C19
D18
C18
B18
D17
C17
B17
C23
B23
C20
B20
PMC_IDSEL
PMC_DEVSEL#
PMC_PAR
PMC_FRAME#
PMC_IRDY#
PMC_TRDY#
PMC_LOCK#
PMC_STOP#
PMC_RST#
PMC_REQ#
PMC_GNT#
PMC_INTA#
PMC_INTB#
PMC_INTC#
PMC_INTD#
PMC_PERR#
PMC_SERR#
PMC_PCI
PCI_PAR64
L24
L23
L22
M24
M23
M22
M21
M18
M17
N23
N22
N19
N18
N17
N16
P22
P18
P17
R24
R23
R22
R21
R20
R19
R18
R17
T24
T23
T22
T21
T20
T19
W20
Y20
Y19
AA20
PCI_AD32
PCI_AD33
PCI_AD34
PCI_AD35
PCI_AD36
PCI_AD37
PCI_AD38
PCI_AD39
PCI_AD40
PCI_AD41
PCI_AD42
PCI_AD43
PCI_AD44
PCI_AD45
PCI_AD46
PCI_AD47
PCI_AD48
PCI_AD49
PCI_AD50
PCI_AD51
PCI_AD52
PCI_AD53
PCI_AD54
PCI_AD55
PCI_AD56
PCI_AD57
PCI_AD58
PCI_AD59
PCI_AD60
PCI_AD61
PCI_AD62
PCI_AD63
PCI_C/BE#4
PCI_C/BE#5
PCI_C/BE#6
PCI_C/BE#7
PMC_AD32
PMC_AD33
PMC_AD34
PMC_AD35
PMC_AD36
PMC_AD37
PMC_AD38
PMC_AD39
PMC_AD40
PMC_AD41
PMC_AD42
PMC_AD43
PMC_AD44
PMC_AD45
PMC_AD46
PMC_AD47
PMC_AD48
PMC_AD49
PMC_AD50
PMC_AD51
PMC_AD52
PMC_AD53
PMC_AD54
PMC_AD55
PMC_AD56
PMC_AD57
PMC_AD58
PMC_AD59
PMC_AD60
PMC_AD61
PMC_AD62
PMC_AD63
PMC_C/BE#4
PMC_C/BE#5
PMC_C/BE#6
PMC_C/BE#7
PMC_BM1
PMC_BM2
PMC_BM3
PMC_BM4
PMC_REQ64#
PMC_ACK64#
PMC_SBO
PMC_SDONE
NC
LVDS_RX_CLK+
LVDS_RX_CLKLVDS_DESKEW
PMC_PAR64 / LVDS_RX15+
B
PMC_BM1
PMC_BM2
PMC_BM3
PMC_BM4
M20
V4
AA5
AB5
8
8
8
8
PMC_REQ64# 7,8
PMC_ACK64# 7,8
PMC_SBO# 8
PMC_SDONE 8
D15
D14
E21
H23
G23
CLK_LVDS_RX+ 7,8
CLK_LVDS_RX- 7,8
LVDS_DESKEW 7,8
AB25
AB26
U12
TP
PMC_PAR64 7,8
D26
PMC_C/BE#[7..0] 7,8
PMC_AD32
PMC_AD33 / LVDS_RX0PMC_AD34 / LVDS_RX1PMC_AD35 / LVDS_RX0+
PMC_AD36 / LVDS_RX1+
PMC_AD37 / LVDS_RX2PMC_AD38 / LVDS_RX3PMC_AD39 / LVDS_RX2+
PMC_AD40 / LVDS_RX3+
PMC_AD41 / LVDS_RX4PMC_AD42 / LVDS_RX5PMC_AD43 / LVDS_RX4+
PMC_AD44 / LVDS_RX5+
PMC_AD45 / LVDS_RX6PMC_AD46 / LVDS_RX7PMC_AD47 / LVDS_RX6+
PMC_AD48 / LVDS_RX7+
PMC_AD49 / LVDS_RX8PMC_AD50 / LVDS_RX9PMC_AD51 / LVDS_RX8+
PMC_AD52 / LVDS_RX9+
PMC_AD53 / LVDS_RX10PMC_AD54 / LVDS_RX11PMC_AD55 / LVDS_RX10+
PMC_AD56 / LVDS_RX11+
PMC_AD57 / LVDS_RX12PMC_AD58 / LVDS_RX13PMC_AD59 / LVDS_RX12+
PMC_AD60 / LVDS_RX13+
PMC_AD61 / LVDS_RX14PMC_AD62 / LVDS_RX15PMC_AD63 / LVDS_RX14+
PMC_CBEN4
PMC_CBEN5
PMC_CBEN6
PMC_CBEN7
PMC_AD[63..0] 7,8
PMC_C/BE#[7..0]
E24
AA26
Y25
AA25
Y26
W26
V25
W25
V26
U26
T25
U25
T26
R26
M25
R25
M26
L26
K25
L25
K26
J26
H25
J25
H26
G26
F25
G25
F26
E26
D25
E25
F20
F19
F24
F23
TP
PCI_REQ64# 2
PCI_ACK64# 2
AB20
AB19
L20
PCI_PAR64 2
AA19
PMC_AD[63..0]
NC
PCI_REQ64#
PCI_ACK64#
PMC PCI
PRIMARY_PCI
PCI_IDSEL
PCI_DEVSEL#
PCI_PAR
PCI_FRAME#
PCI_IRDY# (FAST3)
PCI_TRDY# (FAST2)
PCI_LOCK#
PCI_STOP#
PCI_RST#(DEDIN)
PCI_REQ#
PCI_GNT#
PCI_INTA#
PCI_PERR#
PCI_SERR#
PCI_AD32
PCI_AD33
PCI_AD34
PCI_AD35
PCI_AD36
PCI_AD37
PCI_AD38
PCI_AD39
PCI_AD40
PCI_AD41
PCI_AD42
PCI_AD43
PCI_AD44
PCI_AD45
PCI_AD46
PCI_AD47
PCI_AD48
PCI_AD49
PCI_AD50
PCI_AD51
PCI_AD52
PCI_AD53
PCI_AD54
PCI_AD55
PCI_AD56
PCI_AD57
PCI_AD58
PCI_AD59
PCI_AD60
PCI_AD61
PCI_AD62
PCI_AD63
PCI_CBEN4
PCI_CBEN5
PCI_CBEN6
PCI_CBEN7
PCI_C/BE#[7..0] 2
PCI_C/BE#[7..0]
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
PCI_AD27
PCI_AD28
PCI_AD29
PCI_AD30
PCI_AD31
PCI_CBEN0
PCI_CBEN1
PCI_CBEN2
PCI_CBEN3
PMC_AD0
PMC_AD1
PMC_AD2
PMC_AD3
PMC_AD4
PMC_AD5
PMC_AD6
PMC_AD7
PMC_AD8
PMC_AD9
PMC_AD10
PMC_AD11
PMC_AD12
PMC_AD13
PMC_AD14
PMC_AD15
PMC_AD16
PMC_AD17
PMC_AD18
PMC_AD19
PMC_AD20
PMC_AD21
PMC_AD22
PMC_AD23
PMC_AD24
PMC_AD25
PMC_AD26
PMC_AD27
PMC_AD28
PMC_AD29
PMC_AD30
PMC_AD31
PMC_CBEN0
PMC_CBEN1
PMC_CBEN2
PMC_CBEN3
U7E
AB17
Y16
AA18
AA16
Y13
Y14
P19
W16
H14
AB14
AB13
T18
Y18
W18
U24
U23
U22
U21
U20
U19
V24
V23
V22
V21
V20
V19
W24
W23
W22
Y22
AA22
AB22
W21
Y21
AA21
AB21
AB18
W17
U15
V15
W15
Y15
AB15
T14
U14
V14
Y17
AA17
V16
AB16
U7B
PCI_AD[63..0] 2
PCI_AD[63..0]
PRIMARY PCI
B
5
5
5
5
C
SDRAM_BA0
SDRAM_BA1
SDRAM_S0#
SDRAM_S1#
APEX 2 of 2
C
SDRAM_A0
SDRAM_A1
SDRAM_A2
SDRAM_A3
SDRAM_A4
SDRAM_A5
SDRAM_A6
SDRAM_A7
SDRAM_A8
SDRAM_A9
SDRAM_A10
SDRAM_A11
SDRAM_A12
SDRAM_A13
SDRAM_DQ0
SDRAM_DQ1
SDRAM_DQ2
SDRAM_DQ3
SDRAM_DQ4
SDRAM_DQ5
SDRAM_DQ6
SDRAM_DQ7
SDRAM_DQ8
SDRAM_DQ9
SDRAM_DQ10
SDRAM_DQ11
SDRAM_DQ12
SDRAM_DQ13
SDRAM_DQ14
SDRAM_DQ15
SDRAM_DQ16
SDRAM_DQ17
SDRAM_DQ18
SDRAM_DQ19
SDRAM_DQ20
SDRAM_DQ21
SDRAM_DQ22
SDRAM_DQ23
SDRAM_DQ24
SDRAM_DQ25
SDRAM_DQ26
SDRAM_DQ27
SDRAM_DQ28
SDRAM_DQ29
SDRAM_DQ30
SDRAM_DQ31
SDRAM_DQMB0
SDRAM_DQMB1
SDRAM_DQMB2
SDRAM_DQMB3
E7
E8
F9
F8
G9
E9
H11
G11
F11
K12
H12
G12
H10
G10
E11
J12
E6
F7
T8
R9
R7
R4
R3
P4
P5
P8
P9
N5
N9
N10
M3
M4
M5
M7
M8
M9
M10
L3
L4
L5
L6
L7
L8
L9
K3
K4
K5
K6
K7
K8
H6
G3
F12
K13
SDRAM_SODIMM
SDRAM_A0
SDRAM_A1
SDRAM_A2
SDRAM_A3
SDRAM_A4
SDRAM_A5
SDRAM_A6
SDRAM_A7 (RDYnBSY)
SDRAM_A8 (CLKUSR)
SDRAM_A9
SDRAM_A10
SDRAM_A11
SDRAM_A12
SDRAM_A13
SDRAM_BA0
SDRAM_BA1
SDRAM_S0# (DATA1)
SDRAM_S1#
SDRAM_DQ0 (CLKFBIN1A)
SDRAM_DQ1
SDRAM_DQ2 (DEV_CLRn)
SDRAM_DQ3
SDRAM_DQ4 (nWS)
SDRAM_DQ5
SDRAM_DQ6
SDRAM_DQ7
SDRAM_DQ8
SDRAM_DQ9 (DATA7)
SDRAM_DQ10
SDRAM_DQ11
SDRAM_DQ12 (DATA6)
SDRAM_DQ13
SDRAM_DQ14
SDRAM_DQ15
SDRAM_DQ16
SDRAM_DQ17
SDRAM_DQ18
SDRAM_DQ19
SDRAM_DQ20
SDRAM_DQ21
SDRAM_DQ22
SDRAM_DQ23
SDRAM_DQ24
SDRAM_DQ25
SDRAM_DQ26
SDRAM_DQ27
SDRAM_DQ28
SDRAM_DQ29
SDRAM_DQ30 (DATA4)
SDRAM_DQ31
SDRAM_DQMB0 (DATA5)
SDRAM_DQMB1
SDRAM_DQMB2
SDRAM_DQMB3
U7C
D
SDRAM_RSVD0
SDRAM_RSVD1
SDRAM_RSVD2
SDRAM_RSVD3
SDRAM_RSVD4
SDRAM_RSVD5
SDRAM_RSVD6
SDRAM_RSVD7
SDRAM_SCL
SDRAM_SDA
SDRAM_CKE0 (DATA2)
SDRAM_CKE1
SDRAM_RAS#
SDRAM_CAS#
SDRAM_WE#
SDRAM_DQ32
SDRAM_DQ33
SDRAM_DQ34
SDRAM_DQ35
SDRAM_DQ36
SDRAM_DQ37
SDRAM_DQ38
SDRAM_DQ39
SDRAM_DQ40 (nCS)
SDRAM_DQ41
SDRAM_DQ42
SDRAM_DQ43
SDRAM_DQ44
SDRAM_DQ45
SDRAM_DQ46
SDRAM_DQ47
SDRAM_DQ48
SDRAM_DQ49
SDRAM_DQ50
SDRAM_DQ51
SDRAM_DQ52
SDRAM_DQ53
SDRAM_DQ54
SDRAM_DQ55
SDRAM_DQ56
SDRAM_DQ57
SDRAM_DQ58
SDRAM_DQ59
SDRAM_DQ60
SDRAM_DQ61
SDRAM_DQ62
SDRAM_DQ63 (DATA3)
SDRAM_DQMB4
SDRAM_DQMB5
SDRAM_DQMB6
SDRAM_DQMB7
SDRAM_DQMB[7..0]
SDRAM_DQ[63..0]
SDRAM_A[13..0]
SDRAM SODIMM
D
Title
Date:
Size
C
E
Monday, October 09, 2000
Document Number
APEX - 2 of 2
SDRAM_RSVD[7..0] 5
SDRAM_SCL 5
SDRAM_SDA 5
B4
B5
C5
C6
B9
B10
B11
B12
H13
K14
SDRAM_RAS# 5
SDRAM_CAS# 5
SDRAM_WE# 5
SDRAM_CKE0 5
SDRAM_CKE1 5
SDRAM_RSVD0
SDRAM_RSVD1
SDRAM_RSVD2
SDRAM_RSVD3
SDRAM_RSVD4
SDRAM_RSVD5
SDRAM_RSVD6
SDRAM_RSVD7
SDRAM_DQ32
SDRAM_DQ33
SDRAM_DQ34
SDRAM_DQ35
SDRAM_DQ36
SDRAM_DQ37
SDRAM_DQ38
SDRAM_DQ39
SDRAM_DQ40
SDRAM_DQ41
SDRAM_DQ42
SDRAM_DQ43
SDRAM_DQ44
SDRAM_DQ45
SDRAM_DQ46
SDRAM_DQ47
SDRAM_DQ48
SDRAM_DQ49
SDRAM_DQ50
SDRAM_DQ51
SDRAM_DQ52
SDRAM_DQ53
SDRAM_DQ54
SDRAM_DQ55
SDRAM_DQ56
SDRAM_DQ57
SDRAM_DQ58
SDRAM_DQ59
SDRAM_DQ60
SDRAM_DQ61
SDRAM_DQ62
SDRAM_DQ63
SDRAM_DQMB4
SDRAM_DQMB5
SDRAM_DQMB6
SDRAM_DQMB7
C4
F6
F5
E5
D5
J4
J5
J6
J7
J8
H3
H4
H5
G5
G6
G7
G8
F3
E3
F4
E4
H9
F10
E10
J11
E13
J14
E14
E15
F15
G15
H15
J15
E16
F16
G16
H16
H7
G4
E12
J13
Sheet
SDRAM_DQMB[7..0] 5
SDRAM_DQ[63..0] 5
SDRAM_A[13..0] 5
E
4
of
14
Rev
B03
1
2
3
4
1
2
3
4
4 SDRAM_RAS#
4 SDRAM_SDA
4 SDRAM_WE#
4 SDRAM_S0#
4 SDRAM_S1#
11 CLK_SODIMM0
A
RPACK8, 22
S_DQMB0
16
S_DQMB1
15
S_A0
14
S_A1
13
S_A2
12
S_DQ8
11
S_DQ9
10
S_DQ10
9
RPACK8, 22
S_DQ11
16
S_DQ12
15
S_DQ13
14
S_DQ14
13
S_DQ15
12
S_RSVD0
11
S_RSVD1
10
S_RAS#
9
RP23
1
2
3
4
5
6
7
8
RP18
1
2
3
4
5
6
7
8
SDRAM_DQMB0
SDRAM_DQMB1
SDRAM_A0
SDRAM_A1
SDRAM_A2
SDRAM_DQ8
SDRAM_DQ9
SDRAM_DQ10
RPACK8, 22
S_A10
16
S_DQMB2
15
S_DQMB3
14
S_DQ24
13
S_DQ25
12
S_DQ26
11
S_DQ27
10
S_DQ28
9
RPACK8, 22
S_DQ29
16
S_DQ30
15
S_DQ31
14
S_SDA
13
12
11
10
9
RP12
1
2
3
4
5
6
7
8
RP14
1
2
3
4
5
6
7
8
SDRAM_DQ19
SDRAM_DQ20
SDRAM_DQ21
SDRAM_DQ22
SDRAM_DQ23
SDRAM_A6
SDRAM_A8
SDRAM_A9
SDRAM_A10
SDRAM_DQMB2
SDRAM_DQMB3
SDRAM_DQ24
SDRAM_DQ25
SDRAM_DQ26
SDRAM_DQ27
SDRAM_DQ28
B
RPACK8, 22
S_DQ19
16
S_DQ20
15
S_DQ21
14
S_DQ22
13
S_DQ23
12
S_A6
11
S_A8
10
S_A9
9
RP10
1
2
3
4
5
6
7
8
SDRAM_RSVD2
SDRAM_RSVD3
SDRAM_DQ16
SDRAM_DQ17
SDRAM_DQ18
SDRAM_DQ29
SDRAM_DQ30
SDRAM_DQ31
RPACK8, 22
S_WE#
16
S_S0#
15
S_S1#
14
S_RSVD2
13
S_RSVD3
12
S_DQ16
11
S_DQ17
10
S_DQ18
9
RP8
1
2
3
4
5
6
7
8
SDRAM_DQ11
SDRAM_DQ12
SDRAM_DQ13
SDRAM_DQ14
SDRAM_DQ15
SDRAM_RSVD0
SDRAM_RSVD1
RPACK8, 22
S_DQ0
16
S_DQ1
15
S_DQ2
14
S_DQ3
13
S_DQ4
12
S_DQ5
11
S_DQ6
10
S_DQ7
9
RP24
1
2
3
4
5
6
7
8
SDRAM_DQ0
SDRAM_DQ1
SDRAM_DQ2
SDRAM_DQ3
SDRAM_DQ4
SDRAM_DQ5
SDRAM_DQ6
SDRAM_DQ7
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
SO-DIMM144
Vss
DQ0
DQ1
DQ2
DQ3
Vdd
DQ4
DQ5
DQ6
DQ7
Vss
DQMB0
DQMB1
Vdd
A0
A1
A2
Vss
DQ8
DQ9
DQ10
DQ11
Vdd
DQ12
DQ13
DQ14
DQ15
Vss
NC
NC
CK0
Vdd
RAS#
WE#
S0#
S1#
DNU
Vss
NC
NC
Vdd
DQ16
DQ17
DQ18
DQ19
Vss
DQ20
DQ21
DQ22
DQ23
Vdd
A6
A8
Vss
A9
A10
Vdd
DQMB2
DQMB3
Vss
DQ24
DQ25
DQ26
DQ27
Vdd
DQ28
DQ29
DQ30
DQ31
Vss
SDA
Vdd
J6
C
Vss
DQ32
DQ33
DQ34
DQ35
Vdd
DQ36
DQ37
DQ38
DQ39
Vss
DQMB4
DQMB5
Vdd
A3
A4
A5
Vss
DQ40
DQ41
DQ42
DQ43
Vdd
DQ44
DQ45
DQ46
DQ47
Vss
NC
NC
CKE0
Vdd
CAS#
CKE1
A12
A13
CK1
Vss
NC
NC
Vdd
DQ48
DQ49
DQ50
DQ51
Vss
DQ52
DQ53
DQ54
DQ55
Vdd
A7
BA0
Vss
BA1
NC
Vdd
DQMB6
DQMB7
Vss
DQ56
DQ57
DQ58
DQ59
Vdd
DQ60
DQ61
DQ62
DQ63
Vss
SCL
Vdd
SDRAM_RSVD[7..0]
VIO
SDRAM_DQMB[7..0]
SDRAM_A[13:0]
SDRAM_DQ[63..0]
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
SDRAM SODIMM
C
4 SDRAM_RSVD[7..0]
B
4 SDRAM_DQMB[7..0]
4 SDRAM_A[13..0]
4 SDRAM_DQ[63..0]
A
VIO
S_DQ60
S_DQ61
S_DQ62
S_DQ63
S_SCL
S_BA1
S_A11
S_DQMB6
S_DQMB7
S_DQ56
S_DQ57
S_DQ58
S_DQ59
S_DQ50
S_DQ51
S_DQ52
S_DQ53
S_DQ54
S_DQ55
S_A7
S_BA0
S_CAS#
S_CKE1
S_A12
S_A13
S_RSVD6
S_RSVD7
S_DQ48
S_DQ49
CLK_SODIMM1
S_DQ43
S_DQ44
S_DQ45
S_DQ46
S_DQ47
S_RSVD4
S_RSVD5
S_CKE0
S_DQMB4
S_DQMB5
S_A3
S_A4
S_A5
S_DQ40
S_DQ41
S_DQ42
S_DQ32
S_DQ33
S_DQ34
S_DQ35
S_DQ36
S_DQ37
S_DQ38
S_DQ39
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
RPACK8, 22
1
2
3
4
5
6
7
8
RP9
RP13 RPACK8, 22
1
2
3
4
5
6
7
8
RP11 RPACK8, 22
1
2
3
4
5
6
7
8
RPACK8, 22
1
2
3
4
5
6
7
8
RPACK8, 22
1
2
3
4
5
6
7
8
RP7
RP6
RP17 RPACK8, 22
1
2
3
4
5
6
7
8
RP20 RPACK8, 22
1
2
3
4
5
6
7
8
D
SDRAM_DQ60
SDRAM_DQ61
SDRAM_DQ62
SDRAM_DQ63
SDRAM_A11
SDRAM_DQMB6
SDRAM_DQMB7
SDRAM_DQ56
SDRAM_DQ57
SDRAM_DQ58
SDRAM_DQ59
SDRAM_DQ50
SDRAM_DQ51
SDRAM_DQ52
SDRAM_DQ53
SDRAM_DQ54
SDRAM_DQ55
SDRAM_A7
SDRAM_A12
SDRAM_A13
SDRAM_RSVD6
SDRAM_RSVD7
SDRAM_DQ48
SDRAM_DQ49
SDRAM_DQ43
SDRAM_DQ44
SDRAM_DQ45
SDRAM_DQ46
SDRAM_DQ47
SDRAM_RSVD4
SDRAM_RSVD5
SDRAM_DQMB4
SDRAM_DQMB5
SDRAM_A3
SDRAM_A4
SDRAM_A5
SDRAM_DQ40
SDRAM_DQ41
SDRAM_DQ42
SDRAM_DQ32
SDRAM_DQ33
SDRAM_DQ34
SDRAM_DQ35
SDRAM_DQ36
SDRAM_DQ37
SDRAM_DQ38
SDRAM_DQ39
D
Date:
Size
C
Title
E
Monday, October 09, 2000
Document Number
SDRAM SODIMM
E
Sheet
SDRAM_SCL 4
SDRAM_BA1 4
SDRAM_BA0 4
5
CLK_SODIMM1 11
SDRAM_CAS# 4
SDRAM_CKE1 4
SDRAM_CKE0 4
of
14
Rev
B03
1
2
3
4
A
C34
0.1UF
C83
0.1UF
C102
0.1UF
C41
0.1UF
C51
0.1UF
C52
0.1UF
C107
0.1UF
C38
0.1UF
C104
0.1UF
C43
0.1UF
C54
0.1UF
C79
0.1UF
C55
0.1UF
C33
0.1UF
C42
0.1UF
C88
0.01UF
C35
0.1UF
C57
0.01UF
APEX PLL POWER BYPASS
C63
0.1UF
C105
0.1UF
SODIMM BYPASS
+1.8V
C73
0.1UF
C77
0.1UF
B
C31
0.1UF
C108
0.001UF
C91
0.1UF
C90
0.1UF
C32
0.1UF
C60
0.001UF
C75
0.1UF
C53
0.1UF
+3.3V
C89
0.1UF
C12
0.1UF
C61
0.1UF
C70
0.1UF
C93
0.1UF
CFGPLD BYPASS
C13
0.1UF
C
C94
0.1UF
C29
0.1UF
C64
0.1UF
C27
0.1UF
EPC4 BYPASS
C45
0.1UF
C46
0.1UF
+3.3V
C85
0.1UF
C86
0.1UF
FLASH BYPASS
D
+3.3V
C15
0.1UF
CFG HDR BYPASS
Title
+3.3V
Miscellaneous Bypass
C44
0.1UF
DAUGHTER CARD BYPASS
E
Sheet
6
of
14
Rev
B03
3
4
Date:
Size
C
E
Monday, October 09, 2000
Document Number
1
C39
0.1UF
C66
0.1UF
C49
0.1UF
C95
0.1UF
+1.8V
D
1
C40
0.1UF
C50
0.1UF
C92
0.1UF
C69
0.1UF
+3.3V
74VCH125 BYPASS
MISCELLANEOUS BYPASS
C
2
VIO
VIO
+1.8V
C58
0.1UF
APEX BYPASS
B
2
3
4
+3.3V
A
1
2
3
4,8 CLK_LVDS_RX+
4,8 CLK_LVDS_RX-
4,8 PMC_AD[63..0]
4,8 PMC_PAR64
4,8 PMC_C/BE#[7..0]
A
PMC_AD62
PMC_AD63
PMC_AD61
PMC_AD60
PMC_AD58
PMC_AD59
PMC_AD57
PMC_AD56
PMC_AD54
PMC_AD55
PMC_AD53
PMC_AD52
PMC_AD50
PMC_AD51
PMC_AD49
PMC_AD48
PMC_AD46
PMC_AD47
PMC_AD45
PMC_AD44
PMC_AD42
PMC_AD43
PMC_AD41
PMC_AD40
PMC_AD38
PMC_AD39
PMC_AD37
PMC_AD36
PMC_AD34
PMC_AD35
PMC_AD33
LVDS_RX-15
LVDS_RX+14
LVDS_RX-14
LVDS_RX+13
LVDS_RX-13
LVDS_RX+12
LVDS_RX-12
LVDS_RX+11
LVDS_RX-11
LVDS_RX+10
LVDS_RX-10
LVDS_RX+9
LVDS_RX-9
LVDS_RX+8
LVDS_RX-8
LVDS_RX+7
LVDS_RX-7
LVDS_RX+6
LVDS_RX-6
LVDS_RX+5
LVDS_RX-5
LVDS_RX+4
LVDS_RX-4
LVDS_RX+3
LVDS_RX-3
LVDS_RX+2
LVDS_RX-2
LVDS_RX+1
LVDS_RX-1
LVDS_RX+0
LVDS_RX-0
R71
R70
LVDS_TX-1
LVDS_TX-0
B
R58
R57
LVDS_TX-3
LVDS_TX-2
R68
3,8 LVDS_TX-[15..0]
CLK_LVDS_RX+
CLK_LVDS_RX+
R47
R51
R75
PMC_AD39
PMC_AD40
LVDS_RX+2
LVDS_RX+3
R55
R64
3,8 CLK_LVDS_TX-
PMC_AD35
PMC_AD36
LVDS_RX+0
LVDS_RX+1
CLK_LVDS_RX+
CLK_LVDS_RX-
PMC_AD32
PMC_PAR64
LVDS_RX+15
PMC_C/BE#7
PMC_C/BE#5
PMC_C/BE#6
PMC_C/BE#4
RPACK8, 10K, DNI
RP5
RPACK8, 10K, DNI
RP15
+3.3V
RPACK8, 10K, DNI
RP16
+3.3V
0, DNI
0, DNI
0, DNI
0, DNI
0, DNI
0, DNI
0, DNI
0, DNI
0, DNI
0, DNI
ALVDS_TX-1
ALVDS_TX-0
ALVDS_TX-3
ALVDS_TX-2
ALVDS_TX_CLK-
ALVDS_RX_CLK+
ALVDS_RX+2
ALVDS_RX+3
ALVDS_RX+0
ALVDS_RX+1
+3.3V
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
HDR2X20, DNI
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
J1
C
ALTERNATE LVDS HEADER
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
+3.3V
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
+3.3V
RPACK8, 10K, DNI
RP4
Place resistors anywhere on the PMC PCI nets. The
resistor pinouts are optimized for placement close
to the PMC JN3 connector.
Only install if using the PCI function of PMC connector
JN3. If using the LVDS function of JN3, these
resistors must not be installed.
PMC PCI 64-bit Signal Pull-Ups
ALVDS_TX+1
ALVDS_TX+0
ALVDS_TX+3
ALVDS_TX+2
ALVDS_TX_CLK+
ALVDS_RX_CLKALVDS_DESKEW
ALVDS_RX-2
ALVDS_RX-3
ALVDS_RX-0
ALVDS_RX-1
R66
R65
R53
R52
R74
R72
R73
R50
R56
R63
R69
R119
R113
R107
R101
R96
R91
R87
R83
R80
R78
R54
R49
R46
R44
R43
R42
R41
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
100
TERMINATIONS AND LVDS
C
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
+3.3V
RPACK8, 10K, DNI
RP3
B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
4
A
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
0, DNI
0, DNI
0, DNI
0, DNI
0, DNI
0, DNI
0, DNI
0, DNI
0, DNI
0, DNI
0, DNI
PMC_FRAME#
PMC_IRDY#
PMC_TRDY#
PMC_DEVSEL#
PMC_STOP#
PMC_LOCK#
PMC_INTA#
PMC_INTB#
PMC_INTC#
PMC_INTD#
+3.3V
R7
10K
R1
10K
LVDS_TX+1
LVDS_TX+0
LVDS_TX+3
LVDS_TX+2
CLK_LVDS_RX-
PMC_AD37
PMC_AD38
PMC_AD33
PMC_AD34
D
CLK_LVDS_RX-
LVDS_RX-2
LVDS_RX-3
LVDS_RX-0
LVDS_RX-1
LVDS_TX+[15..0] 3,8
CLK_LVDS_TX+ 3,8
LVDS_DESKEW 4,8
Place immediately adjacent to associated APEX pins.
R10
10K
R6
10K
R31
10K
Date:
Size
C
Title
R32
10K
R35
10K
R34
10K
R36
10K
R38
10K
E
E
Monday, October 09, 2000
Document Number
Terminations and LVDS Hdr
R33
10K
PMC PCI 32-bit Signal Pull-Ups
Only install if using the LVDS RX function of PMC
connector JN3. If using the PCI function of JN3, these
resistors must not be installed.
LVDS Receive Termination
4,8 PMC_GNT#
4,8 PMC_REQ#
4,8 PMC_ACK64#
4,8 PMC_REQ64#
4,8 PMC_SERR#
4,8 PMC_PERR#
4,8
4,8
4,8
4,8
4,8
4,8
4,8
4,8
4,8
4,8
D
R37
10K
Sheet
R40
10K
7
R39
10K
of
R16
10K
14
R15
10K
Rev
B03
1
2
3
4
1
2
3
4
+3.3V
C23
0.1UF
CLK_PMC
C59
0.1UF
4 PMC_SDONE
4 PMC_PAR
PMC_C/BE#6
PMC_C/BE#4
PMC_AD63
PMC_AD61
PMC_AD59
PMC_AD57
PMC_AD55
PMC_AD53
PMC_AD51
PMC_AD49
PMC_AD47
PMC_AD45
PMC_AD43
PMC_AD41
PMC_AD39
PMC_AD37
PMC_AD35
PMC_AD33
LVDS_RX+14
LVDS_RX-14
LVDS_RX+12
LVDS_RX-12
LVDS_RX+10
LVDS_RX-10
LVDS_RX+8
LVDS_RX-8
LVDS_RX+6
LVDS_RX-6
LVDS_RX+4
LVDS_RX-4
LVDS_RX+2
LVDS_RX-2
LVDS_RX+0
LVDS_RX-0
PMC_AD2
PMC_AD0
PMC_AD6
PMC_AD4
PMC_AD12
PMC_AD9
PMC_AD22
PMC_AD19
PMC_AD28
PMC_AD25
LVDS_RX+16
LVDS_RX-16
A
C25
0.1UF
C36
0.1UF
C37
0.1UF
Place 2 per slot on JN1, JN3, and JN4.
4,7 CLK_LVDS_RX+
4,7 CLK_LVDS_RX-
4,7 PMC_DEVSEL#
4,7 PMC_FRAME#
4,7 PMC_REQ#
11
4,7 PMC_INTB#
4
PMC_BM1
4,7 PMC_INTD#
3,9,10 JTAG_TCK
4,7 PMC_AD[63..0]
4,7 PMC_C/BE#[7..0]
A
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
C47
0.1UF
Place 4 on JN2.
+3.3V
+3.3V
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
C14
0.1UF
B
C18
0.1UF
PMC_AD3
PMC_AD1
PMC_C/BE#0
PMC_AD5
PMC_AD15
PMC_AD11
PMC_AD17
PMC_C/BE#3
PMC_AD21
PMC_AD31
PMC_AD27
LVDS_RX+5
LVDS_RX-5
LVDS_RX+3
LVDS_RX-3
LVDS_RX+1
LVDS_RX-1
PMC_AD44
PMC_AD42
PMC_AD40
PMC_AD38
PMC_AD36
PMC_AD34
C26
0.1UF
LVDS_RX+7
LVDS_RX-7
PMC_AD48
PMC_AD46
C22
0.1UF
+5.0V
C24
0.1UF
C
C19
0.1UF
Place on JN1 next to +5.0V power pins
LVDS_DESKEW 4,7
LVDS_RX+9
LVDS_RX-9
PMC_AD52
PMC_AD50
PMC_AD32
LVDS_RX+11
LVDS_RX-11
PMC_AD56
PMC_AD54
LVDS_RX+15
LVDS_RX-15
LVDS_RX+13
LVDS_RX-13
PMC_PAR64 4,7
LVDS_RX+17
LVDS_RX-17
PMC_REQ64# 4,7
PMC_LOCK# 4,7
PMC_SBO# 4
PMC_IRDY# 4,7
PMC_GNT# 4,7
PMC_INTA# 4,7
PMC_INTC# 4,7
PMC_AD[63..0]
PMC_C/BE#[7..0]
PMC_IDSEL
PMC_BM2
PMC_RST#
C21
0.1UF
-12V
C9
0.1UF
Place on JN1 next to -12V
power pin
3,7 CLK_LVDS_TX+
3,7 CLK_LVDS_TX-
3,7 LVDS_TX+[15..0]
3,7 LVDS_TX-[15..0]
4,7 PMC_ACK64#
4,7 PMC_PERR#
4,7 PMC_TRDY#
4
4
4
3,9,10 JTAG_TMS
9,10 JTAG_PMC_TDI
PMC PCI Expansion
C
PMC_AD60
PMC_AD58
PMC_AD62
PMC_C/BE#7
PMC_C/BE#5
-12V +5.0V
Place next to +3.3V power pins.
PMC_RECEPTACLE
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
JN3
PMC_RECEPTACLE
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
JN1
B
+3.3V
+3.3V
+12V
D
+12V
C10
0.1UF
Place on JN2 next to +12V
LVDS_TX+0
LVDS_TX-0
LVDS_TX+2
LVDS_TX-2
LVDS_TX+4
LVDS_TX-4
LVDS_TX+6
LVDS_TX-6
LVDS_TX+8
LVDS_TX-8
LVDS_TX+10
LVDS_TX-10
LVDS_TX+12
LVDS_TX-12
LVDS_TX+14
LVDS_TX-14
LVDS_TX+16
LVDS_TX-16
PMC_AD8
PMC_AD7
PMC_C/BE#1
PMC_AD14
PMC_AD18
PMC_AD16
PMC_AD24
PMC_AD30
D
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
PMC_RECEPTACLE
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
JN4
PMC_RECEPTACLE
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
power pin
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
JN2
PMC_AD13
PMC_AD10
PMC_C/BE#2
PMC_AD23
PMC_AD20
PMC_AD29
PMC_AD26
PMC_TRST#
Date:
Size
C
Title
LVDS_TX+1
LVDS_TX-1
LVDS_TX+3
LVDS_TX-3
LVDS_TX+5
LVDS_TX-5
LVDS_TX+7
LVDS_TX-7
LVDS_TX+9
LVDS_TX-9
R2
10K
E
Monday, October 09, 2000
Document Number
PMC Expansion
LVDS_TX+11
LVDS_TX-11
LVDS_TX+13
LVDS_TX-13
LVDS_TX+15
LVDS_TX-15
LVDS_TX+17
LVDS_TX-17
+3.3V
+3.3V
E
Sheet
8
of
PMC_SERR# 4,7
PMC_STOP# 4,7
PMC_BM3 4
PMC_BM4 4
JTAG_PMC_TDO 10
14
Rev
B03
1
2
3
4
1
2
3
4
CLK50_PLD
3,8,10
3,8,10
3,10
10
A
3 FLASH_RESET#
3 FLASH_RDY_BSY#
3 FLASH_D[7..0]
3 FLASH_A[21..0]
3 FLASH_CE#
3 FLASH_OE#
3 FLASH_WE#
10 CFGPLD_SW_RSVD0
10 CFGPLD_SW_RSVD1
JTAG_TCK
JTAG_TMS
JTAG_CFGPLD_TDI
JTAG_CFGPLD_TDO
3 CFG_FLASH_PGM[3..0]
3 CFG_STROBE
3 CFG_SEL_EPC4_FLASH#
3 CFG_SEL_EPC41_0#
3 APEX_NCONFIG
3 APEX_NSTATUS
3 APEX_CONF_DONE
3 APEX_DATA0
10 APEX_SEL[3..0]
1M, DNI
C81
0.1UF, DNI
R84
10 SEL_EPC4_FLASH#
10 EPC4_SEL1_0#
3,10 DEF_FLASH_PGM[3..0]
11
+3.3V
Power On Reset
RPACK8, 1K
+3.3V
RP19
+3.3V
RP22
RPACK8, 1K
CFG_FLASH_PGM0
CFG_FLASH_PGM1
CFG_FLASH_PGM2
CFG_FLASH_PGM3
APEX_SEL3
APEX_SEL2
APEX_SEL1
APEX_SEL0
DEF_FLASH_PGM3
DEF_FLASH_PGM2
DEF_FLASH_PGM1
DEF_FLASH_PGM0
The RC reset circuitry is not used. Once the 3256A
has completed its power-on sequence, it enables its
logic which immediately begins a configuration.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
119
126
128
139
1
2
12
19
34
35
36
43
46
47
48
49
66
75
90
103
108
120
121
122
89
20
4
104
134
133
132
131
138
137
136
143
142
141
140
110
109
107
106
116
113
112
111
118
117
125
127
IO_RSVD
IO_RSVD/DEDIN/OE1
IO_RSVD
IO_RSVD
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
JTAG_TCK
JTAG_TMS
JTAG_TDI
JTAG_TDO
CFG_FLASH_PGM0
CFG_FLASH_PGM1
CFG_FLASH_PGM2
CFG_FLASH_PGM3
CFG_STROBE
CFG_SEL_EPC4_FLASHn
CFG_SEL_EPC41_0#
APEX_nCONFIG
APEX_nSTATUS
APEX_CONF_DONE
APEX_DATA0
APEX_CFG_ADDR_MASK3
APEX_CFG_ADDR_MASK2
APEX_CFG_ADDR_MASK1
APEX_CFG_ADDR_MASK0
DEFAULT_FLASH_PROGRAM3
DEFAULT_FLASH_PROGRAM2
DEFAULT_FLASH_PROGRAM1
DEFAULT_FLASH_PROGRAM0
SEL_EPC4/FLASH#
EPC4_SEL1/0#
CLK
RESET#
U9
+3.3V
B
B
C
FLASH_CE#
FLASH_OE#
FLASH_WE#
FLASH_D7
FLASH_D6
FLASH_D5
FLASH_D4
FLASH_D3
FLASH_D2
FLASH_D1
FLASH_D0
FLASH_RDY/BSY#
FLASH_RESET#
71
70
69
68
67
65
63
62
61
60
56
55
54
31
30
29
28
27
25
23
22
21
18
16
15
14
11
10
9
8
7
6
5
38
32
FLASH_A21
FLASH_A20
FLASH_A19
FLASH_A18
FLASH_A17
FLASH_A16
FLASH_A15
FLASH_A14
FLASH_A13
FLASH_A12
FLASH_A11
FLASH_A10
FLASH_A9
FLASH_A8
FLASH_A7
FLASH_A6
FLASH_A5
FLASH_A4
FLASH_A3
FLASH_A2
FLASH_A1
FLASH_A0
102
101
100
99
98
97
96
93
92
91
88
87
86
84
83
82
81
80
79
78
74
72
41
40
39
37
45
44
42
53
C
+3.3V
RP21
RPACK8, 1K
Pull nCS EPC4 pins
high for slave mode.
CONFIGURATION CIRCUIT
EPM3256ATC144-7
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
IO_RSVD
SW_RSVD0
SW_RSVD1
FLASH_RY/BY#
FLASH_RESET#
FLASH_DATA7
FLASH_DATA6
FLASH_DATA5
FLASH_DATA4
FLASH_DATA3
FLASH_DATA2
FLASH_DATA1
FLASH_DATA0
FLASH_CE#
FLASH_OE#
FLASH_WE#
FLASH_A21
FLASH_A20
FLASH_A19
FLASH_A18
FLASH_A17
FLASH_A16
FLASH_A15
FLASH_A14
FLASH_A13
FLASH_A12
FLASH_A11
FLASH_A10
FLASH_A9
FLASH_A8
FLASH_A7
FLASH_A6
FLASH_A5
FLASH_A4
FLASH_A3
FLASH_A2
FLASH_A1
FLASH_A0
EPC4_1_OE
EPC4_1_CSn
EPC4_1_INIT_CONFn
EPC4_1_DATA0
EPC4_0_OE
EPC4_0_CSn
EPC4_0_INIT_CONFn
EPC4_0_DATA0
GNDINT
GNDINT
GNDINT
GNDINT
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
A
51
58
123
130
VCCINT
VCCINT
VCCINT
VCCINT
52
57
124
129
8
7
6
5
4
3
2
1
9
10
11
12
13
14
15
16
24
50
73
76
95
115
144
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
3
13
17
26
33
59
64
77
85
94
105
114
135
+3.3V
RP25
RPACK8, 10K
FLASH_A[21..0]
FLASH_D[7..0]
10 JTAG_EPC4_1_TDI
10 JTAG_EPC4_1_TDO
11 CLK50_EPC4_1
3,8,10 JTAG_TCK
3,8,10 JTAG_TMS
10 JTAG_EPC4_0_TDI
8,10 JTAG_EPC4_0_TDO
11 CLK50_EPC4_0
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
D
D
8
5
22
24
9
10
11
FLASH_CE#
FLASH_OE#
FLASH_WE#
FLASH_RESET#
Remove resistor for Flash
without an ACC pin.
29
38
37
13
40
1
2
3
4
5
6
36
7
8
14
15
16
17
18
19
20
21
41
19
38
7
9
30
FLASH_A21
FLASH_A20
FLASH_A19
FLASH_A18
FLASH_A17
FLASH_A16
FLASH_A15
FLASH_A14
FLASH_A13
FLASH_A12
FLASH_A11
FLASH_A10
FLASH_A9
FLASH_A8
FLASH_A7
FLASH_A6
FLASH_A5
FLASH_A4
FLASH_A3
FLASH_A2
FLASH_A1
FLASH_A0
R93
0
+3.3V
Always powered
off +1.8V
C28
0.1UF
+1.8V
2
10
11
12
13
14
15
25
EPC4_1_DATA0
+3.3V
6
39
26
42
16
17
28
29
8
5
41
19
38
7
9
30
JTAG_TCK
JTAG_TMS
EPC4_1_nINIT_CONF
EPC4_1_OE
EPC4_1_nCS
Always powered
off +1.8V
C30
0.1UF
+1.8V
2
10
11
12
13
14
15
25
EPC4_0_DATA0
+3.3V
6
39
26
42
16
17
28
29
JTAG_TCK
JTAG_TMS
EPC4_0_nINIT_CONF
EPC4_0_OE
EPC4_0_nCS
EPC4 #0
Date:
Size
C
Title
RESET#
ACC
CE#
OE#
WE#
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
U13
EPC4_PLCC44
VCCINT
GND
VPP
VCCIO
VCCSEL
VPPSEL
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
TCK
TMS
TDI
TDO
OE
nCS
nCASC
nINIT_CONF
FLASH_RDY/BSY#
12
E
Monday, October 09, 2000
Document Number
Configuration PLD
Sheet
FLASH_D7
FLASH_D6
FLASH_D5
FLASH_D4
FLASH_D3
FLASH_D2
FLASH_D1
FLASH_D0
1
3
4
18
20
21
22
23
24
27
31
32
33
34
35
36
37
40
43
44
1
3
4
18
20
21
22
23
24
27
31
32
33
34
35
36
37
40
43
44
E
35
34
33
32
28
27
26
25
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
nc
AM29LV033C_TSOP40
RY/BY#
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
EPC4 #1
DCLK
EXCLK
U5
EPC4_PLCC44
VCCINT
GND
VPP
VCCIO
VCCSEL
VPPSEL
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
TCK
TMS
TDI
TDO
OE
nCS
nCASC
nINIT_CONF
DCLK
EXCLK
U4
30
31
VCC
VCC
GND
GND
23
39
9
of
14
Rev
B03
1
2
3
4
1
2
3
4
3
1
7
8
12
11
10
9
2
PCI_M66EN
3,9 JTAG_APEX_TDO
9 JTAG_EPC4_1_TDO
9 JTAG_EPC4_0_TDI
8 JTAG_PMC_TDO
2 PCI_PCIXCAP
3,9 JTAG_CFGPLD_TDI
5
6
13
14
1
3
5
7
9
R116
10K, DNI
R103
10K, DNI
R115
10K, DNI
R109
10K
2
4
6
8
10
12
14
A
APEX_SEL[3..0] 9
JTAG_TCK 3,8,9
R59
10K
R114
10K
R108
10K, DNI
APEX_SEL3
APEX_SEL2
APEX_SEL1
APEX_SEL0
Notes
Invalid
APEX 20K200E
APEX 20K400E
APEX 20K1000E
B
JTAG_APEX_TDI 3
NOT_PCIXCAP
PCIX66_CAP
JTAG_CFGPLD_TDO 9
JTAG_EPC4_1_TDI 9
JTAG_EPC4_0_TDO 8,9
JTAG_PMC_TDI 8,9
JTAG_TMS 3,8,9
APEX_SEL[3..0] are set when the APEX is soldered to the board. These signals
indicate the size of the configuration file required to program the APEX.
They are used as mask bits for user flash program selection.
SEL3 SEL2 SEL1 SEL0
All other settings
1
1
1
1
1
1
1
0
1
0
0
0
R24
10K
APEX_SEL[3..0]
2
4
6
8
10
12
14
PMC
EPC4 #0
EPC4 #1
Config PLD
JTAG_HDR_TDO
R23
1K
+3.3V
R26
1K
HDR2X7
1
3
5
7
9
11
13
J8
R25
1K
1
3
5
7
9
11
13
Include
Include
Include
Include
JTAG_TCK
JTAG_HDR_TDI
JTAG_TMS
R60
10K
+3.3V
PMC
EPC4 #0
EPC4 #1
Config PLD
OFF
OFF
OFF
OFF
Skip
Skip
Skip
Skip
Jumper:
Jumper:
Jumper:
Jumper:
ON
ON
ON
ON
OFF 33/66 MHz Std PCI
OFF PCIX 133 MHz
OFF PCIX Capable
Jumper: ON 33 MHz Std PCI
M66EN indicates to the PCI motherboard whether the APEX PCI core supports 66 MHz or 33
MHz PCI. Since different cores may be used on the board, a jumper option is
implemented to allow the user to set the status of the M66EN pin which controls the
frequency of the PCI bus.
Information Option: APEX Cfg Addr Mask
R110
10K
HEADER10A
2
4
6
8
10
J2
R98
10K
+3.3V
+3.3V
Configuration Option Block:
To accomodate different user configurations, jumper options are implemented to allow the
user to maintain JTAG chain connectivity even though some devices may not be installed.
Jumper: ON PCIX 66 MHz
Jumper: ON Standard PCI
MasterBlaster /
ByteBlasterMV Download
Cable Header - JTAG
Only
4
2
B
C
C
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
SW_DIP-10
S1
JTAG AND USER OPTIONS
+3.3V
D
RP2
RPACK8, 10K
16
15
14
13
12
11
10
9
D
1
2
3
4
5
6
7
8
A
ON
R29
10K
R30
10K
Date:
Size
C
Title
E
Monday, October 09, 2000
Document Number
JTAG Circuit
DEF_FLASH_PGM0
DEF_FLASH_PGM1
DEF_FLASH_PGM2
DEF_FLASH_PGM3
CFGPLD_SW_RSVD[1..0] reserved for future use.
Option: Reserved
APEX_SW_RSVD[1..0] reserved for future use.
Option: Reserved
Sheet
10
of
14
SEL_EPC4_FLASH# 9
EPC4_SEL1_0# 9
APEX_SW_RSVD0 3
APEX_SW_RSVD1 3
CFGPLD_SW_RSVD0 9
CFGPLD_SW_RSVD1 9
DEF_FLASH_PGM[3..0] 3,9
EPC4_SEL1_0# selects which EPC4 to use during EPC4 power on configuration.
When 1 selects EPC4 #1. When 0 selects EPC4 #0.
Rev
B03
Option: Default EPC4 for Power On Configuration
SEL_EPC4_FLASH# selects power on configuration from EPC4 when 1 and from
Flash when 0.
Option: Power On Configuration Source
DEF_FLASH_PGM[3..0] control the highest 4 address bits of the byte-wide Flash
memory to enable the selection of up to 16 different APEX configuration
programs. The configuration PLD ignores all DEF_FLASH_PGM bits for which the
APEX_SEL[3..0] is set to 0. Thus, fewer than 16 programs are selectable for
the larger devices.
Option: Default Flash Program
E
1
2
3
4
1
2
3
4
4
1
8
OUTPUT
HALFSIZE_OSC
GND
OE
VCC
U11
5
CLK_PCI_EDGE
CLK_OSC_SOCKET
CLK_APEX_CLKOUT1
3 CLK_APEX_CLKOUT1
A
CLK_APEX_CLKOUT0
3 CLK_APEX_CLKOUT0
0, DNI
R106
R104
22
R112
R111
R121
R120
R118
R117
S
R
D
C
B
A
0, DNI
22
0
22, DNI
0, DNI
22
R100
R99
R95
R94
R86
R85
R82
R90
R89
B
N
M
L
K
J
H
G
F
E
22, DNI
22, DNI
22
22, DNI
22, DNI
22
0, DNI
22, DNI
22, DNI
C
C
CLK_SODIMM1 5
CLK_SODIMM0 5
CLK_PMC 8
CLK_DAUGHTER_CARD 12
CLK_APEX_CLK1 3
CLK_APEX_CLK0 3
CLK_DAUGHTER_OSC 12
Current clock DNI options assume that APEX
devices with PLLs are installed on the board
and SDR SDRAM is implemented for the SODIMM
interface.
Clock Distribution
APEX Source Clock Selection
B
Module Source Clock Selection
0, DNI
R105
OPTION: PCI may only have 1 clock load to be compliant
with the PCI specification, so only one of resistors
B, D, and S may be installed.
LAYOUT: Place CLK_PLL_CLKOUTx option resistors near
CLK_APEX_CLKOUTx source to reduce stub length.
LAYOUT: Resistors A through S are important
option resistors. The letters next to the
resistors appear in the layout for easy
identification.
LAYOUT: Place B, D, and S directly
adjacent to edge finger PCI_CLK pin.
LAYOUT: Place A, C, and R directly
adjacent to oscillator socket.
2 CLK_PCI_EDGE
C80
0.1UF
+3.3V
A
C62
0.1UF
C82
0.1UF
+3.3V
+3.3V
OUTPUT
HALFSIZE_OSC
GND
OE
VCC
U12
4
1
6
U8
D
CLK1
CLK2
CLK3
CLK4
CLKOUT
CY2305
GND
REF
Vdd
E
5
3
2
5
7
8
CLK_PLL_CLKOUT1
CLK_PLL_OSC_EXTRA
CLK_PLL_PMC
CLK_PLL_CLKOUT0
CLK50_OSC
22
R102
CLK50_APEX 3
CLK50_PLD 9
CLK50_EPC4_1 9
CLK50_EPC4_0 9
Date:
Size
C
Title
22
22
E
Monday, October 09, 2000
Document Number
Clock Distribution
R76
R67
Sheet
11
of
CLK_OSC_EXTRA 3
CLK_PLL_PMC may be used to clock PMC logic when the APEX
device is interfacing to DDR SDRAM. DDR SDRAM requires both
APEX clock outputs to be dediacated to the SODIMM due to the
need to generate a differential clock.
CLK_OSC_EXTRA is used to clock APEX logic when APEX
devices without internal PLLs are used on the board.
Extra APEX Clock Input
Place resistors at clock oscillator clock output
pin. Match trace lengths of these clocks.
22
22
22
R97
R92
R88
Configuration Clock Distribution
Optional Zero Delay Buffer for
using non-PLL APEX devices.
4
1
8
D
14
Rev
B03
1
2
3
4
2
4
6
8
10
12
14
16
18
20
HDR2X10
1
3
5
7
9
11
13
15
17
19
J7
2
4
6
8
10
12
14
16
18
20
2
4
6
8
10
12
14
LCD_D1
LCD_D3
LCD_D5
LCD_D7
LCD_RS 3
LCD_E 3
C
3
3
3
3
3
3
3
3
3
3
IDE_DRQ3
IDE_IOW#
IDE_IOR#
IDE_IOCHRDY
IDE_DACK3
IDE_IRQ14
IDE_ADDR1
IDE_ADDR0
IDE_CHIPSEL0#
IDE_ACTIVITY
3 IDE_RESET_IDE
IDE_HOSTDATA7
IDE_HOSTDATA6
IDE_HOSTDATA5
IDE_HOSTDATA4
IDE_HOSTDATA3
IDE_HOSTDATA2
IDE_HOSTDATA1
IDE_HOSTDATA0
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
HDR2X20
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
J5
D
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
IDE_HOSTDATA[15..0]
IDE_ADDR2 3
IDE_CHIPSEL1# 3
IDE_IOCS16# 3
IDE_BALE 3
IDE_HOSTDATA8
IDE_HOSTDATA9
IDE_HOSTDATA10
IDE_HOSTDATA11
IDE_HOSTDATA12
IDE_HOSTDATA13
IDE_HOSTDATA14
IDE_HOSTDATA15
Title
Daughter Card
E
Sheet
12
of
14
Rev
B03
3
4
Date:
Size
C
E
Monday, October 09, 2000
Document Number
1
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
HDR2X7
1
3
5
7
9
11
13
J4
3 IDE_HOSTDATA[15..0]
D
1
B
+3.3V
LCD_D0
LCD_D2
LCD_D4
LCD_D6
1
3
5
7
9
11
13
LCD_D[7..0]
DAUGHTER CARD
C
2
A
LCD_RW
LCD_D[7..0]
11 CLK_DAUGHTER_OSC
11 CLK_DAUGHTER_CARD
3
3
B
2
3
4
A
1
2
3
4
C11
0.1uF
A
+
A
C1
47UF
R3
10K
ADJUST
OUTPUT
GND TAB
MIC29152BU
GND
INPUT
ENABLE
U1
6
5
4
VOUT = 1.240V * (1 + (R1/R2))
3
2
1
+
+3.3V
1
2
3
4
5
6
C7
47UF
+
C3
47UF
+
VIO
HDR1X6_PWR
1
2
3
4
5
6
J3
BULK DECOUPLING
+3.3V
C4
47UF
Do not use if the board is plugged into a PCI slot.
B
R1_PWR_ADJ
+2.5V Supply
Auxiliary Power Header
R1_PWR_EN
+3.3V
B
R11
1.00K,1%
R12
1.00K,1%
+
C2
47UF
+2.5V
C20
0.01uF
C
C
C56
0.1uF
+
C5
47UF
POWER SUPPLIES
R48
10K
ADJUST
OUTPUT
GND TAB
MIC29152BU
GND
INPUT
ENABLE
U6
6
5
4
+2.5V
R2_PWR_ADJ
R79
1.00K,1%
R77
1.00K,1%
VIO SELECTION
C74
0.1uF
C78
0.1uF
C84
0.1uF
C87
0.1uF
VREF
R62
2.21K,1%
R61
1.00K,1%
VREF GENERATION AND DECOUPLING
VOUT = 1.240V * (1 + (R1/R2))
3
2
1
+1.8V Supply
+3.3V
R27
0, DNI
R28
0
R17
0, DNI
R18
0
+2.5V
R14
0
R13
0, DNI
D
R9
0
R8
0, DNI
R5
0
R4
0, DNI
VIO
Install either +3.3V or +2.5V resistors depending upon the desired
VIO power plane. DDR requires +2.5V. All others use +3.3V.
R2_PWR_EN
+3.3V
D
+
C6
47UF
+1.8V
Date:
Size
C
Title
C65
0.01uF
E
Monday, October 09, 2000
Document Number
Power Supplies
E
VCC
Sheet
13
of
For SSI gates with
hidden power pins
+3.3V
14
Rev
B03
POWER ALIASES
1
2
3
4
1
2
3
3
3
3
3
3
RS232_DSR
RS232_RX
RS232_CTS
RS232_CD
RS232_RI
3 RS232_TX
3 RS232_DTR
3 RS232_RTS
A
3
+3.3V
2
21
23
22
19
18
17
16
15
20
14
13
12
1
C2NEG
24
28
C2POS
C1NEG
LED#[7..0]
C67
0.1UF
C72
0.1UF
INVALID#
B
LED#[7..0]
MAX3243E
16
15
14
13
12
11
10
9
+3.3V
RPACK8, 22, DNI
RP26
FORCEON
FORCEOFF#
R1OUT
R2OUT
R3OUT
R4OUT
R5OUT
R2OUTB
T1IN
T2IN
T3IN
C2-
C2+
C1-
C1+
U10
1
2
3
4
5
6
7
8
26
V-
V+
4
5
6
7
8
9
10
11
3
27
LED#7
LED#6
LED#5
LED#4
LED#3
LED#2
LED#1
LED#0
R1_RS232_IN
R2_RS232_IN
R3_RS232_IN
R4_RS232_IN
R5_RS232_IN
T1_RS232_OUT
T2_RS232_OUT
T3_RS232_OUT
VCC
GND
25
C1POS
B
C71
0.1UF
+3.3V
C68
0.1UF
C76
0.1UF
C
DB9-MALE
RPACK8, 10K
RP1
C
12
9
5
2
12
9
5
2
11
U3D
74VHC125
8
U3C
74VHC125
6
U3B
74VHC125
3
U3A
74VHC125
11
U2D
74VHC125
8
U2C
74VHC125
6
U2B
74VHC125
3
U2A
74VHC125
BLED#7
BLED#6
BLED#5
BLED#4
BLED#3
BLED#2
BLED#1
BLED#0
General Purpose APEX Controlled LEDs
R_DSR
R_RX
R_CTS
R_CD
R_RI
R_TX
R_DTR
R_RTS
JP1
MISCELLANEOUS
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
OPTION: Don't use transceiver
1
4
10
13
1
4
10
13
4
A
5
9
4
8
3
7
2
6
1
3
3
5
D
6
7
8
4
LED-QUAD4
LED2
3
2
1
5
4
7
8
6
LED-QUAD4
LED1
3
2
1
SW_GP0
SW_GP1
D
+3.3V
+3.3V
+3.3V
C17
0.1UF
R22
10K
C16
0.1UF
R20
10K
SHIELD
4
2
4
Date:
Size
C
Title
E
Monday, October 09, 2000
Document Number
Miscellaneous
SW_NO_MOMENTARY
2
SHIELD
3
SW2
SW_NO_MOMENTARY
SW1
1
3
1
General Purpose Right Angle Switches
E
Sheet
R21
1K
R19
1K
14
of
14
Rev
B03
1
2
3
4