Scripting with Tcl in the Quartus II
Software
December 2002, ver. 1.1
Introduction
Application Note 195
Developing and running tool command language (Tcl) scripts in the
Altera® Quartus® II software allows you to perform a wide range of simple
or complex functions, such as compiling a design or writing procedures to
automate common tasks. This application note describes and gives
examples on how to develop Tcl scripts for the Quartus II software, and
also describes how to make LogicLockTM assignments using Tcl
commands. You can modify the example scripts from this application note
and use them for your own design.
1
The Quartus II software version 2.0 and higher supports Tcl/Tk
version 8.0.3, supplied by the Tcl DeveloperXchange at
http://tcl.activestate.com.
You can automate your Quartus II assignments using Tcl scripts so that
you do not have to create them individually. Tcl scripts also facilitate
project or assignment migration. For example, when using the same
prototype or development board for different projects, you do not have to
manually reassign your pin locations in each new project; you can use a
Tcl script that you run for each project. The Quartus II software can also
generate a Tcl script based on all the current assignments in the project,
which is very useful for documenting assignments and migrating the
assignments to another project.
What is Tcl?
Tcl (pronounced tickle) is a popular scripting language that is similar to
many shell scripting and high-level programming languages. It provides
support for control structures, variables, network socket access, and
application programming interfaces (APIs) for integration. Tcl is the EDA
industry-standard scripting language used by Synopsys,
Mentor Graphics®, and Synplicity® software tools.
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AN-195-1.1
Tcl is an interpreted language that is easy to learn and use. It
allows you to create custom commands or procedures and is
used for multi-platform programming because it works
seamlessly across most development platforms such as UNIX
and Windows NT. For a list of recommended literature on Tcl,
see “References” on page 71.
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You can create your own procedures by writing scripts containing basic
Tcl commands, user-defined procedures, and Quartus II API functions.
You can then automate your design flow, run the Quartus II software in
batch mode, or execute the individual Tcl commands interactively within
the Quartus II Tcl Console window.
Running Tcl in
the Quartus II
Software
There are three different ways of running Tcl in the Quartus II software:
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■
■
Interactively in the Tcl Console window
Using scripts in batch mode
Using scripts at the DOS or UNIX command prompt
The Quartus II Tcl interpreter executes both basic (commands that can be
used for any tool) and Quartus II-specific Tcl commands.
Running Tcl Commands Interactively
You can execute Tcl commands directly in the Quartus II Tcl Console
window. To open the Tcl Console window, choose Auxiliary Windows
(View menu) then Tcl Console. Figure 1 shows the interface for opening
the Tcl Console window. The Tcl Console is usually located on the
bottom-right corner of Quartus II graphic user interface (GUI). You can
type Tcl commands directly into the Tcl Console.
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Figure 1. Opening the Tcl Console Window in the Quartus II Software
The Tcl Console window supports a history (list of previous n commands
entered in the Tcl Console window), but it does not allow commands to
span more than one line. Tcl messages appear in the System tab (Messages
window). Errors and messages written to stdout and stderr appear in
the Quartus II Tcl Console window.
Using Scripts in Batch Mode
Once you create a Tcl script file (.tcl), you can run it by typing the
following command in the Tcl Console window:
source <script_name>.tcl r
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Using Scripts from the DOS or UNIX Command-Line Prompt
The Quartus II software supports -f <script_name>.tcl command- line
arguments. You must have the path to the <quartus_install_dir>\bin
directory in your system path to run Tcl scripts from the command
prompt. Change to your project directory and use the following syntax for
running scripts from the command prompt:
quartus_cmd -f <script_name>.tcl r
When you compile a design by sourcing a Tcl script from the command
prompt, the Quartus II software displays the compilation messages on the
command prompt itself. You can choose to pipe the messages to a file by
using the following syntax:
quartus_cmd -f <script_name>.tcl <textfile> r
The Quartus II software can differentiate whether the Tcl script is running
from the Tcl Console window or from the command line. The command
is_command_line_mode returns 1 if you source the script in the
command-line prompt and returns 0 if you use the Tcl Console window.
Figure 2 shows a Tcl Console code usage example.
Figure 2. Tcl Console Code Usage
# Determines whether the script is running at the command prompt or the
# Tcl Console window.
if {[is_command_line_mode]} {
# If is_command_line_mode returns 1, the script is running at the
# command prompt.
puts "Running from a command line prompt.\n"
} else {
# If is_command_line_mode returns 0, the script is running from the Tcl
# Console window.
puts "Running script from the Tcl Console.\n"
}
Basic Tcl
Commands
4
The following sections discuss basic Tcl commands, including basic
syntax, Tcl API functions in the Quartus II software, Quartus II templates,
Quartus II basic assignments, and Tcl file generation in the Quartus II
software.
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Basic Syntax
The basic syntax for a Tcl command is:
<command> [<argument1> <argument2> <argument3>]
You can substitute the command variable with one of the following:
■
■
■
Quartus II built-in API functions (e.g., project)
User-defined procedures (e.g., proc my_project {})
Generic Tcl commands (e.g., expr)
1
Spaces separate commands and arguments, and a new line
character or semicolon terminates commands. Arguments to
commands are passed as quoted strings.
Tcl API Functions in the Quartus II Software
You can use Quartus II API functions to perform common actions such as
creating projects and specifying the Compiler and Simulator settings. A
few of the common tasks that you can easily automate are:
■
■
■
■
Make assignments
Compile designs
Perform timing analysis
Run simulations
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For a sample basic script that you can use with the Quartus II
Tutorial design, go to the Altera web site at
http://www.altera.com
Quartus II API functions are divided into the following categories:
■
■
■
■
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■
■
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Project functions
Compiler functions
Timing analysis functions
LogicLock functions
Simulator functions
Software build functions
Device database functions
Global functions
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For a detailed list of Quartus II Tcl commands, search for
“API syntax” in the Quartus II on-line Help. To see command
details with available command options, click the command
name in the function category.
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Quartus II Templates
The Quartus II software also provides two sets of template for the most
common procedures:
■
■
Tclthis template lists the syntax for general Tcl procedures and
non-Quartus II-specific basic Tcl commands.
Quartus II Tclthis template displays the syntax for Quartus IIspecific commands.
To open the templates, choose Template (Insert menu) with the Quartus II
text editor open. Figure 3 shows the Generic Tcl Template window, and
Figure 4 shows the Quartus II Tcl Template window.
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Figure 3. Tcl Template Window
Figure 4. Quartus II Tcl Template Window
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You must modify the variables from the template that starts with “__” as
those variables are design-dependent. For example, in the compile
template shown in Figure 4, you must substitute the __cmp variable with
the active Compiler setting in your design. The Tcl Console displays the
following error when you try to run the code as displayed in the template:
cmp does not exist: __cmp
Quartus II Basic Assignments
Quartus II Tcl commands can perform common tasks such as controlling
projects and working with the Compiler and Simulator. The Quartus II
software saves the settings in different setting files based on assignment
types. Table 1 outlines the different Quartus II settings files.
Table 1. Files Containing Quartus II Assignments
File Type
Quartus File (.quartus)
Description
Contains the project configuration.
Project Settings File (.psf)
Contains settings for the entire project.
Compiler Settings File (.csf)
Contains settings for the Compiler
(e.g., pin locations).
Entity Settings File (.esf) (1)
Contains parameter settings for individual
entities and nodes (e.g., timing constraints).
Simulator Settings File (.ssf)
Contains settings for the Simulator.
Software Build Setting File (.fsf)
Contains settings for the Software Builder.
Note to Table 1:
(1)
8
There will be an ESF for every entity in which settings are made.
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Before performing any other task, you must create a new project or open
an existing one using the appropriate Quartus II API function. After
creating or opening a project, you can use Tcl commands to add design
files, make device assignments, and create project-wide or entity-specific
assignments. Table 2 shows the syntax for commands to add or remove an
assignment for a project.
Table 2. Add or Remove Assignments
Command
Description
project add_assignment
<section identifier> <source> <target>
<variable> <value>
Adds or changes an assignment in the specified section
of the project’s current PSF and QUARTUS file, or in
one of the project’s ESF if a design entity is specified.
cmp add_assignment
<section identifier> <source> <target>
<variable> <value>
Adds or changes an assignment in the specified section
of the project’s current CSF.
sim add_assignment
<section identifier> <source> <target>
<variable> <value>
Adds or changes an assignment in the specified section
of the project’s current SSF.
swb add_assignment
<section identifier> <source> <target>
<variable> <value>
Adds or changes an assignment in the specified section
of the project’s current FSF.
project remove_assignment
<section identifier> <source> <target>
<variable> <value>
Removes an existing assignment from a project’s
current PSF and QUARTUS file, or from one of the
project’s ESF if a design entity is specified.
cmp remove_assignment
<section identifier> <source> <target>
<variable> <value>
Removes an existing assignment from the specified
section in the project’s current CSF.
sim remove_assignment
<section identifier> <source> <target>
<variable> <value>
Removes an existing assignment from the specified
section in the project’s current SSF.
swb remove_assignment
<section identifier> <source> <target>
<variable> <value>
Removes an existing assignment from the specified
section in the project’s current FSF.
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Table 3 defines the argument for the commands in Table 2.
Table 3. Quartus II Tcl Command Arguments
Command
Description
<entity>
Specifies the entity for the assignment being made.
<section identifier>
Identifies the name of the section in the settings file. (1)
<source>
Specifies the beginning instance name for a range of
targets.
<target>
Specifies the ending name for the range of targets started
by <source>.
<variable>
Specifies variable to be added, changed, or removed.
<value>
Specifies the value to be assigned to the variable.
Note to Table 3:
(1)
For a list of sections for each type of settings and configuration files, search for
“Settings and Configuration File Sections” in the Quartus II On-line Help.
Arguments values that do not apply must be passed as empty strings
using quotation marks (""). For example, project-wide assignments
specifying the source files for the project do not need entity-specific
arguments.
Quartus II Tcl File Generation
To help you migrate assignments or document your project assignment,
the Quartus II software can now create a Tcl script from a project. Any
assignments in the project are converted to a Tcl command with a click of
a button by choosing Generate Tcl File for Project (Project menu).
Figure 5 shows the Generate Tcl File for Project dialog box from the
Quartus II software.
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Figure 5. Generate Tcl File for Project window
This feature is also useful for migrating assignments, eliminating the need
to save the setting files when archiving the projects. You only need to type
source <script_name>.tcl in the Quartus II Tcl Console window to
create the same setting files as you had when you archived the project. In
addition, you can also add the instructions to compile and simulate the
project, or perform a software build, eliminating the need to save your
compilation result. The Quartus II software will then automatically
compile, simulate, or perform a software build when you source the Tcl
file. You may find this automated feature useful when you are comparing
compilation results between your project versions.
Creating
Quartus II
Projects
This section gives examples on how to set up a working directory, delete
an existing project, create or open a project, close a project, archive or
restore a project, and add source files to a project. Table 4 summarizes the
Quartus II Tcl commands used in the following sections.
Table 4. Commonly used Quartus II Project Commands (Part 1 of 2)
Command
Description
project exists <name>
Verifies if a project called <name> already exists to prevent errors when
creating a project. This command returns 1 if the statement is true and
returns 0 if the statement is false.
project create <name>
Creates a Quartus II project called <name> and its auxiliary files,
including <name>.quartus.
project open <name>
Opens an existing Quartus II project called <name>.
project close
Closes the current Quartus II project.
project archive <archive_name> Provides a method of backing up a project and its related files in the form
of a single Quartus II Archive File (.qar). The list of files to be archived
is selected automatically and can be added to or changed. Any file or
directory name, if not absolute, is assumed relative to the project
directory. Optional arguments or options can come in any sequence.
project restore <archive_name> Extracts files from the QAR file and places them in the target directory.
<target directory>
A new directory is created if a target directory does not yet exist.
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Table 4. Commonly used Quartus II Project Commands (Part 2 of 2)
Command
Description
project start_batch <entity>
Accelerates the assignment process when many assignment
commands (e.g., project add_assignment) are used in a script.
Add this command before the set of commands. Add
project end_batch after the set of commands.
project end_batch <entity>
Accelerates the assignment process when many assignment
commands (e.g., project add_assignment) are used in a script.
Add this command after the set of commands.
Setting up a Working Directory & Deleting Old Projects
Before setting up a project, you must ensure that the directory does not
already have a Quartus II project or Quartus II project files with the same
name. If a project exists, you can either choose to delete it and create a new
project or open the existing project. Change to the working directory
shown in Figure 6.
Figure 6. Working Directory
# The code below changes the directory to d:\qdesigns\tutorial, which is
# your working directory.
cd d:\qdesigns\tutorial
If you want to delete an existing project, the following code removes the
project-related files: <project>.quartus, setting files, and db directory
(see Figure 7).
Figure 7. Code that Removes Project-Related Files
# If a project called filtref exist in the working directory, delete the
# QUARTUS, PSF, ESF, CSF, SSF, and FSF files and the db directory
if [project exists filtref] {
file delete -force filtref.quartus
file delete -force filtref.psf
file delete -force filtref.esf
file delete -force filtref.csf
file delete -force filtref.ssf
file delete -force filtref.fsf
file delete -force db
}
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Creating a New Project, Opening & Closing a Project
Figure 8 shows example code to create a project for the Quartus II Tutorial
design.
Figure 8. Example Code for Opening a Project
# Create a project called filtref in the working
# directory.
project create filtref
# Open the project filtref located in the working
# directory.
project open filtref
You can use an if-then-else statement if you do not want to create a new
project each time you run the Tcl script. Figure 9 shows an example to
create a project if it does not exist, or open the project if it does exists.
Figure 9. Example Code for Creating a Project
# If the project filtref does not exist, create one.
if [!project exists filtref] {
project create filtref
}
# Open the project filtref.
project open filtref
Use the code in Figure 10 to close a project.
Figure 10. Example Code for Closing a Project
# Close the project.
project close
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Adding Source Files
Source files are added to the project using the project
add_assignment command. When you have a sequence of project
add_assignment commands, place project start_batch before the
sequence and project end_batch after the sequence to eliminate the
overhead when the Quartus II software performs the commands which in
turn will speed up the assignment process. See Figure 11.
Figure 11. Adding Source Files Example
# Start a batch of project commands.
project start_batch filtref
# Add the following design files to the already open project:
# filtref.bdf, acc.v, accum.v, hvalues.v, mult.v, state_m.v, and taps.v.
# These files are located in the same directory as the open project.
project add_assignment "" "" "" "" "SOURCE_FILE" "filtref.bdf"
project add_assignment "" "" "" "" "SOURCE_FILE" "acc.v"
project add_assignment "" "" "" "" "SOURCE_FILE" "accum.v"
project add_assignment "" "" "" "" "SOURCE_FILE" "hvalues.v"
project add_assignment "" "" "" "" "SOURCE_FILE" "mult.v"
project add_assignment "" "" "" "" "SOURCE_FILE" "state_m.v"
project add_assignment "" "" "" "" "SOURCE_FILE" "taps.v"
# End a batch of project assignments.
project end_batch filtref
Archiving & Restoring a Project
The Quartus II archive feature allows you to back up a project and its
related files into a single, compressed QAR file. A Quartus Log File
(.quarlog) is created for every archive. The example Tcl commands to
archive and restore a project are shown in Figure 12.
Figure 12. Archiving & Restoring a Project Example
# Archive the open project, name the archive rev1, and save the QAR file
# in the same directory as the open project directory.
project archive rev1
# Restore the rev1 project located in the working directory and extract the
# project files into d:/rev1.
project restore rev1 d:/rev1
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Creating Default Parameters
If a design has any generic parameters (e.g., bus width), you can also
create a default parameter setting through the Tcl command. Table 5
shows the Tcl commands for default parameters.
Table 5. Tcl Commands for Default Parameters
Command
Description
project add_default_parameter
<variable> <value>
Adds or changes the specified default parameter from
the current project. For example:
# Add a default width parameter of value 5
# to the open project.
project add_default_parameter width 5
project remove_default_parameter
<variable>
Removes the specified default parameter to the current
project.
project get_default_parameter_value
<variable>
Returns the value of the specified default parameter.
project get_all_default_parameters
Returns the value of all default parameters in the
project.
Retrieving Project Assignment Values
Table 6 shows the Tcl commands that you can use to retrieve project
assignments from the project’s PSF.
Table 6. Tcl Commands for Retrieving Assignment Values
Command
Description
project get_assignment_value
<section identifier> <source> <target>
<variable>
Returns the value of the specified variable.
For example:
# Find out which clock settings that
# you assigned to the node clk.
project get_assignment_value "filtref"
"clk" "" "clock_settings"
project get_assignment_count
<section identifier> <source> <target>
Returns the number of assignments for the section,
source, and target.
project get_all_assignments
<section identifier> <source> <target>
Returns the value of all assignments in the section,
source, and target. For example:
# Find out all the assignments in the
# entity filtref where clk is the source.
project get_all_assignments "filtref"
"clk" ""
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Running the
Compiler
You can use a group of Compiler settings, which are saved in a CSF, to
control the Compiler. The active group of Compiler settings is known as
the current Compiler settings. This section offers examples on creating a
group of Compiler settings and controlling the Compiler.
Setting an Active Group of Compiler Settings
You must create an active group of Compiler settings for your design
compilation. Table 7 lists the commands used in this section.
Table 7. Compiler Setting Commands
Command
Description
project cmp_exists <settings>
Checks to see if <settings>.csf already exists.
project create_cmp <settings>
Creates <settings>.csf and designates the settings as the current
Compiler settings for the project.
project set_active_cmp <settings>
Specifies <settings> as the active group of Compiler settings for
compilation in the Quartus II software to be used.
Figure 13 shows the combined commands from Table 7. The code checks
if a Compiler setting already exists. If not, create a setting and set it as the
active Compiler setting.
Figure 13. Example on Creating Compiler Settings
# Checks if Compiler settings filtref already exists.
if {![project cmp_exists filtref]} {
# If filtref.csf does not exist, create one
project create_cmp filtref
# Set Compiler settings filtref as the active
# Compiler setting
project set_active_cmp filtref
}
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Controlling the Compiler
Table 8 lists the commands to start, stop, and check the status of the
Quartus II Compiler.
Table 8. Compiler Commands
Command
Description
cmp start
Starts the Compiler for the active Compiler setting.
cmp stop
Stops the Compiler.
cmp is_running
Checks the status of the Compiler and returns the value of
1 if the Compiler is running and 0 if the Compiler is
stopped.
Similar to the Compiler settings commands, you can also combine the
commands to perform additional steps. For example, the code in Figure 14
checks the status of the Compiler and stops the Compiler if it is still
running.
Figure 14. Compiler Status Code
# Check if the Compiler is running. If it is running,
# stop it.
if {[cmp is_running] == 1} {
# Stop the Compiler
cmp stop
}
The code in Figure 15 prevents further script execution during
compilation. When compilation finishes, the Tcl interpreter exits this loop.
The code uses the is_command_line_mode command to determine
whether the script is running at the command prompt or in the
Tcl Console window. When running the script on the Tcl Console
window, the Quartus II GUI must be updated from time-to-time; hence,
adding a wait loop to refresh the GUI. However, in command-line mode,
the Quartus II software does not need to refresh the GUI. Therefore, you
do not need to use the wait loop because it may prolong the compilation
time in command-line mode.
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Figure 15. Sample While Loop Code
# Flush messages after a certain time while the Compiler is still running.
# Check if the Compiler is still running.
while {[cmp is_running]} {
# If the Compiler is still running, determine whether the script is
# running in command-line mode or in the Tcl Console window.
if {![is_command_line_mode]} {
# If the script is running in the Tcl Console window, create a
# delay so that the Quartus II software can update its GUI.
# Create a dummy flag x and set it to 0.
set x 0;
# After 1, set x to 1.
after 1000 {set x 1};
# Wait until x changes its value and then proceed.
vwait x;
}
# Flush Quartus II compilation messages
FlushEventQueue;
}
To pipe Quartus II messages to stdout or to a file handle, include the
code in Figure 16 in a library.
Figure 16. Example Code to Override the Default Procedure
# Example code to override the default procedure for displaying the
# Quartus II compilation messages. This procedure must be called
# postMessage.
proc postMessage {report msg} {
# Override the postMessage procedure in quartus/bin/ccl_msg.tcl.
split $msg ""
set line " Q> [lindex $msg 0] : [lindex $msg 3] "
put stdout $line
}; # ______________postMessage______________#
# Example code to override the default procedure for displaying the
# Quartus II internal error messages. This procedure must be called
# InternalError.
proc InternalError {report text} {
# Override the InternalError procedure in quartus/bin/ccl_msg.tcl.
puts stdout "Q>report (IE) = $report"
puts stdout "Q>msg (OE) = $text"
}; # ______________InternalError______________#
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A full netlist extraction and a full compilation are the two different kinds
of compilation. To perform a full netlist extraction, use the commands
shown in Figure 17.
Figure 17. Netlist Extraction Code
# Perform netlist extraction only.
cmp add_assignment "" "" "" "COMPILATION_LEVEL" "SYNTHESIS_ONLY";
To perform a full compilation, use the commands in Figure 18.
Figure 18. Full Compilation Code
# Perform a full compilation.
cmp add_assignment "" "" "" "COMPILATION_LEVEL" "FULL";
Figure 19 shows a simple procedure to start compilation and print out messages.
Figure 19. Example Procedure to Control the Compiler
# Start the Compiler and store the return value of the command cmp start in a
# variable called status. If the Compiler starts, cmp start will return 1;
# otherwise it will return 0.
set status [cmp start]
if {$status == 1} {
# If cmp start returns 1, display the message "Compiling project ..."
puts "Compiling project ...\n"
} else {
# If cmp start returns 0, display the message "Compiler failed."
puts "Compiler failed.\n"
}
When you are running multiple compilations using a Tcl script, a window
will be displayed at the end of each compilation stating “Full Compilation
was Successful.” The script will not proceed unless you click OK on the
displayed window, which may be cumbersome when you want to
perform batch compilations. To avoid this delay, use disable_msg_box
to prevent the window from popping up at the end of compilation. You
can use the procedure in Figure 20 to compile or extract netlists with or
without suppressing the end compilation window.
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Figure 20. Example Procedure to Compile Current Compiler Settings
# An example procedure to compile the current Compiler settings. The
# arguments to this procedure are type and suppress. The argument type
# defines whether to perform a netlist extraction only (EXTRACTION) or to
# perform a full compilation (COMPILE), while the argument suppress
# indicates whether the end-of-compilation message box is disabled (YES)
# or enabled (NO).
proc do { {type "compile"} {suppress "yes"}} {
# Set the type variable based on the user input. The user can either
# input the type variable using lower case letters, uppercase letters,
# or combination of both as the script will convert the arguments to all
# upper case letters with the string toupper command.
set type [string toupper $type]
# Set the suppress variable based on the user input.
set suppress [string toupper $suppress]
# If the type variable is EXTRACTION, perform a netlist extraction only.
if {$type == "EXTRACTION"} {
cmp add_assignment "" "" "" COMPILATION_LEVEL SYNTHESIS_ONLY
}
# If the type variable is COMPILE, perform a full compilation.
elseif {$type == "COMPILE"} {
cmp add_assignment "" "" "" COMPILATION_LEVEL FULL
} else {
# If the type variable is neither EXTRACTION nor COMPILE, display an
# error message and exit the script.
puts "Error: Variable type must be set to \"COMPILE\" or
\"EXTRACTION\" but was $type.";
return "Error: See System tab for details.";
}
puts "Performing $type ......."
# If the suppress variable is set to yes, disable the end compilation
# window.
if {$suppress == "YES"} {
disable_msg_box ;
}
# Enable the end compilation window.
elseif {$suppress == "NO"} {
enable_msg_box
}
Code Continued on Next Page...
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# Start the Compiler.
cmp start compile
# Flush messages after a certain time while the Compiler is still
# running. Check if the Compiler is still running.
while {[cmp is_running]} {
# If the Compiler is still running, determine whether the script is
# running at the
# command prompt or the Tcl Console window.
if {![is_command_line_mode]} {
# If the script is running on the Tcl Console window, create a
# delay so that the Quartus II
# software can update its GUI. Create a dummy flag x and set it
# to 0.
set x 0;
# After 1, set x to 1.
after 1000 {set x 1};
# Wait until x changes its value and then proceed.
vwait x;
}
# Flush Quartus II compilation messages
FlushEventQueue;
}
}
To invoke the procedure in Figure 20 to perform a full design compilation
with the message box disabled, use the syntax in Figure 21.
Figure 21. Full Design Compilation With Message Box Disabled
# Call procedure do with the type argument equal to compile and the
# suppress argument equal to yes.
do compile yes
Common
Compiler
Settings
Altera Corporation
This section provides examples on how to create project information
assignments, make third-party tool assignments, make device
assignments, make pin and I/O assignments, and make timing
requirements. Most of the commands used in this section will be using the
project add_assignment command.
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Project Information Assignments
You may skip this section if you are not using any user library for your
project. The user library assignments are placed in the PROJECT_INFO
section of the PSF.
To add multiple user libraries, separate the path to the libraries with a
semicolon (;), as shown in Figure 22.
Figure 22. Add Multiple User Libraries
# Add user libraries which are located in d:\qdesigns\prim and
# d:\qdesigns\bb to the project.
project add_assignment "" "filtref" "" "" "USER_LIBRARIES"
"d:/qdesigns/bb;d:/qdesigns/prim"
Third-Party Tool Assignments
This section describes the assignments that you need to add when using a
third-party tool in your design. All third-party tool assignments, except
for naming the third-party tools used, are placed in the
EDA_TOOL_SETTINGS section of the PSF. The names of the tools are
placed in the THIRD_PARTY_EDA_TOOLS section of the PSF. This section
has four different subsections reflecting the different design stages of the
project. Depending on the design stage, you must use a different section
identifier for the Tcl command. Table 9 lists the section identifier for each
of the design stages.
Table 9. EDA_TOOL_SETTINGS Subsection Identifier in the PSF
Design Stage
Synthesis
eda_design_synthesis
Simulation
eda_simulation
Timing analysis
eda_timing_analysis
Board design tool
eda_board_design
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Section Identifier
For more information on the variables used in this section, search
for the variable name in the Quartus II Help Index.
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Synthesis
Figure 23 is an example of how to set the LeonardoSpectrumTM tool as the
third-party synthesis tool, and shows the optional settings to invoke the
LeonardoSpectrum tool automatically through NativeLink® integration.
NativeLink integration enables you to launch supported EDA tools from
within the Quartus II software, or to launch the Quartus II software from
within the supported EDA tools. It also provides the ability to pass
information via scripts between the Quartus II software and supported
EDA tools, and includes additional enhancements that improve the flow
between supported EDA tools and the Quartus II software. To use
NativeLink integration, you must have the path to the EDA tool’s
executable files.
Figure 23. Setting the LeonardoSpectrum Software as the Third-Party Synthesis Tool
# The next two lines of code are required when you are using a third-party
# synthesis tool for your design. Specify the LeonardoSpectrum software as
# the third-party synthesis tool for the project.
project add_assignment "" "fir_filter" "" ""
"EDA_DESIGN_ENTRY_SYNTHESIS_TOOL" "Leonardo Spectrum"
# Specify the library mapping file for the LeonardoSpectrum software.
project add_assignment "" "eda_design_synthesis" "" "" "EDA_LMF_FILE"
"exemplar.lmf"
# Optional command to allow the Quartus II software to display the Library
# Mapping File (.lmf) mapping messages.
project add_assignment "" "eda_design_synthesis" "" ""
"EDA_SHOW_LMF_MAPPING_MESSAGES" "on"
# Optional command that you can use to automatically run the
# LeonardoSpectrum software using NativeLink integration. With this
# variable set, the Quartus II software invokes the LeonardoSpectrum
# software to compile the design when you click the Compile button. You
# must have the path to the LeonardoSpectrum software executable in your
# system path variable.
project add_assignment "" "eda_design_synthesis" "" ""
"EDA_RUN_TOOL_AUTOMATICALLY" "on"
When using a third-party synthesis tool, you only need to specify the
synthesis tool name and the LMF name. Depending on the third-party
synthesis tool chosen, a different LMF will be used. The LMF is located at
<quartus_install_dir>\lmf.
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Table 10 contains a description of the variables for the synthesis tool
settings. Only the first two entries are required; the rest of the entries are
optional settings and the Quartus II software can automatically assign
values to these variables when compiling the design.
Table 10. Third-Party Synthesis Tool Variable Description
Variable
Description
EDA_DESIGN_ENTRY_SYNTHESIS_TOOL
Specifies the name of the EDA design entry tool, or the EDA
synthesis tool used to generate a design file.
EDA_LMF_FILE
Specifies the default LMF for the current compilation.
EDA_SHOW_LMF_MAPPING_MESSAGES
Determines whether to display messages describing the mappings
used in the LMF.
EDA_RUN_TOOL_AUTOMATICALLY
Runs the third-party EDA tool automatically from the Quartus II
software when a design is compiled using NativeLink integration.
EDA_INPUT_DATA_FORMAT
Specifies the format of the input data read from other EDA design
entry or synthesis tools. The value is either Verilog HDL or VHDL.
For example:
project add_assignment ""
"eda_design_synthesis" "" ""
"EDA_INPUT_DATA_FORMAT" "Verilog HDL";
EDA_OUTPUT_DATA_FORMAT
Specifies the format of the output data generated for use with other
EDA simulation or timing analysis tools. In general, the value is
EDIF. If you are using the Synplicity® tool and targeting one of
Altera’s FPGAs (excluding the FLEX® and ACEX® device families),
the value should be Verilog HDL. For example:
project add_assignment ""
"eda_design_synthesis" "" ""
"EDA_OUTPUT_DATA_FORMAT" "EDIF";
EDA_INPUT_GND_NAME
Specifies the global low signal used in the files generated by the
EDA design entry or synthesis tool. The default value is GND and
usually you do not need to change this value. For example:
project add_assignment ""
"eda_design_synthesis" "" ""
"EDA_INPUT_GND_NAME" "GND";
EDA_INPUT_VCC_NAME
Specifies the global high signal used in the files generated by the
EDA design entry or synthesis tool. The default value is VCC and
usually you do not need to change this value.
project add_assignment ""
"eda_design_synthesis" "" ""
"EDA_INPUT_VCC_NAME" "VCC";
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For a list of the current variables, refer to the Quartus II On-Line
Help.
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Simulation
Figure 24 shows an example of how to specify the ModelSim® tool (VHDL
output from the Quartus II software) as the third-party simulation tool,
and how to invoke the tool automatically through NativeLink integration.
Figure 24. Specifying ModelSim VHDL Output as the Third-Party Simulation Tool
# Specify the ModelSim OEM version as the third-party simulation tool for
# the project. In addition, the code also specifies that the Quartus II
# software should create a VHDL Output File (.vho) file in the
# <project_dir>\simulation\modelsim.
# directory. This code is only required when you want to perform VHDL
# timing simulation.
project add_assignment "" "fir_filter" "" "" "EDA_SIMULATION_TOOL"
"ModelSim (VHDL output from Quartus II)";
# When you choose to have a Verilog Output File (.vo) netlist file for
# simulation, you must specify the simulation time scale. The default value
# is 1 picosecond (ps). This code is only required for Verilog timing
# simulation.
project add_assignment "" "eda_simulation" "" "" "EDA_TIME_SCALE" "1 ps";
# Optional code that you can use to run the ModelSim OEM version
# automatically using NativeLink integration. You must have the path to the
# ModelSim OEM executable in your system path variable.
project add_assignment "" "eda_simulation" "" ""
"EDA_RUN_TOOL_AUTOMATICALLY" "on";
# The Quartus II software allows you to perform power estimation for your
# design based on your simulation input. When you simulate your design using
# the ModelSim tool, you can create a power input file by adding the code
# below. For more information, refer to the Quartus II On-Line Help under
# Power Input File or Power Estimation.
project add_assignment "" "eda_simulation" "" ""
"EDA_GENERATE_POWER_INPUT_FILE" "on";
# Optional code to include Configuration Declaration in the VHO file,
# which only applies to VHDL timing simulation. On is the default value.
project add_assignment "" "eda_simulation" "" ""
"EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION" "on";
# Optional code to map illegal characters in the Quartus II hierarchical
# node names to legal VHDL and Verilog HDL. On is the default value.
project add_assignment "" "eda_simulation" "" ""
"EDA_MAP_ILLEGAL_CHARACTERS" "on";
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# Optional code to shorten the hierarchy path names. Off is the default
# value.
project add_assignment "" "eda_simulation" "" ""
"EDA_TRUNCATE_LONG_HIERARCHY_PATHS" "off";
# Optional code to flatten all the buses in your design. Off is the default
# value, but you must turn this value on if your third-party Simulator does
# not support buses.
project add_assignment "" "eda_simulation" "" "" "EDA_FLATTEN_BUSES" "off";
# Optional code to create the Excalibur stripe in your design as a single
# entity. Off is the default value.
project add_assignment "" "eda_simulation" "" ""
"EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE" "off";
When you choose the ModelSim tool as the Simulator, you can also choose
either testbench mode or command/macro mode. The Quartus II
testbench file must have a VHDL Testbench File (.vht) or Verilog HDL
Testbench File (.vt) extension. You must create a .do file if you want to use
the command/macro mode. Figure 25 shows an example of both
testbench mode and command/macro mode. You can only use one mode
for any given project.
Figure 25. Creating Both Testbench & Command/Macro Modes
# TESTBENCH MODE
# Enable the testbench mode for the open project.
project add_assignment "" "eda_simulation" "" ""
"EDA_TEST_BENCH_ENABLE_STATUS" "TEST_BENCH_MODE";
# Set the top-level module for simulation.
project add_assignment "" "eda_simulation" "" ""
"EDA_TEST_BENCH_ENTITY_MODULE_NAME" "fir_filter";
# Specify the testbench file name. The code below assumes that the file is
# in the same directory as the project.
project add_assignment "" "eda_simulation" "" ""
"EDA_TEST_BENCH_FILE_NAME" "fir_filter.vt";
# Specify the instantiation of the top-level module in the testbench.
project add_assignment "" "eda_simulation" "" ""
"EDA_TEST_BENCH_DESIGN_INSTANCE_NAME" "u1";
# Specify the simulation time.
project add_assignment "" "eda_simulation" "" "" "EDA_TEST_BENCH_RUN_FOR"
"100ns";
# COMMAND/MACRO MODE
# Enable Command/Macro mode to simulate the open project.
project add_assignment "" "eda_simulation" "" ""
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"EDA_TEST_BENCH_ENABLE_STATUS" "COMMAND_MACRO_MODE";
# Specify the location of the .do file that will be used for simulation.
project add_assignment "" "eda_simulation" "" ""
"EDA_SIMULATION_RUN_SCRIPT" "d:\quartus\tutorial\run.do";
Table 11 shows the variables for the advanced simulation tool setting.
Table 11. Third-Party Simulation Tool Advanced Variable Descriptions
Variable
Description
EDA_TEST_BENCH_ENABLE_STATUS
Enables the advanced options (VHDL or Verilog HDL
simulation options for testbench or command/macro
mode). You can only enable this variable when you
choose to use the ModelSim tool.
EDA_TEST_BENCH_ENTITY_MODULE_NAME
Specifies the top-level design entity in the testbench
file.
EDA_TEST_BENCH_FILE_NAME
Specifies the testbench file name for testbench mode.
File type can be a VHT file, VT file, or another design
file type.
EDA_TEST_BENCH_DESIGN_INSTANCE_NAME
Specifies the instance name of the design entity in the
testbench file.
EDA_TEST_BENCH_RUN_FOR
Specifies the simulation run time for a third-party
simulation in testbench mode.
EDA_TIME_SCALE
Specifies the time unit used to represent timing delays
in each VO file. The value for the EDA_TIME_SCALE
option may be between 0.001 ns and 10 ns, and should
be a multiple of 10.
EDA_SIMULATION_RUN_SCRIPT
Specifies the script file for running a third-party
simulation in command/macro mode.
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Table 12 shows the description of variables specific to simulation, timing
analysis, and board design tools.
Table 12. Third-Party Variable Descriptions Specific to Simulation, Timing & Analysis
Variable
Description
EDA_SIMULATION_TOOL
Specifies the name of the EDA simulation tool.
EDA_TIMING_ANALYSIS_TOOL
Specifies the name of the EDA timing analysis tool.
EDA_BOARD_DESIGN_TOOL
Specifies the name of the EDA board design tool.
EDA_EXCALIBUR_ATOMS_AS_SINGLE_STRIPE
Writes the ExcaliburTM stripe as a single module or
entity.
EDA_FLATTEN_BUSES
Flattens all buses when creating the netlist output
file. Turn on this option if your third-party EDA
environment does not support buses.
EDA_GENERATE_POWER_INPUT_FILE
Generates a Power Input File (.pwf) to perform
power analysis in the Quartus II software when
using third-party simulation tools.
EDA_MAP_ILLEGAL_CHARACTERS
Maps the vertical bar (|), tilde (~), and colon (:)
characters in the Quartus II software hierarchical
node names to the legal Verilog HDL characters z,
x, and underscore (_), respectively, in VO files.
Turning on this option also maps other illegal nonalphanumeric characters, including brackets [],
parentheses, (), angle brackets <>, and braces {} to
underscore (_).
EDA_OUTPUT_DATA_FORMAT
Specifies the format of the output data generated for
use with other EDA simulation or timing analysis
tools.
EDA_TRUNCATE_LONG_HIERARCHY_PATHS
Truncates long hierarchical node names.
EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION
Includes a configuration declaration in each VHO
file.
EDA_USE_IBIS_RLC_TYPE
Specifies the type of RLC values used in the IBIS
output file (.ibs). You can choose minimum, typical,
or maximum.
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Timing Analysis
Similar to the third-party simulation settings, you can specify the timing
analysis timescale when using Verilog HDL output, and specify whether
you want to add the configuration VHDL when using VHDL output. In
addition, you can also specify whether you want to map illegal characters,
shorten long hierarchy paths, flatten buses, or include the Excalibur stripe
in your design as a single entity. Figure 26 shows the code to set
PrimeTime (VHDL output from the Quartus II software) as your thirdparty timing analyzer.
Figure 26. Code to Set PrimeTime as the Third-Party Timing Analysis Tool
# Specify PrimeTime as the third-party timing analysis tool for the open
# project and specify the Quartus II software to create a VHDL netlist
# output. The Quartus II software places the netlist in the
# <project_dir>\timing\primetime directory.
project add_assignment "" "fir_filter" "" "" "EDA_TIMING_ANALYSIS_TOOL"
"PrimeTime (VHDL output from Quartus II)";
# Optional code that you can use to automatically run PrimeTime
# using NativeLink integration. You must have the path to the PrimeTime
# executable in your system path variable.
project add_assignment "" "eda_timing_analysis" "" ""
"EDA_RUN_TOOL_AUTOMATICALLY" "on";
Board Design
You can specify the third-party board design tool name and IBIS RLC
values that you want to use. You can also use the generated IBS file in your
signal integrity verification tools. See Figure 27.
Figure 27. Specifying Signal Integrity as the Third-Party Board Design Tool
# Specify Signal Integrity (IBIS) as the third-party board design tool.
# The Quartus II software will then create an IBS file for the design at
# the <project_dir>\board\ibis directory.
project add_assignment "" "fir_filter" "" "" "EDA_BOARD_DESIGN_TOOL"
"Signal Integrity (IBIS)";
# Specify the Quartus II software to use typical IBIS RLC values.
project add_assignment "" "eda_board_design" "" "" "EDA_USE_IBIS_RLC_TYPE"
"TYPICAL";
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Device, Pin & I/O Assignments
To add device, pin, or I/O assignments to a project, use the
cmp add_assignment command. These assignments will be written
into the CSF. You can also use cmp start_batch coupled with
cmp end_batch around a sequence of cmp add_assignment
commands to speed up assignment processing. Table 13 shows the
commands to make assignments in a project’s CSF.
Table 13. Making Assignments in a CSF
Command
Description
cmp add_assignment <section identifier>
<source> <target> <variable> <value>
Adds an assignment to the current Compiler settings.
cmp remove_assignment
<section identifier> <source> <target>
<variable> <value>
Removes an assignment to the current Compiler settings.
cmp start_batch <entity>
Used when many assignment commands
(e.g., cmp add_assignment) are used in a row. Add this
command before the set of commands. Add cmp end_batch
after the set of commands.
cmp end_batch <entity>
Used when many assignment commands (e.g.,
cmp add_assignment) are used in a row. Add this command
after the set of commands.
The code in Figure 28 shows how to add an EP20K100QC208-1device
using Tcl commands.
Figure 28. Adding a Device Using Tcl Commands
# Make the device family and assignment to the project.
cmp add_assignment "" "" "" "FAMILY" "APEX20K"
cmp add_assignment "filtref" "" "" "DEVICE" "EP20K100QC208-1"
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Figure 29 shows how to add a pin assignment.
Figure 29. Syntax for Assigning Pin Locations to the Project
cmp add_assignment "<chip_name>" "" "<signal_name>" "LOCATION"
"Pin_<location>";
where:
<chip_name> = the name of the chip, which is typically the project name.
<signal_name> = the name of the I/O signal.
<location> = the valid I/O pin number to be added.
When assigning part of the bus, use the backslash (\) before the open and
close square brackets ([ ]) so that the <signal_name> becomes
<signal_name>\[<bit_number>\]. Figure 30 shows a code example for
assigning pins to the filtref tutorial design.
Figure 30. Assigning Pins to the filtref Tutorial Design
cmp add_assignment "filtref" "" "clk" "LOCATION" "Pin_131";
cmp add_assignment "filtref" "" "d\[0\]" "LOCATION" "Pin_4";
cmp add_assignment "filtref" "" "d\[1\]" "LOCATION" "Pin_151";
Figure 31 shows how to set the I/O standard for I/O ports.
Figure 31. Syntax for Assigning the I/O Standard
cmp add_assignment "<chip_name>" "" "<signal_name>" "IO_STANDARD" "<standard>";
Figure 32 shows an example of creating a VREF pin for a GTL I/O standard (supported by the
StratixTM device family only).
Figure 32. Example on Reserving Pins & I/O Standards
# Reserve a pin called my_vref as a VREF pin.
cmp add_assignment "pin_test" "" "my_vref" "RESERVE_PIN" "AS VREF";
# Specify the location for my_vref.
cmp add_assignment "pin_test" "" "my_vref" "LOCATION" "Pin_C27";
# Specify the I/O standard for my_vref.
cmp add_assignment "pin_test" "" "my_vref" "IO_STANDARD" "GTL";
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Table 14 lists the available I/O assignments for a particular pin or register
going to or from a pin. For information on each variable and whether the
variable is available for a particular device, search for the variable in the
Quartus II On-Line Help.
Table 14. Most Commonly Used I/O Assignment (Part 1 of 2)
Variable
Value
CURRENT_STRENGTH
Default Strength | Min Strength | Max Strength | Strength 2 mA | Strength
4 mA | Strength 8 mA | Strength 12 mA | Strength 16 mA | Strength 24 mA
ENABLE_BUS_HOLD_CIRCUITRY
On | Off
For example:
project add_assignment " filtref " "" ""
"test_pin" "ENABLE_BUS_HOLD_CIRCUITRY" "On";
DQS_FREQUENCY
<string>
For example:
project add_assignment "filtref" "" ""
"my_dqs" "DQS_FREQUENCY" "100 MHz";
DQS_SHIFT
Phase of 72 degrees | Phase of 90 degrees
For example:
project add_assignment " filtref " "" ""
"my_dqs" "DQS_SHIFT" "Phase of 90 degrees";
FAST_INPUT_REGISTER
On | Off
FAST_OUTPUT_REGISTER
On | Off
FAST_OUTPUT_ENABLE_REGISTER On | Off
GLOBAL_SIGNAL (1)
On | Off
For example:
project add_assignment " filtref " "" ""
"my_sig" "GLOBAL_SIGNAL" "On";
PCI_IO
On | Off
PLL_COMPENSATE
On | Off
POWER_UP_HIGH
On | Off
RESERVE_ALL_UNUSED_PINS
As input tri-stated | As output driving ground | As output driving an
unspecified signal
RESERVE_PIN
As input tri-stated | As output driving ground | As output driving an
unspecified signal | As VREF | As SignalProbe output
SLOW_SLEW_RATE
On | Off
TERMINATION
Series | Parallel | Differential
For example:
project add_assignment " filtref " "" ""
"out_pin" "TERMINATION" "Series";
WEAK_PULL_UP_RESISTOR
On | Off
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Table 14. Most Commonly Used I/O Assignment (Part 2 of 2)
Variable
Value
STRATIX_DEVICE_IO_STANDARD <string>
MERCURY_DEVICE_IO_STANDARD For example:
APEXII_DEVICE_IO_STANDARD
cmp add_assignment "filtref" "" ""
APEX20KE_DEVICE_IO_STANDARD
"STRATIX_DEVICE_IO_STANDARD" "LVCMOS";
APEX20K_DEVICE_IO_STANDARD
MAX7000_DEVICE_IO_STANDARD
FLEX6K_DEVICE_IO_STANDARD
Note to Table 14:
(1)
The GLOBAL_SIGNAL variable is not only for pins; you can also assign the GLOBAL_SIGNAL variable to an internal
node in the design.
To create an assignment from the list in Table 14, use the following syntax:
project add_assignment "<entity_name>" "" ""
"<pin_name>" "<variable>" "<value>";
Optional
Compiler
Settings
This section describes other Compiler settings that you may want to
change in the course of creating your design. Most of the commands use
the project add_assignment command. This section covers
configuration, synthesis and fitting, and routing assignments.
HDL Settings
When using Quartus II native synthesis to synthesize your design, you
only need to set the HDL settings (see Figure 33).
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Figure 33. HDL Settings
# HDL settings for VHDL designs
# Specify the VHDL version for the design. The value can be either
# VHDL87 or VHDL93.
project add_assignment "" "" "" "" "VHDL_INPUT_VERSION" "VHDL87";
# Use the maxplus2.lmf file as the library mapping file. You
# only need to use this file when using VHDL primitives from the
# maxplus2 package.
project add_assignment "" "" "" "" "VHDL_LMF_FILE" "maxplus2.lmf";
project add_assignment "" "" "" ""
"VHDL_SHOW_LMF_MAPPING_MESSAGES" "OFF";
# Specify the VHDL user library for the project.
project add_assignment "" "" "" "my_lib" "VHDL_INPUT_LIBRARY"
"d:/vhdl/lib";
# HDL settings for Verilog HDL designs
# Use the maxplus2.lmf file as the library mapping file. You only need to
# use this file when using Verilog HDL primitives from the maxplus2
# package.
project add_assignment "" "" "" "" "VERILOG_LMF_FILE" "maxplus2.lmf";
# Turn off the LMF mapping messages.
project add_assignment "" "" "" "" "VERILOG_SHOW_LMF_MAPPING_MESSAGES"
"OFF";
Configuration Settings
Some of the configuration settings in the Quartus II software only affects
one particular device family, while the other settings apply to all Altera
devices. To set the assignment, use the following syntax:
cmp add_assignment "<entity_name>" "" "" "<variable>"
"<value>";
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Table 15 shows the configuration settings that you may need to set for a
particular device family.
Table 15. Configuration Settings for Altera Devices (Part 1 of 2)
Device Family
Stratix
Setting
STRATIX_CONFIGURATION_SCHEME
For example:
cmp add_assignment "filtref" "" ""
"STRATIX_CONFIGURATION_SCHEME" "Passive Serial";
STRATIX_CONFIGURATION_DEVICE
For example:
cmp add_assignment "filtref" "" ""
"STRATIX_CONFIGURATION_DEVICE" "EPC16";
STRATIX_JTAG_USER_CODE
For example:
cmp add_assignment "filtref" "" ""
"STRATIX_JTAG_USER_CODE" "FFFFFFFF";
STRATIX_CONFIG_DEVICE_JTAG_USER_CODE
For example:
cmp add_assignment "filtref" "" ""
"STRATIX_CONFIG_DEVICE_JTAG_USER_CODE" "FFFFFFFF";
STRATIX_CRC_ERROR_CHECKING
For example:
cmp add_assignment "filtref" "" ""
"STRATIX_CRC_ERROR_CHECKING" "On";
ERROR_CHECK_FREQUENCY_DIVISOR
For example:
cmp add_assignment "filtref" "" ""
"ERROR_CHECK_FREQUENCY_DIVISOR" "1";
STRATIX_UPDATE_MODE
For example:
cmp add_assignment "filtref" "" ""
"STRATIX_UPDATE_MODE" "Standard";
APEXTM 20K
APEX20K_CONFIGURATION_SCHEME
APEX20K_CONFIGURATION_DEVICE
APEX20K_JTAG_USER_CODE
APEX20K_CONFIG_DEVICE_JTAG_USER_CODE
APEX II
APEX_II_CONFIGURATION_SCHEME
Excalibur
EXCALIBUR_CONFIGURATION_SCHEME
EXCALIBUR_CONFIGURATION_DEVICE
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Table 15. Configuration Settings for Altera Devices (Part 2 of 2)
Device Family
FLEX 6000
Setting
FLEX6K_CONFIGURATION_SCHEME
FLEX6K_CONFIGURATION_DEVICE
FLEX6K_JTAG_USER_CODE
FLEX6K_CONFIG_DEVICE_JTAG_USER_CODE
FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE
For example:
cmp add_assignment "filtref" "" ""
"FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE" "On";
FLEX 10K
FLEX10K_CONFIGURATION_SCHEME
FLEX10K_CONFIGURATION_DEVICE
FLEX10K_JTAG_USER_CODE
FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE
FLEX10K_ENABLE_LOCK_OUTPUT
FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE
MercuryTM
MERCURY_CONFIGURATION_SCHEME
MERCURY_CONFIGURATION_DEVICE
MERCURY_JTAG_USER_CODE
MERCURY_CONFIG_DEVICE_JTAG_USER_CODE
MAX® 7000
MAX7000_ENABLE_JTAG_BST_SUPPORT
MAX7000_JTAG_USER_CODE
SECURITY_BIT
For example:
cmp add_assignment "filtref" "" "" "SECURITY_BIT" "On";
ENABLE_JTAG_BST_SUPPORT
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Table 16 shows the configurations settings that are available for all device
families.
Table 16. Configuration Settings for All Device Families (Part 1 of 2)
Variable
Generating other
programming files
Value
GENERATE_RBF_FILE
GENERATE_TTF_FILE
GENERATE_HEX_FILE
For example:
cmp add_assignment "filtref" "" ""
"GENERATE_HEX_FILE" "On";
HEXOUT_FILE_COUNT_DIRECTION
HEXOUT_FILE_START_ADDRESS
Enabling or reserving pins
after configuration
RELEASE_CLEARS_BEFORE_TRI_STATES
BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE
For example:
cmp add_assignment "filtref" "" ""
"BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE" "On";
ENABLE_DEVICE_WIDE_OE
ENABLE_DEVICE_WIDE_RESET
ENABLE_VREFA_PIN
For example:
cmp add_assignment "filtref" "" ""
"ENABLE_VREFA_PIN" "On";
ENABLE_VREFB_PIN
ENABLE_INIT_DONE_OUTPUT
RESERVE_NCEO_AFTER_CONFIGURATION
RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION
RESERVE_RDYNBUSY_AFTER_CONFIGURATION
RESERVE_DATA0_AFTER_CONFIGURATION
RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION
For example:
cmp add_assignment "filtref" "" ""
"RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION" "On";
RESERVE_RUNLU_AFTER_CONFIGURATION
DISABLE_CONF_DONE_AND_NSTATUS_PULLUPS_ON_CONFIG_DEVICE
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Table 16. Configuration Settings for All Device Families (Part 2 of 2)
Variable
Other configuration settings
Value
AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE
For example:
cmp add_assignment "filtref" "" ""
"AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE" "On";
AUTO_RESTART_CONFIGURATION
For example:
cmp add_assignment "filtref" "" ""
"AUTO_RESTART_CONFIGURATION" "On";
USE_CONFIGURATION_DEVICE
USE_CHECKSUM_AS_USERCODE
For example:
cmp add_assignment "filtref" "" ""
"USE_CHECKSUM_AS_USERCODE" "On";
USER_START_UP_CLOCK
EPROM_USE_CHECKSUM_AS_USERCODE
Synthesis & Fitting Settings
You can apply these settings to the whole project or to specific entities
and/or nodes. Use the following syntax to add the settings, and leave the
destination argument blank when specifying the setting for the entire
project:
project add_assignment "" "" "" "<destination>" "<variable>"
"<value>";
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Table 17 lists the most commonly used settings for synthesis and fitting.
Table 17. Most Commonly Used Synthesis & Fitting Settings (Part 1 of 2)
Group Setting Description
Setting
Automatic settingsthe Quartus II software
automatically implements these variables when
they are set to “on” if the software determines that
it is possible or necessary to do so.
AUTO_CARRY_CHAINS
AUTO_CASCADE_CHAINS
AUTO_GLOBAL_CLOCK
AUTO_GLOBAL_MEMORY_CONTROLS
AUTO_GLOBAL_OE
AUTO_GLOBAL_REGISTER_CONTROLS
AUTO_FAST_INPUT_REGISTERS
AUTO_LCELL_INSERTION
AUTO_OPEN_DRAIN_PINS
AUTO_FAST_OUTPUT_ENABLE_REGISTERS
AUTO_FAST_OUTPUT_REGISTERS
AUTO_PARALLEL_EXPANDERS
AUTO_IMPLEMENT_IN_ROM
AUTO_PACKED_REGISTERS
AUTO_PACKED_REGISTERS_LAST_RESORT
AUTO_PACKED_REGISTERS_STRATIX
ALLOW_XOR_GATE_USAGE
NOT_GATE_PUSH_BACK
AUTO_TURBO_BIT
For example:
# Turns on turbo bit for state_m.
project add_assignment state_m "" "" ""
"TURBO_BIT" "ON"
Ignore buffer settingswhen the variables are set
to “on,” the Quartus II software ignores the
appropriate buffers assigned for any nodes in the
design.
IGNORE_LCELL_BUFFERS
IGNORE_ROW_GLOBAL_BUFFERS
IGNORE_SOFT_BUFFERS
IGNORE_CARRY_BUFFERS
IGNORE_CASCADE_BUFFERS
IGNORE_GLOBAL_BUFFERS
For example:
project add_assignment "" "" "" ""
"IGNORE_GLOBAL_BUFFERS" "OFF";
Remove duplicate logicall duplicates are
removed when these variables are set to “on.”
REMOVE_DUPLICATE_REGISTERS
REMOVE_REDUNDANT_LOGIC_CELLS
REMOVE_DUPLICATE_LOGIC
For example:
project add_assignment "filtref" "" ""
"sig_dup0" "REMOVE_DUPLICATE_LOGIC" "On";
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Table 17. Most Commonly Used Synthesis & Fitting Settings (Part 2 of 2)
Group Setting Description
Setting
Limit settingssets a limit to a chain length.
CASCADE_CHAIN_LENGTH
PARALLEL_EXPANDER_CHAIN_LENGTH
CARRY_CHAIN_LENGTH
For example:
project add_assignment "" "" "" ""
"CARRY_CHAIN_LENGTH" "32";
State machine processingthis option is for
choosing the state machine style.
STATE_MACHINE_PROCESSING
For example:
project add_assignment "" "" "" ""
"STATE_MACHINE_PROCESSING" "One-Hot";
Technology mapperwhen implementing logic in TECHNOLOGY_MAPPER
the device, this option is for targeting look-up table For example:
(LUT), product-term, or ROM structures.
# Set up technology mapper for state_m to be
# product termproject add_assignment state_m
"" "" "" "TECHNOLOGY_MAPPER" "product_term"
Optimization techniquethis option is for choosing APEX20K_OPTIMIZATION_TECHNIQUE
whether to optimize for speed or for area.
MERCURY_OPTIMIZATION_TECHNIQUE
FLEX10K_OPTIMIZATION_TECHNIQUE
FLEX6K_OPTIMIZATION_TECHNIQUE
MAX7000_OPTIMIZATION_TECHNIQUE
STRATIX_OPTIMIZATION_TECHNIQUE
For example:
project add_assignment "" "" "" ""
"STRATIX_OPTIMIZATION_TECHNIQUE" "AREA";
Table 18 lists the variables that are available in the Compiler settings.
Table 18. Compiler Setting Variables (Part 1 of 2)
Group Setting Description
OPTIMIZE_TIMING
Setting
Turns on the timing driven compilation.
OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR When the I/O timing requirements are not met, enables the
_TIMING
Quartus II software to use registers in I/O cells.
FAST_FIT_COMPILATION
40
Decreases compilation time by up to 50%. This option may
reduce fMAX for the design.
For example:
cmp add_assignment "" "" ""
"FAST_FIT_COMPILATION" "On";
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Table 18. Compiler Setting Variables (Part 2 of 2)
Group Setting Description
Setting
SPEED_DISK_USAGE_TRADEOFF
Chooses to use either full or smart recompilation.
For example:
# To enable smart recompilation
cmp add_assignment "" "" ""
"SPEED_DISK_USAGE_TRADEOFF" "Smart";
SAVE_DISK_SPACE
Preserves fewer node names when the option is turned on.
SIGNAL_PROBE_COMPILATION
Enables SignalProbeTM compilation. (1)
For example:
cmp add_assignment "" "" ""
"SIGNAL_PROBE_COMPILATION" "OFF";
SIGNAL_PROBE_AUTO_ASSIGN
Automatically assigns SignalProbe compilation. (1)
For example:
cmp add_assignment "" "" ""
"SIGNAL_PROBE_AUTO_ASSIGN" "2";
SIGNAL_PROBE_ROUTING
Routes the SignalProbe signals during a SignalProbe
compilation. (1)
For example:
cmp add_assignment "" "" ""
"SIGNAL_PROBE_ROUTING" "ALL_SIGNAL_PROBE";
Note to Table 18:
(1)
You must reserve the pins if you want to use specific pins, and perform a smart compilation before enabling the
SignalProbe feature. You also need to specify the third-party synthesis tool if you used one for your design.
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Routing Assignment
The Quartus II software allows you to choose certain routing assignments
to minimize timing paths on the design. Table 19 lists the variables to
choose a special routing path in certain device families.
Table 19. Routing Variables in the Quartus II Software Version 2.0
Variable
Devices Supported
LOCAL_ROUTING
APEX 20K, APEX 20KC, APEX 20KE, and APEX II devices
For example:
project add_assignment "filtref" "" "" "my_pin"
"APEX20K_LOCAL_ROUTING_SOURCE" "On";
CLOCK_ENABLE_ROUTING
ACEX 1K, APEX 20K, APEX II, Excalibur, and FLEX 10KE devices
For example:
project add_assignment "filtref" "" "" "my_ce"
"CLOCK_ENABLE_ROUTING" "Peripheral";
FASTROW_INTERCONNECT
ACEX 1K, APEX 20K, APEX II, Excalibur, and FLEX 10KE devices
For example:
project add_assignment "filtref" "" "" "my_pin"
"FASTROW_INTERCONNECT" "On";
OUTPUT_ENABLE_ROUTING
ACEX 1K, APEX 20K, APEX II, Excalibur, and FLEX 10KE devices
For example:
project add_assignment "filtref" "" "" "my_oe"
"OUTPUT_ENABLE_ROUTING" "Single-Pin";
Use the following syntax when using variables from Table 19:
project add_assignment "<entity>" "" "" "<signal>"
"<variable>" "<value>";
Timing
Requirement
Settings
42
Timing requirements are essential to any design. Timing requirements in
the Quartus II software can either be global or individual assignments.
This section covers clock settings, including multi-cycle and multidomain clock settings, I/O timing assignments, cut timing path settings,
programmable delay settings, and other possible timing requirement
settings for the Quartus II software version 2.0.
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Clock Settings
To create an fMAX assignment for a specific clock in the Quartus II
software, you must first create the clock settings and then assign each
clock signal to the appropriate clock setting. The following code is an
example of how to set a global fMAX of 50 MHz:
# Set the global fMAX for the design to 50 MHz.
project add_assignment "" "" "" ""
"FMAX_REQUIREMENT" "50.0 MHz";
When you have a multi-clock domain, you must make a clock setting for
each clock domain. A multi-clock domain sets up a clock configuration in
which two or more clocks exist within a single device.
The example code in Figure 34, which applies to the Quartus II tutorial
design, sets two clock settings (clocka and clockb) where clocka is an
absolute clock of 50 MHz, and clockb is a derived clock from clocka.
The frequency of clockb is half of clocka and is lagging clocka by
500 ps. Figure 34 also shows how to set a multi-cycle path assignment to
the project. A multi-cycle path intentionally requires more than a cycle to
become stable.
Figure 34. Setting Multi-Domain Timing Assignments
# Add the code below to speed up the assignment process for a sequence of
# project add_assignment commands.
project start_batch filtref;
# Create clocka settings (a 50 MHz absolute clock). The two lines of code
# below is the only code required for absolute clocks.
project add_assignment "" "clocka" "" "" "FMAX_REQUIREMENT" "50.0 MHz";
# Set duty cycle for clocka to be 50%.
project add_assignment "" "clockb" "" "" "DUTY_CYCLE" "50";
# Create clockb settings (a derived clock from clocka).
project add_assignment "" "clockb" "" "" "BASED_ON_CLOCK_SETTINGS"
"clocka";
# Set frequency of clockb to 25 MHz (half of clocka frequency) by setting
# the multiply variable to 1 and divide variable to 2.
project add_assignment "" "clockb" "" "" "MULTIPLY_BASE_CLOCK_PERIOD_BY"
"1";
project add_assignment "" "clockb" "" "" "DIVIDE_BASE_CLOCK_PERIOD_BY" "2";
# Specify that clockb is not inverted from clocka.
project add_assignment "" "clockb" "" "" "INVERT_BASE_CLOCK" "OFF";
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# Specify that clockb should lag clocka by 500 ps.
project add_assignment "" "clockb" "" "" "OFFSET_FROM_BASE_CLOCK" "500 ps";
# Specify that clockb should have a 50% duty cycle.
project add_assignment "" "clockb" "" "" "DUTY_CYCLE" "50";
# Set clk to include clocka settings and clkx2 to include clockb settings.
project add_assignment "filtref" "" "" "clk" "CLOCK_SETTINGS" "clocka";
project add_assignment "filtref" "" "" "clkx2" "CLOCK_SETTINGS" "clockb";
# Set a multi-cycle relationship of 2 between clk and clkx2.
project add_assignment "filtref" "" "clk" "clkx2" "MULTICYCLE" "2";
# Close the batch assignment indicating that there are no more project
# add_assignment commands.
project end_batch filtref;
To set multi-cycle assignments for a particular path between registers, use
the following syntax:
project add_assignment "<entity>" ""
"<register_source>" "<register_destination>"
"MULTICYCLE" "<value>";
For example, to specify a multi-cycle assignment of two between reg1
and reg2, use the following syntax:
project add_assignment "filtref" "" "reg1" "reg2"
"MULTICYCLE" "2";
When you only specify the destination register, a multi-cycle assignment
is applied on all paths leading to the register. In addition to
MULTICYCLE, you can also assign MULTICYCLE_HOLD,
DEFAULT_HOLD_MULTICYCLE, SOURCE_MULTICYCLE, and
SOURCE_MULTICYCLE_HOLD paths.
f
44
For more information on performing timing analysis, refer to AN 123:
Using Timing Analysis in the Quartus II Software.
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I/O Timing Requirements
The following code in Figure 35 sets global I/O timing requirements for
the entire project.
Figure 35. Setting Global I/O Timing Requirements
# Set the global tCO to 5 ns.
project add_assignment "" "" ""
# Set the global tH to 5 ns.
project add_assignment "" "" ""
# Set the global tPD to 5 ns.
project add_assignment "" "" ""
# Set the global tSU to 5 ns.
project add_assignment "" "" ""
"" "TCO_REQUIREMENT" "5ns";
"" "TH_REQUIREMENT" "5ns";
"" "TPD_REQUIREMENT" "5ns";
"" "TSU_REQUIREMENT" "5ns";
To specify a point-to-point timing requirement, use the following syntax:
project add_assignment "<entity_name>" " " "<source>"
"<destination>" "<tco/tsu/th/tpd_requirement>" "<value>";
When the source node is not specified but the destination node is
specified, the timing requirements apply to any path to or from the node.
Setting tSU on a pin sets a tSU requirement from that pin to all destinations,
while setting tCO on a pin sets a tCO requirement from all sources to the
pin. See Figure 36.
Figure 36. Timing Requirements
# Set tCO to 4.5 ns for all registers feeding pin yn_out.
project add_assignment "filtref" "" "" "yn_out" "TCO_REQUIREMENT" "4.5ns";
# Set tSU to 3 ns for all registers fed by pin newt.
project add_assignment "filtref" "" "" "newt" "TSU_REQUIREMENT" "3ns";
To compensate for delay on the board, you may add external delay settings to control the project
more accurately. To add an external input delay or an external output delay setting, use the syntax
shown in Figure 37.
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Figure 37. Setting the External Input & Output Delay
# Setting the external input and output delay.
project add_assignment "<project_name>" "" "" "<signal_name>"
"EXTERNAL_INPUT_DELAY" "<value in ns>";
project add_assignment "<project_name>" "" "" "<signal_name>"
"EXTERNAL_OUTPUT_DELAY" "<value in ns>";
Cut Timing Settings
You can set a cut timing path for specific nodes to exclude certain paths
from the timing analysis. Use the following syntax to apply a point-topoint cut timing path:
project add_assignment "<entity>" "" "<source>"
"<destination>" "CUT" "On";
This assignment will be placed in the TIMING_REQUIREMENTS section in
the ESF. When only the destination node is specified, the timing analyzer
will cut all paths forward from the register.
There are four other cut timing assignments that apply to a specific group
of paths. Table 20 lists the assignments and gives an example on how to
specify the assignments.
Table 20. Cut Timing Assignment Options in the Quartus II Software (Part 1 of 2)
Variable
Description
CUT_OFF_CLEAR_AND_PRESET_PATHS
Excludes the timing paths for clear and preset signals to a
D-type flipflop in the timing analysis.
For example:
project add_assignment "" "" "" ""
"CUT_OFF_CLEAR_AND_PRESET_PATHS" "ON";
CUT_OFF_IO_PIN_FEEDBACK
Cuts off the delay that is fed back from a bidirectional pin during
timing analysis.
For example:
project add_assignment "" "" "" ""
"CUT_OFF_IO_PIN_FEEDBACK" "ON";
CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS Eliminates the paths between unrelated clock domains from the
timing analysis.
For example:
project add_assignment "" "" "" ""
"CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS" "ON";
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Table 20. Cut Timing Assignment Options in the Quartus II Software (Part 2 of 2)
Variable
Description
CUT_OFF_READ_DURING_WRITE_PATHS
Cuts off the delay from the write enable register through the
embedded system block (ESB) to any destination register
during timing analysis.
For example:
project add_assignment "" "" "" ""
"CUT_OFF_READ_DURING_WRITE_PATHS" "ON";
Programmable Delay Settings
Altera devices offer many programmable delay settings around the
input/output element (IOE) that can be set through the Quartus II
software. Table 21 shows the available programmable delay settings for
Altera devices.
Table 21. Programmable Delay Options in Altera Devices
Variable
Devices Supported
DECREASE_INPUT_DELAY_TO_INPUT_REGISTER
Stratix, APEX 20K, APEX II, Excalibur, and Mercury
devices
DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS
Stratix, ACEX 1K, APEX 20K, APEX II, Excalibur,
FLEX 6000, FLEX 10KE, and Mercury devices
DECREASE_INPUT_DELAY_TO_OUTPUT_REGISTER
Stratix, APEX 20K, APEX II, and Excalibur devices
DELAY_SETTING_FROM_VIO_TO_CORE
APEX II
INCREASE_DELAY_TO_OUTPUT_ENABLE_PIN
Stratix and Mercury devices
INCREASE_DELAY_TO_OUTPUT _PIN
Stratix, APEX 20K, APEX II, Excalibur, and Mercury
devices
INCREASE_INPUT_DELAY_TO_CE_IO_REGISTER
Stratix, APEX 20K, APEX II, Excalibur, and Mercury
devices
INCREASE_TZX_DELAY_TO_OUTPUT_PIN
Stratix, APEX II, and Mercury devices
INCREASE_INPUT_CLOCK_ENABLE_DELAY
Stratix devices
INCREASE_OUTPUT_CLOCK_ENABLE_DELAY
Stratix devices
INCREASE_OUTPUT_ENABLE_CLOCK_ENABLE_DELAY Stratix devices
Since these settings only apply to a particular signal in the design, the
syntax is as follows:
project add_assignment "<project_name>" ""
""<signal_name>" "<delay_settings>" "<value>";
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Other Timing Settings
The Quartus II software assumes that all signals going to the clock port are
treated as a clock. However, you may make a NOT_A_CLOCK assignment
with the syntax shown in Figure 38.
Figure 38. Not_A_Clock Assignment
# Specify that a signal is not a clock.
project add_assignment "<project_name>" "" "" "<signal_name>" "NOT_A_CLOCK"
"ON";
For registers fed by an inverted clock, you may make an “Inverted Clock”
assignment as follows:
# Inform the Quartus II software that the register is
# fed by an inverted clock.
project add_assignment "<project_name>" "" ""
"<register_name>" "INVERTED_CLOCK" "ON";
If you want to ignore the clock settings, add the following assignment:
# Ignoring the user-defined clock settings.
project add_assignment "" "" "" ""
"IGNORE_CLOCK_SETTINGS" "OFF";
You can also specify minimum delay requirements for a signal going
through combinatorial logic with the following syntax:
# Setting a minimum delay requirement for combinatorial logic.
project add_assignment "" "" "" "" "MINIMUM_DELAY_REQUIREMENT"
"2ns";
For back-compatibility with the MAX+PLUS® II software, The Quartus II
software has a logic option to set CLKLOCKX1_INPUT_FREQ. Specifying
the option with a value is similar to instantiating an altclocklock
megafunction with its ClockBoostTM parameter set to 1.
Create a PLL with a ClockBoost parameter of 1 by using the following
syntax:
project add_assignment "<entity_name>" "" ""
"<clock_name>" "CLKLOCKX1_INPUT_FREQ"
"<freq in MHz>";
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Timing
Analysis
Commands
The Quartus II software reports the timing analysis result based on the
assignments that are made on the design. However, if a specific path is
desired, you can write Tcl commands to obtain the timing information.
This section describes how to set the timing analyzer and obtain timing
information for nodes in the design.
Setting the Timing Analyzer
Once the design compilation is complete, use the example code in
Figure 39 to run the timing analyzer.
Figure 39. Sample Code for Running the Analyzer after Compilation
# Run the timing analyzer after completing compilation.
project add_assignment "" "" "" "" "RUN_TIMING_ANALYSES" "ON";
The Quartus II software usually displays the timing analysis report based
on the timing constraints that you have put in your project. To include all
timing analysis in the compilation report regardless of whether any
timing requirements have been assigned, use the following code:
# Run the timing analyzer after completing compilation.
project add_assignment "" "" "" ""
"RUN_ALL_TIMING_ANALYSES" "ON";
You can modify the number of paths to report and the number of sources
and destinations to report in the timing analysis. See Figure 40.
Figure 40. Changing the Number of Paths to Report
# Set the number of paths to report.
project add_assignment "" "" "" "" "NUMBER_OF_PATHS_TO_REPORT" "200";
# Set the maximum number of destinations per path.
project add_assignment "" "" "" "" "NUMBER_OF_DESTINATION_TO_REPORT" "10";
# Set the maximum number of sources per destination.
project add_assignment "" "" "" ""
"NUMBER_OF_SOURCES_PER_DESTINATION_TO_REPORT" "10";
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In addition to choosing the number of paths, you can exclude specific
paths below or above a specific value. See Figure 41.
Figure 41. Excluding Specific Paths
# Do not report tCO paths that are less than 5 ns.
project add_assignment "" "" "" "" "EXCLUDE_TCO_PATHS_LESS_THAN" "5.0 ns";
# Do not report tH paths that are less than 1 ns.
project add_assignment "" "" "" "" "EXCLUDE_TH_PATHS_LESS_THAN" "1.0 ns";
# Do not report tPD paths that are less than 10 ns.
project add_assignment "" "" "" "" "EXCLUDE_TPD_PATHS_LESS_THAN" "10.0 ns";
# Do not report tSU paths that are less than 3 ns.
project add_assignment "" "" "" "" "EXCLUDE_TSU_PATHS_LESS_THAN" "3.0 ns";
# Do not report fMAX paths that are greater than 100 MHz.
project add_assignment "" "" "" "" "EXCLUDE_FMAX_PATHS_GREATER_THAN"
"100.0 MHz";
# Do not report paths with 10 ns or higher slack.
project add_assignment "" "" "" "" "EXCLUDE_SLACK_PATHS_GREATER_THAN"
"10.0 ns";
Find Timing Commands
To obtain timing delays using Tcl commands in the Quartus II software,
node IDs are used instead of the node names. Table 22 lists the commands
to obtain a node ID and the information for the node.
Table 22. Node Information Commands
Command
Description
cmp_get_timing_nodes <node_type>
Returns a list of node IDs from the timing analysis
network. The node_type can be one of the following:
all, reg, pin, clk, or comb.
cmp get_timing_node_info <info type>
<node id>
Returns the requested type of information for the
specified timing node. The info_type can be one of
the following: name, tSU, tH, tCO, type, location,
is_loop, or is_clock_inverted. The node_id is
the number returned from the cmp
get_timing_nodes command.
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Figure 42 shows how to use the commands in Table 22.
Figure 42. Determining the Number of Nodes
# Determine the number of nodes in the design. This code returns all the
# node numbers in the following format: {1} {2} {3} {4} {5}.
cmp get_timing_nodes all
# You can then use the following code to determine the node name
# representing node number 5. The code returns the hierarchical name of the
# node.
cmp get_timing_node_info name 5
# You can also use the following code to determine the node type
# representing node number 5.
cmp get_timing_node_info type 5
#
#
#
#
A more practical way to use this function is to list all the node IDs and
the corresponding names that are used later to find the timing
information. The following example describes how to perform
this task.
# Assuming there are only 20 node names to be listed, list all the node
# names.
for {set i 0} {$i < 20} {incr i} {
puts "$i [cmp get_timing_node_info name $i]"
}
After obtaining the list of node names and IDs, you can gather the timing
information by cross referencing the node ID and name. Table 23 lists the
find timing and get delays commands for the Quartus II software.
Table 23. Find Timing & Get Delays Commands (Part 1 of 2)
Command
Description
cmp find_period <type> <dst id> <dst clk id>
<src id> <src clk id>
Locates the maximum or minimum period of clock,
register, or register-to-register path. The type can be
either max or min.
cmp find_tco <pin id> <reg id> <clk id>
Locates the tCO delay for the specified pin, register,
and clock.
cmp find_th <pin id> <reg id> <clk id>
Locates the tH delay for the specified pin, register,
and clock.
cmp find_tsu <pin id> <reg id> <clk id>
Locates the tSU delay for the specified pin, register,
and clock.
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Table 23. Find Timing & Get Delays Commands (Part 2 of 2)
Command
Description
cmp get_clock_delay_path <path type>
<source id> <destination id>
Returns a list of the longest or shortest delay path
between a clock and a register. The path type is
either longest or shortest.
cmp get_delay_path <path type>
<source id> <destination id>
Returns a list of the longest or shortest delay path
between the specified source and destination nodes.
Used to return the path between pin-to-register,
register-to-register, and register-to-pin. The
path_type is either longest or shortest.
cmp get_delays_from_clocks <node id>
Returns the delay from each source clock to a
register
cmp get_delays_from_keepers <node id>
Returns the delays from pin-to-register, register-toregister, and pin-to-register. A keeper is a node of
the type pin, register, or clock.
Post
Compilation
Commands
After compilation, check for the timing information of the design to
ensure that all timing requirements are met. You can then locate signal
nodes in the floorplan, make location or custom region assignments, and
back-annotate the design or purge the Compiler result.
Getting the Location of a Node
Table 24 shows the commands to locate nodes either in the Floorplan
Editor or in the source code.
Table 24. Locating Nodes Commands
Command
Description
cmp get_locations
Returns the locations of all the nodes in the current
project.
cmp locate <signal_name> <Quartus II editor>
Locates the specified node in the specified
Quartus II editor. The Quartus II editor variable is
either floorplan or text.
cmp locate_to_current_assignment_floorplan
<signal_name>
Locates the specified node in the Current
Assignments floorplan.
cmp locate_to_floorplan <signal_name>
Locates the specified node in the Last Compilation
floorplan. This command is similar to
cmp locate <signal_name> floorpan.
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Making the Location Assignment
Making a location assignment is similar to making a pin assignment. To
make a location assignment, use the following syntax:
cmp add_assignment "<entity>" "" "<node>" "LOCATION"
"<location>";
Table 25 lists the location variables.
Table 25. Location Variables
Location Variable
TM
Syntax
Example Code
MegaLAB
interconnect
MegaLAB_ROW#COL#
(e.g., MegaLAB_A1)
# Assign the node to Megalab G2.
cmp add_assignment "filtref" ""
"acc:inst3|86~8" "LOCATION" "MegaLAB_G2";
Logic array block (LAB)
LAB_LE#_ROW#COL#
(e.g., LAB_1_A1)
# Assign the node to LAB 1 of Megalab G2.
cmp add_assignment "filtref" ""
"acc:inst3|86~7"
"LOCATION" "LAB_1_G2";
Embedded system block ESB_EC#_ROW#COL#
(ESB)
(e.g., ESB_1_A1)
1
# Assign the state machine state_m to
# ESB 1 of Megalab G2.
cmp add_assignment "filtref" ""
"state_m:inst1|37~5" "LOCATION"
"ESB_1_G2";
The <location> assignment does not apply to Stratix devices.
Refer to the Quartus II Floorplan Editor to obtain the syntax for
Stratix device locations.
Custom Region Assignment
To create a custom region, you must know the syntax for the location in
the Floorplan Editor. The example code in Figure 43 makes a custom
region in MegaLAB A1 and adds the node my_reg to the custom region.
Figure 43. Custom Region Assignment Example
# Assign my_reg to a custom region. The custom region itself spans from
# LAB 1 of MegaLab A1 to LAB 16 of MegaLab A1.
cmp add_assignment "my_program" "" "my_reg" "LOCATION"
"CUSTOM_REGION LAB_1_A1 LAB_16_A1";
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Other Post-Compilation Commands
The following is a list of other post-compilation commands:
■
■
LogicLock
Assignment
Back-annotate a design. For example:
# Back annotate the whole design down to the
# MegaLAB blocks
cmp full_back_annotate
Purge Compiler result. For example:
# Purge the Compiler result
cmp purge_compiler_result
All LogicLockTM attributes and assignments are stored in a project’s ESF
which is associated with the corresponding entity in a design. You can use
Tcl commands to create your LogicLock assignment. Table 26 shows the
available LogicLock variables in the Quartus II software version 2.0.
Table 26. LogicLock Variables in the Quartus II Software Version 2.0
Variable
LL_AUTO_SIZE (1)
Description
Specifies if the LogicLock region is auto sized. When this option is on, LL_STATE
must be floating.
LL_HEIGHT (1)
Specifies the LogicLock region’s height in rows.
LL_MEMBER_OF
Specifies the name of the LogicLock region where the target node or entity is
assigned; if no target is determined, specifies the LogicLock region where all nodes
or entities in a design are assigned by default. This keyword is case sensitive.
LL_MEMBER_STATE
Specifies whether the target node or entity is locked down or floating inside the
LogicLock region; if no target is determined, specifies whether all nodes or entities
assigned to this LogicLock region are locked or floating by default. The target node
or entity must be assigned to the LogicLock region.
LL_NODE_LOCATION
Specifies the location (by LAB or ESB) where the target node is back-annotated. The
location is relative to the LogicLock region’s LL_ORIGIN setting. This keyword is
case sensitive. The target node must be assigned to the LogicLock region, and this
node’s LL_MEMBER_STATE setting must be locked.
LL_ORIGIN (1)
Specifies the location (by LAB or ESB) of the LogicLock region’s top-left corner.
LL_PARENT
Specifies the name of the LogicLock region’s parent region. This keyword is case
sensitive.
LL_STATE (1)
Specifies whether the location of the LogicLock region is locked or floating. The
Compiler determines an appropriate location for floating regions during compilation.
If this keyword is set to locked, LL_AUTO_SIZE must be set to off. This keyword is
case sensitive.
LL_WIDTH (1)
Specifies the width of the LogicLock region in the LABs or ESBs.
Notes to Table 26:
(1)
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This variable must be set for any LogicLock region.
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Table 27 lists the LogicLock commands available in the Quartus II
software version 2.0.
Table 27. LogicLock Commands in the Quartus II Software Version 2.0
Commands
Description
cmp logiclock_back_annotate
<logiclock_region> <demote_to_lab>
<back_annotate_nodes>
Back-annotates one or more LogicLock region in the
design.
cmp logiclock_export
<file_name> <export_focus>
Saves all the LogicLock region definitions and
assignments applicable to the specified export focus
and its sub-entities to the specified ESF.
cmp logiclock_import
<do_pins> <do_ll> <do_non_ll> <do_update>
<allow_create> <region_name>
Traverses the design hierarchy starting at the current
compilation focus; for each entity, imports the
assignment types specified by the arguments from the
entity’s ESF to the top-level ESF.
1
For more information on the LogicLock feature, refer to AN 161:
Using the LogicLock Methodology in the Quartus II Design Software.
Creating a Floating LogicLock Region
The code in Figure 44 describes how to create a LogicLock region, add
nodes to a region, create LogicLock ‘cliques’, import a LogicLock region,
preserve hierarchy boundary, and back-annotate a LogicLock region
using Tcl scripts. For the example, the top-level design is called top with
two sub-modules called counter and reg.
Figure 44. Creating a LogicLock Region
# counter.tcl
# Create a floating LogicLock region for the entity counter. Start a batch
# of commands.
project start_batch counter
# Specify that the module my_counter is a member of the LogicLock region
# LLR_COUNTER.
project add_assignment "counter" "LLR_COUNTER" "" "my_counter"
"LL_MEMBER_OF" "LLR_COUNTER"
# Set the LogicLock region height to 4 rows.
project add_assignment "counter" "LLR_COUNTER" "" "" "LL_HEIGHT" "4"
# Set the LogicLock region width to 4 LABs.
project add_assignment "counter" "LLR_COUNTER" "" "" "LL_WIDTH" "4"
Code Continued on Next Page...
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# Specify that LLR_COUNTER is a floating LogicLock region
project add_assignment "counter" "LLR_COUNTER" "" "" "LL_STATE" "FLOATING"
# Set the origin of the LogicLock region. You still need the line of code
# below when you are creating a floating LogicLock region.
project add_assignment "counter" "LLR_COUNTER" "" "" "LL_ORIGIN" "LAB_1_A1"
# Since the height and width are defined,set auto-size to off.
project add_assignment "counter" "LLR_COUNTER" "" "" "LL_AUTO_SIZE" "OFF"
# End the batch of commands.
project end_batch counter
# reg.tcl
# Create a floating LogicLock region for the entity reg. Start a batch of
# commands.
project start_batch reg
# Specify that the module reg is a member of the LogicLock region
# LLR_REG.
project add_assignment "reg" "LLR_REG" "" "" "LL_MEMBER_OF" "LLR_REG"
# Set the LogicLock region height to 2.
project add_assignment "reg" "LLR_REG" "" "" "LL_HEIGHT" "2"
# Set the LogicLock region width to 2 LABs.
project add_assignment "reg" "LLR_REG" "" "" "LL_WIDTH" "2"
# Since the height and width are defined, set auto-size to off.
project add_assignment "reg" "LLR_REG" "" "" "LL_AUTO_SIZE" "OFF"
# Specify that LLR_REG is a floating LogicLock region.
project add_assignment "reg" "LLR_REG" "" "" "LL_STATE" "FLOATING"
# Specify that the module reg is a member of the LogicLock region
# LLR_REG.
project add_assignment "reg" "LLR_REG" "" "" "LL_MEMBER_OF" "LLR_REG"
# Set the origin of the LogicLock region. You still need the line of code
# below when you are creating a floating LogicLock region.
project add_assignment "reg" "LLR_REG" "" "" "LL_ORIGIN" "LAB_1_A1"
# End the batch of commands.
project end_batch reg
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The generated content of the ESF after running reg.tcl and counter.tcl is
as follows:
counter.esf
LOGICLOCK_REGION (LLR_COUNTER)
{
LL_AUTO_SIZE = OFF;
LL_HEIGHT = 4;
LL_WEIGHT = 4;
LL_STATE = FLOATING;
LL_MEMBER_OF = LLR_COUNTER;
LL_ORIGIN = LAB_1_A1;
}
reg.esf
LOGICLOCK_REGION (LLR_REG)
{
LL_AUTO_SIZE = OFF;
LL_STATE = FLOATING;
LL_HEIGHT = 2;
LL_WEIGHT = 2;
LL_MEMBER_OF = LLR_REG;
LL_ORIGIN = LAB_1_A1;
}
Creating an Auto-Size LogicLock Region
The commands in Figure 45 will place module counter:CNT in a floating
auto-sized region in top.esf.
Figure 45. Creating an Auto-Size LogicLock Region
# Start a batch of commands.
project start_batch top
# Create an auto-sized LogicLock region LLR_0.
project add_assignment "top" "LLR_0" "" "" "LL_AUT0_SIZE" "ON"
# Place counter:CNT as a member of the LogicLock region LLR_0.
project add_assignment "top" "LLR_0" "" "counter:CNT" "LL_MEMBER_OF"
"LLR_0"
# Specify that counter:CNT is a floating member of LLR_0.
project add_assignment "top" "LLR_0" "" "counter:CNT" "LL_STATE" "FLOATING"
# End the batch of commands.
project end_batch top
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Add a Node or Hierarchy to a Region
The example in Figure 46 describes how to add the entity my_reg into the
LLR_REG region as a floating node.
Figure 46. Adding a Node or Hierarchy to a Region
# Add entity my_reg into the LogicLock region LLR_REG.
project add_assignment "reg" "LLR_REG" "" "reg:my_reg" "LL_MEMBER_OF"
"LLR_REG"
# Specify that my_reg is a floating member of the LogicLock region LLR_REG.
project add_assignment "reg" " LLR_REG" "" "reg:my_reg" "LL_MEMBER_STATE"
"FLOATING"
Preserving Hierarchy Boundary
Preserving hierarchy boundary for all entities or called instances for
which node-level entities are made is optional but essential for
incremental placements. To ensure that the Quartus II software does not
rename the nodes, the Tcl commands in Figure 47 will disable the crossboundary optimizations for the sample blocks.
Figure 47. Preserving Hierarchy Boundaries
# Disable cross-boundary optimization for all instances in the module
# counter.
project add_assignment "counter" "" "" "" "PRESERVE_HIERARCHICAL_BOUNDARY"
"RELAXED"
# Disable cross-boundary optimization for module reg:REG_A in the top
# design.
project add_assignment "top" "" "" "reg:REG_A"
"PRESERVE_HIERARCHICAL_BOUNDARY" "RELAXED"
Importing an Entities’ Regions
The Tcl commands in Figure 48 perform elaboration and synthesis for the
whole design, and import all lower-level LogicLock regions for the
project.
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Figure 48. Performing Elaboration & Synthesis
# Perform a netlist extraction of the design.
cmp add_assignment "" "" "" "COMPILATION_LEVEL" "SYNTHESIS ONLY"
puts "--- Elaborating ---"
# Start the Compiler.
cmp start
while { [cmp is_running] } {
FlushEventQueue
}
puts "--- Importing LogicLock Regions ---"
# Import all LogicLock regions for the project.
cmp logiclock_import
After you execute the cmp logiclock_import command, the
LogicLock regions are imported into the top.esf file, and the LogicLock
constraints within files counter.esf and reg.esf will be enforced. One
LogicLock region is included for reg:REG_A, reg:REG_B, and
counter:CNT. You can see these regions in the generated top.esf file.
Back-Annotating Placement Results
After compilation, it is possible to back-annotate the placement of the
whole or individual part of the circuit. The LogicLock back-annotate
command creates LL_NODE_LOCATION assignments and stores them
within the ESF (see Figure 49).
Figure 49. Back-Annotating Placement Results
# Back-annotate LogicLock region LLR_0 and all its regions, but not the
# nodes.
cmp logiclock_back_annotate "LLR_0" 0 0
Other LogicLock Assignments
When performing an incremental compile, you must add the following
lines to the Tcl script, as shown in Figure 50.
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Figure 50. Incremental Compile
# Turn incremental compilation on. The synthesis result will be saved in a
# VQM file
cmp add_assignment "" "" "" "LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT"
"ON";
# Specify the name of the synthesis result. Based on the below code,the
# Quartus II software will create my_entity.vqm in the same directory as
# the project directory.
cmp add_assignment "" "" "" "LOGICLOCK_INCREMENTAL_COMPILE_FILE"
"my_entity.vqm";
The Quartus II software version 2.0 offers an alternate LogicLock Fitter
algorithm that you can invoke with the following code:
# Use the alternate LogicLock Fitter.
cmp add_assignment "" "" "" "LOGICLOCK_FITTER_TYPE"
"ON";
Simulation
The simulation settings are written into the SSF. Use the command
sim start_batch coupled with sim end_batch around a sequence of
sim add_assignment commands to speed up assignment processing.
Table 28 shows the description of the commands in this section.
Table 28. Add/Remove Assignments for an SSF
Command
Description
sim add_assignment
<section identifier> <source> <target>
<variable> <value>
Adds an assignment to the current Simulator settings.
sim remove_assignment
<section identifier> <source> <target>
<variable> <value>
Removes an assignment from the current Simulator
settings.
sim start_batch <entity>
Used when many assignment commands (e.g.,
sim add_assignment) are used in a row. Add this
command before the set of commands. Add
sim end_batch after the set of commands.
sim end_batch <entity>
Used when many assignment commands (e.g.,
sim add_assignment) are used in a row. Add this
command after the set of commands.
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Setting an Active Simulation Setting
Before simulating a design, you must create a group of Simulator settings
and initialize the Simulator. Simulator settings are saved in an SSF. Once
you determine the simulation focus, the focus-level simulation setting file
will be created accordingly. Table 29 shows the Simulator setting
commands.
Table 29. Simulator Setting Commands
Command
Description
project sim_exists <settings>
Determines whether the <setting>.ssf already exist in
the current project.
project create_sim <settings>
Creates <settings>.ssf and designates the settings as
the current Simulator settings for the project.
project set_active_sim <settings>
Designates the specified Simulator settings as the
current Simulator settings for the project.
Similar to Compiler settings, you can combine the commands. The code in
Figure 51 checks whether a Simulator setting exists for the fir_filter
design in the Quartus II tutorial. If not, the code will create one and set it
as the active Simulator setting.
Figure 51. Checking for Simulator Setting
# Check if the filtref Simulator setting already exists.
if {![project sim_exists filtref]} {
# If filret.ssf does not exist, create it.
project create_sim filtref
# Set the filtref Simulator setting to active.
project set_active_sim filtref
}
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Controlling the Simulator
Table 30 lists the commands to control the Simulator.
Table 30. Simulator Commands
Command
Description
sim initialize
Initializes the Simulator to read all netlists, and sets the
simulation time to zero.
sim run <time>
Simulates for a given time. If <time> is “end”, then
simulate to completion and exit.
sim start
Starts the Simulator for the active or current Simulator
settings.
sim stop
Stops the Simulator.
sim is_initialized
Checks if the Simulator has been initialized.
sim is_running
Checks if the Simulator is running.
sim print <type>
Displays a given string as a Quartus II message (in the
message window). The type can be info, warning, or
error.
sim read_from_memory <hpath> <address>
Reads the memory word from the given address of a
given logical memory. The hpath variable is the
hierarchical name of the memory.
sim write_to_memory <hpath> <address> <data> Writes a given memory word to a given address
location of a given logical memory. The hpath variable
is the hierarchical name of the memory.
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You must initialize the Simulator before making any simulation
assignment or performing a simulation. The code in Figure 52 shows an
example of initializing the Simulator and making a simulation assignment
for the fir_filter design (from the Quartus II tutorial).
Figure 52. Initializing the Simulator
# Initialize the Simulator.
sim initialize
# Start a batch of commands.
sim start_batch;
# Set the simulation focus to filtref.
sim add_assignment "" "" "" "FOCUS_ENTITY_NAME" "|filtref";
# Let the Quartus II software add all pins in the design to the simulation
# output waveform.
sim add_assignment "" "" ""
"ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS" "ON";
# Use the netlist created by the Compiler settings filtref.
sim add_assignment "" "" "" "USE_COMPILER_SETTINGS" "filtref";
# Use fir.vwf as the input waveform file.
sim add_assignment "" "" "" "VECTOR_INPUT_SOURCE" "fir.vwf";
# Turn off setup and hold time detection.
sim add_assignment "" "" "" "SETUP_HOLD_DETECTION" "OFF";
# Turn off estimate power consumption.
sim add_assignment "" "" "" "ESTIMATE_POWER_CONSUMPTION" "OFF";
# Turn on glitch detection.
sim add_assignment "" "" "" "GLITCH_DETECTION" "ON"
# Specify a glitch detection of 2 ns. The Quartus II software will flag a
# glitch if there are 2 logic transitioned within 2 ns.
sim add_assignment "" "" "" "GLITCH_INTERVAL" "2ns"
# Enable the simulation coverage report.
sim add_assignment "" "" "" "SIMULATION_COVERAGE" "ON"
# Turn off waveform comparison.
sim add_assignment "" "" "" "CHECK_OUTPUTS" "OFF"
# Perform timing simulation.
sim add_assignment "" "" "" "SIMULATION_MODE" "TIMING";
# Specify the start time to 1 ns.
sim add_assignment "" "" "" "START_TIME" "1ns"
# Specify the end simulation time to 100 ns.
sim add_assignment "" "" "" "END_TIME" "100ns"
# End the batch of commands.
sim end_batch
# Run the Simulator until END_TIME.
sim run END_TIME
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Retrieving Simulator Assignments
Similar to project assignments, you can retrieve all the assignments that
are made to the Simulator settings. Table 31 shows all the Tcl commands
that you can use to retrieve Simulator assignments in the Quartus II
software.
Table 31. Retrieving Simulator Assignments Commands
Command
Description
sim get_all_assignments <source> <target>
Returns a list of all the specified assignments for the
specified statement(s) in the project’s current SSF.
sim get_assignment_count <source> <target>
Returns the number of assignments that exist in the
specified statement(s) of the project’s current SSF.
sim get_assignment_value
<section_identifier> <source> <target>
<variable>
Returns the value(s) for the specified assignment in the
specified section(s) and statement(s) of the project’s
current SSF.
sim get_memory_depth <hpath>
Returns the depth (number of words or addresses) of
the specified logic memory. The hpath is the
hierarchical name of the logic memory.
sim get_memory_width <hpath>
Returns the width (number of bits per memory word) of
the specified logic memory. The hpath is the
hierarchical name of the logic memory.
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Simulation with Testbench
During this mode, the Quartus II software does not display message
dialog boxes during processing the simulation. No vector file (.vec) or
Vector Waveform File (.vwf) is required when the Quartus II Simulator is
running in testbench mode. Table 32 describes the interactive Simulator
commands that you need in testbench mode.
Table 32. Interactive Simulator Commands
Command
Description
sim force_value <signal name>
Forces the value of the signal name signal to 1 or 0
(designate 1 to force the value high, and 0 to force the
value low).
sim release_value <signal name>
Releases the value of the signal name signal to revert
back to the original state.
sim get_value <signal name>
Checks the value of the signal name signal.
sim run <time>
Adds a value after the sim run command specifying the
length of time to run the Simulator.
sim run end
Runs the simulation until completion.
sim get_time
Checks for the current time of the on-going simulation.
sim testbench_mode
Directs the Quartus II software to enter or exit
testbench mode. When in testbench mode, the
Quartus II software does not display message dialog
boxes after you use the sim run API function, and does
not return errors if a VWF or VEC file is not used.
The Tcl script sample in Figure 53 opens a project named “counter,” sets
the simulation inputs using a Tcl testbench, and outputs the results of the
simulation to either a file or the screen. The design project is a 4-bit
counter with a clk and an aclr input port, and a q and cout output port.
1
To record the simulation messages and results into a file instead
of displaying them on the screen, you can run the sample (see
Figure 53) Tcl script from the command prompt:
quartus_cmd -f counter_sim.tcl >results.txt r
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Figure 53. A Sample Script to Simulate a Design
# This output redirection process will save the simulation outputs to a
# text file called results.txt.
# Change to the working directory.
cd d:/quartus/qdesigns/counter
# Open the project, assuming that you have created the project.
project open counter
# Create the simulation setting file (counter.ssf) for the module counter.
# Check if counter.ssf already exists.
if { ![project sim_exists counter] } {
# If it does not exist, create counter.ssf
project create_sim counter
}
# Set the counter as the active Simulator settings.
project set_active_sim counter
# Perform timing simulation.
sim add_assignment "" "" "" SIMULATION_MODE TIMING
# Set the start time of the simulation to 1 ns.
sim add_assignment "" "" "" START_TIME 1ns
# Set the end time of the simulation to 100 ns.
sim add_assignment "" "" "" END_TIME 100ns
# Check all assignments made to the simulation setting file by retrieving
# all the assigned values.
sim get_all_assignments "" ""
# Initialize the Simulator for the current design focus. During
# initialization, the Quartus II Simulator builds the simulation netlists
# and sets the simulation time to zero.
sim initialize
# Check to see if initialization is complete.
while { ![sim is_initialized] } {
# If the Simulator is not yet initialized, flush the Quartus II messages.
FlushEventQueue
}
# Enter testbench mode.
sim testbench_mode true
Code Continued on Next Page...
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# Start the testbench. Set the initial value of input signals aclr and clk
# to 0.
sim force_value aclr 0
sim force_value clk 0
# Check the initial values of inputs and outputs by gathering the values and
# printing them out to the screen or output file.
sim print info "clk = [sim get_value clk]"
sim print info "aclr = [sim get_value aclr]"
sim print info "q = [sim get_value q]"
sim print info "cout = [sim get_value cout]"
# Set the clock period to 20 ns a cycle and display the resulting values of
# the signals every 10 ns.
for { set i 0} {$i < 50 } {incr i 1} {
sim force_value clk 0
sim run 10ns
sim print info "clk = [sim get_value clk]"
sim print info "aclr = [sim get_value aclr]"
sim print info "q = [sim get_value q]"
sim print info "cout = [sim get_value cout]"
sim force_value clk 1
sim run 10ns
sim print info "clk = [sim get_value clk]"
sim print info "aclr = [sim get_value aclr]"
sim print info "q = [sim get_value q]"
sim print info "cout = [sim get_value cout]"
}
# End the testbench.
# The following command directs the Quartus II software to exit testbench
# mode.
sim testbench_mode false
# Close the project.
project close
# Terminate the script.
exit
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Software Build
The Quartus II software version 2.0 offers Software mode in which you
can use the Software Builder to process a design for an Excalibur device or
a Nios® embedded processor. This section describes how to create
software build settings and how to run the software build. Table 33 shows
the commands to make and retrieve assignments from the project’s FSF.
Table 33. Making & Retrieving Assignments in an FSF
Command
Description
swb add_assignment <section identifier>
<source> <target> <variable> <value>
Adds an assignment to the current software build
settings.
swb remove_assignment
<section identifier> <source> <target>
<variable> <value>
Removes an assignment to the current software build
settings.
swb get_all_assignments <source> <target>
Returns a list of all the assignments and values for the
specified statement(s) in the project’s current FSF.
swb get_assignment_count <source> <target>
Returns the number of assignments in the project’s
current FSF.
swb get_assignment_value
<section_identifier> <source> <target>
<variable>
Returns the value(s) for the specified assignment in the
specified section(s) and statement(s) of the project’s
current FSF.
Creating Software Build Settings
You must create software build settings and make assignments before
doing a software build. Software build settings are saved in an FSF.
Table 34 shows the commands for the software build settings.
Table 34. Software Build Setting Commands
Command
Description
project swb_exists <settings>
Determines whether the specified software build
settings exist in the current project.
project create_swb <settings>
Creates software build settings with the specified name
and designates the settings as the current software
build settings for the project.
project set_active_swb <settings>
Designates the specified software build settings as the
current software build settings for the project.
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AN 195: Scripting with Tcl in the Quartus II Software
Two types of software builds exist: debug and release. The example code
in Figure 54 shows how to check if there is a release software build setting,
and how to create one if there is none.
Figure 54. Release Software Build Setting
if {![project swb_exists Release]} {
project create_swb Release;
}
project set_active_swb Release;
Controlling the Software Build
Table 35 shows the commands needed to control the software build.
Table 35. Software Build Command
Command
Description
swb is_running
Determines whether a software build is currently
running.
swb start
Starts a software build.
swb stop
Stops a software build.
swb purge_intermediate_files
Removes the intermediate files created during the last
software build for the current software build settings.
Table 36 shows the settings for the software build.
Table 36. Software Build Settings (Part 1 of 3)
Command
Description
ARM_ASM_COMMAND_LINE
Specifies the command-line options for the ADS standard
tools assembler that is used to compile Assembly language
files.
ARM_CPP_COMMAND_LINE
Specifies the command-line options for the ADS standard
tools C/C++ Compiler that is used to compile C source files
(.c) and C++ source files (.cpp).
ARM_LINK_COMMAND_LINE
Specifies the command-line options for the ADS standard
tools’ linker that is used to link object files, resolve undefined
symbols, and generate an executable and linkable format
file (.elf).
Altera Corporation
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AN 195: Scripting with Tcl in the Quartus II Software
Table 36. Software Build Settings (Part 2 of 3)
Command
Description
BYTE_ORDER
Specifies the byte order of the memory initialization data for
an Excalibur embedded processor stripe (either little endian
or big endian).
CUSTOM_BUILD_COMMAND_LINE
Specifies the command-line command you want to run when
you choose Custom-build in the software toolset list by
clicking the CPU tab of the Software Build Settings
command (Processing menu).
DO_POST_BUILD_COMMAND_LINE
Specifies whether the post-build command line should be
run after a successful build. This keyword is case sensitive.
FLASH_PROGRAMMING_FILE_NAME
Specifies the Slave Binary Image File (.sbi) that is included
in the programming file when Excalibur device is configured
from flash memory.
GNUPRO_ARM_ASM_COMMAND_LINE
Specifies the command-line options that is used for the
GNUPro® for the ARM® assembler.
GNUPRO_ARM_CPP_COMMAND_LINE
Specifies the command-line options that is used for the
GNUPro for the ARM C/C++ Compiler.
GNUPRO_ARM_LINK_COMMAND_LINE
Specifies the command-line options that is used for the
GNUPro for the ARM linker.
GNUPRO_NIOS_ASM_COMMAND_LINE
Specifies the command-line options for the GNUPro that is
used for the Nios assembler (generates Assembly files).
GNUPRO_NIOS_CPP_COMMAND_LINE
Specifies the command-line options for the GNUPro for the
Nios C/C++ Compiler that is used to compile C files and CPP
source files.
GNUPRO_NIOS_LINK_COMMAND_LINE
Specifies the command-line options for the GNUPro for the
Nios linker that is used to link together object files, resolve
undefined symbols, and generate an ELF.
OUTPUT_FILE_NAME
Specifies the file name for the Intel Hexadecimal File (.hex),
Motorola S-Record File (.srec), Binary File (.bin), or Library
File (.a) that the Software Builder generates during a
software build.
OUTPUT_TYPE
Specifies whether you want the Software Builder to generate
a HEX, SREC, BIN, or A file during a software build.
PASSIVE_PROGRAMMING_FILE_NAME
Specifies the name of the programmable logic Partial SRAM
Object File (.psof) that generates a passive programming
file.
POST_BUILD_COMMAND_LINE
Specifies the command-line command you want the
Software Builder to run after it completes a successful
software build.
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AN 195: Scripting with Tcl in the Quartus II Software
Table 36. Software Build Settings (Part 3 of 3)
Command
Description
PROCESSOR
Specifies whether you want to use the embedded processor
core for the Software Builder that is used to build a software
application.
PROGRAMMING_FILE_TYPE
Specifies whether you want the Software Builder to generate
a flash programming file, passive programming file, or no
programming files when performing a software build.
TOOLSET
Specifies the software toolset for the Software Builder that is
used when performing a software build.
USE_C_PREPROCESSOR_FOR_GNU_ASM_FILES
Directs the Software Builder to use the GNUPro for ARM or
the GNUPro for the Nios C/C++ pre-processor on the
Assembly files (.s, .asm) that you are using to generate a
HEX, SREC, BIN, or A file. This keyword is case sensitive.
References
For more information on using Tcl, refer to the following sources:
■
■
■
■
Practical Programming in Tcl and Tk, Brent B. Welch
Tcl and TK Toolkit, John Ousterhout
Effective Tcl/TK Programming, Michael McLennan and Mark Harrison
Tcl Developer Xchange at http://tcl.activestate.com
Contact
Information
For technical support, contact Altera Applications at (800) 800-EPLD or
access mySupport at http://mysupport.altera.com.
Revision
History
The information contained in AN 195: Scripting with Tcl in the Quartus II
Software version 1.1 supersedes information published in previous
versions.
Version 1.1
AN 195: Scripting with Tcl in the Quartus II Software version 1.1 contains the
following changes:
■
Altera Corporation
Updated Figure 48.
71
AN 195: Scripting with Tcl in the Quartus II Software
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
http://www.altera.com
Applications Hotline:
(800) 800-EPLD
Literature Services:
lit_req@altera.com
72
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