EELE 367 – Logic Design
Lab #1 – Introduction to Altera’s Quartus II and the DE2 Board
Lab Description
Today’s lab will introduce you to Altera’s Quartus II Integrated Design Environment (IDE) and the DE2
board that contains a Cyclone II C35 FPGA. In this lab, you will walk through an Altera Quartus Tutorial
in which you will complete the entire digital design from VHDL to functioning hardware on the FPGA.
Any files you need are provided on the course website. The source code is also provided for you to
copy/paste in the design tool. Although it is very short so you can easily type it in. There is no pre-lab or
lab report for this lab. I encourage you to work in teams of two. I recommend that if you work in teams of
two, you take turns being the one that runs the tool (i.e., types) each week. This will ensure that both of
you are getting the most out of the labs.
Quartus II Tutorial
The tutorial that you will follow is the Quartus II Introduction Using VHDL Design tutorial that you can
find on the course website. This tutorial was written using an older version of Quartus II. We have
installed a newer version on the lab computers, so there will probably be a few differences, but you
should be able to get a good enough idea of how to proceed.
To get credit for this lab, you will need to demonstrate a working design on the DE2 board and have the
instructor sheet (found at the end of this lab) signed off. Turn in this sign off sheet to the lab instructor. If
you are working in teams of two, put both of your names on one sheet.
In Section 5 on pin assignments, the information comes from the DE2 user manual (also on the course
website) that tells how the FPGA is connected to the external circuits. The switch connections can be
found in the table starting on page 28. The LED connections can be found in the table starting on page
29.
The new version of Quartus II (v10.0 SP1) in the lab has removed the timing simulation feature. So you
will skip Section 6 in the tutorial on “functional simulation” and “timing simulation”. We will cover timing
verification later in the semester.
Additional Resources for learning the Quartus II IDE
There is an interactive tutorial shipped with Quartus II. It can be found by pointing your browser at:
C:\altera\91\quartus\common\help\tutorial\qtutorial.htm
If you get an Adobe Flash Player Security warning, just exit the warning via the red x on the upper right.
Altera has free online training on their web site. This can be viewed at:
http://www.altera.com/education/training/curriculum/fpga/trn-fpga.html
You will notice that there is the Quartus II Software Design Series half way down on the right side (8
hours worth) in addition to many other on-line tutorials. They are free, but you will need to register to get
access to the tutorials.
1
EELE 367 – Logic Design
Lab Instructor Verification Sheet
Lab #1
Quartus II Introduction Using VHDL Design
Name(s) :
_______________________ / ________________________
Show the lab instructor the following demos:
Demo #1:
Your functioning hardware (i.e., setting the switches and looking at LED)
(5 points)
Verified By: ___________________ Date: ______________
2