TABLE OF CONTENTS
CHAPTER
1
TITLE
PAGE
DECLARATION
ii
DEDICATION
iii
ACKNOWLEDGEMENTS
iv
ABSTRACT
v
ABSTRAK
vi
TABLE OF CONTENTS
vii
LIST OF FIGURES
xi
LIST OF TABLES
xv
LIST OF SYMBOLS
xvii
LIST OF APPENDIX
xix
INTRODUCTION
1
1.1
Research Background
1
1.2
Motivation
6
1.3
Problem Statement
6
1.4
Research Problems
7
1.5
Research Objectives
8
1.6
Scope of the Study
8
1.7
Significance of Findings
8
1.8
Research Workflow
9
1.9
Thesis Outline
13
2
LITERATURE REVIEW
15
2. 1
Introduction to Electronic Design Automation (EDA)
15
2. 2
Mathematical Model
17
2. 3
Routing in PCB/VLSI Design
19
2. 4
Single-row Routing Problem
20
2. 5
Global Routing Problem
22
2.5.1
Global Routing Methods
24
The Single-source Shortest Path problem
25
2.6.1
Eigenvalue of an Adjacency Matrix
27
2.6.2
Breadth-first Search Method
29
2.6.3
Example on BFS
29
2.6.4
Dijkstra‟s Algorithm
32
2.6.5
Example of Dijkstra‟s Algorithm
34
2.6.6
Proof of Correctness of Dijkstra‟s Algorithm
36
2.6.7
Related Algorithms
37
2.6.8
Applications of Dijkstra‟s Algorithm
40
2. 6
2. 7
2. 8
2. 9
3
Exact Method and Approximate Method
41
2.6.1
41
Simulated Annealing Technique
Interconnection Networks
43
2.8.1
43
Network-on-Chip Topologies
Conclusion
47
THREE-DIMENSIONAL CYLINDRICAL MODEL FOR
SINGLE-ROW DYNAMIC ROUTING
49
3.1
Introduction
49
3.2
Problem Background
51
3.3
Energy Level Diagram and Graphical Realization
53
3.4
Enhanced
Simulated
Annealing for
Single-row
Routing (ESSR)
3.5
56
Multi Connection of Pins Using the Cylindrical
Model
59
ix
3.5.1
4
59
3.6
The Dynamic SA-CM Model
65
3.7
Simulation Results
69
3.8
Conclusion
71
SEQUENTIAL GLOBAL ROUTING PROBLEM IN
VLSI DESIGN
73
4.1
Introduction
73
4.2
Problem Statement
77
4.3
Mathematical Model
78
4.4
The Impact of Net Ordering on Global Routing
80
4.5
Heuristics Improvement
81
4.5.1
Simulated Annealing Method
82
4.5.2
Initial Algorithm for Routing
82
4.5.3
Routing Algorithm
83
4.5.4
Greedy Method
85
4.6
4.7
4.8
5
Maximum Possible Net Ordering
Layers for The Minimization Model
87
4.6.1
88
Simulation Results
Obstacle-Avoiding Problem
97
4.7.1
199
Simulation Results
Conclusion
104
SEMI-DIAGONAL TORUS NETWORK FOR
GENERAL PURPOSE NETWORKING
APPLICATIONS
105
5.1
Introduction
105
5.2
Problem Statement
108
5.3
Mesh and Torus Network Topologies
109
5.3.1
Mesh Network Topologies
109
5.3.2
Torus Topologies
110
x
5.4
Semi-Diagonal Torus Network
111
5.4.1
Topological Properties
112
5.4.2
Network Diameter
113
5.4.3
Number of Communication Links in a
5.4.4
Network
115
Topological Properties Comparison
118
5.5
SA-SDT Routing Network
118
5.6
Simulation Results
120
5.6.1
Comparison Between Network Topologies
121
5.6.2
Comparison Between Simulated Annealing
and Greedy Method
5.7
6
Conclusion
126
128
CONCLUDING REMARKS AND FURTHER WORK
130
6.1
Summary of Findings
130
6.2
Suggestions for Further Research
134
REFERENCES
135
Appendix
148
xi
LIST OF FIGURES
FIGURE NO.
1.1
TITLE
PAGE
The demand for electronic circuits during vacuum-tube
era and during the invention of transistor and ICs.
2
The chip scope and the sequence of technologies
in circuit integration.
3
1.3
Evolution on bus on-chip communications.
4
1.4
A 4  4 mesh NoC topology.
5
1.5
Research workflow.
12
2.1
General flow of physical design.
16
2.2
The single-row routing terminologies .
21
2.3
(a) Partitioned layout into n  n rectangular array.
(b) Resource modeling. (c) Global-routing graph.
23
2.4
Previous approach on sequential global routing.
24
2.5
A connected graph.
26
2.6
Graph to be explored using breadth-first search method.
30
2.7
The neighbors of vertex 1 have been explored and
queued up.
30
Current status of BFS progress. Next entries in the
queue list are vertex 5 and vertex 6.
31
2.9
The BFS tree constructed from graph shown in Figure 2.6.
31
2.10
The connected graph.
34
2.11
The schematic illustration for the justification of
Lemma 2.1.
36
1.2
2.8
xii
2.12
Several popular approaches to single-source and all pairs
shortest path problem.
39
2.13
Simulated annealing graph.
42
2.14
The hardware model of processing system [105].
43
2.15
DMesh network topology.
44
2.16
XTorus network topology.
45
2.17
DTorus network topology.
45
2.18
Related NoC topologies.
47
3.1
Node axis.
51
3.2
A regular hexagon has 6 lines of symmetry, a regular
octagon has 8 lines of symmetry but a circle has
unlimited symmetrical axis.
52
3.3
The components of cylindrical model.
52
3.4
Formation of interval lines for L  {N3 , N1, N2 , N5 , N4}.
53
3.5
The reference line that joint each i th and (i  1) th points
in the diagram.
54
The energy level diagram for the interval graphical
representation of Figure 3.2.
55
Graphical realization for net ordering
L  {N3 , N1 , N2 , N5 , N4 } .
55
3.8
ESSR Flowchart [20].
58
3.9
A tree diagram to calculate maximum number of net
orderings for n number of pins.
62
Front view of the cylindrical model showing the axis ai
for all 15 planes.
66
The position of the respective planes for all single-row
routing realizations in the cylindrical model for n  6.
(The drawing for L5 and L12 is omitted due to limited
drawing space. The realization of these sequences have
been provided in Table 3.3)
68
The minimization of energy level.
70
3.6
3.7
3.10
3.11
3.12
xiii
3.13
The minimization of congestion level.
70
3.14
The minimization of number of doglegs.
70
3.15
Time taken to achieve optimal arrangement.
71
4.1
Example of a network with random vertices.
74
4.2
Example of a network in rectangular array pattern.
75
4.3
Partitioned layout into N x  N y rectangular array
77
4.4
(a) Routing realization with bad net ordering.
(b) Routing realization with better net ordering.
80
4.5
Routing region of size 8  8 .
87
4.6
#Connections at all iterations for N  4.
90
4.7
Energy level improvements among R  6.
91
4.8
(a) #Connections at all iterations.
(b) #Connections among all acceptable moves.
92
The algorithm gradually decreased the energy level
for R  22.
93
4.10
#Connections at all iterations in the second layer.
94
4.11
Minimization of energy level.
94
4.12
Final wiring tracks on each layer using simulated annealing
for p  8.
95
Maximization of R using simulated annealing and greedy
method.
95
Minimization of E using simulated annealing and greedy
method.
96
4.15
Detours in obstacle-aware shortest path problem.
97
4.16
Routing in layout of size 9  9 with the presence
of obstacles.
98
4.17
Placement of obstacle in 7  7 routing network.
99
4.18
(a) Placement of obstacles.
(b) Number of connections versus iterations no.
100
4.9
4.13
4.14
xiv
4.19
(a) Placement of obstacles.
(b) Number of connections versus iterations no.
101
(a) Route shortest path first.
(b) Route longest path first.
102
(a) Maximization number of R among four cases with
increasing obstacles placement and net requirement.
(b) Minimization of E for all cases.
103
5.1
Mesh network topology.
110
5.2
Torus network topology.
110
5.3
A six-degree node in SD-Torus network.
111
5.4
SD-Torus interconnection network.
112
5.5
Network diameters for mesh network.
113
5.6
Example of the longest shortest path in torus network
with odd and even number of nodes.
114
Example of largest hop count in SD-Torus is when
connecting node 8 with node 29.
114
5.8
Number of communication links in an n  n mesh network.
115
5.9
Number of wraparound links in torus.
116
5.10
Calculation of diagonal links and diagonal wraparound
links in SD-Torus.
117
5.11
Simulation results for 6  6 network size
125
5.12
Simulation results for 8  8 network size
125
5.13
Number of R over 8  8 torus and SD-Torus network
126
5.14
Number of R and E over 6  6,8  8 and 10 10 SD-Torus
network.
126
Number of R and E over 1111 and 12 12 SD-Torus
network.
127
4.20
4.21
5.7
5.15
xv
LIST OF TABLES
TABLE NO.
TITLE
PAGE
3.1
All possible routings for n  4 .
59
3.2
Net ordering for n  6.
60
3.3
Single-row routing realizations for n  6.
63
3.4
Inductive relationship for orders of pins up to n  20.
64
3.5
Generating list L for n  20 at ten different time slots.
69
4.1
Calculation for maximizing R.
88
4.2
Calculation of energy level in a routing region.
89
4.3
Input data for problem size 4  4.
90
4.4
Input data for problem size 8  8.
91
4.5
Remaining nets to be routed in the second layer.
93
4.6
Calculation of R and E in p  4 routing region.
99
4.7
The whole result.
103
5.1
Pros and cons for bus-based architectures and
NoCs [142].
106
5.2
Topological properties comparisons.
118
5.3
Calculations for maximizing R in mesh network.
121
5.4
Calculations for maximizing R in torus and SD-Torus.
122
5.5
Calculations of energy level in mesh network.
123
5.6
Calculations of energy level in torus network.
123
xvi
5.7
Calculations of energy level in SD-Torus network.
123
5.8
Simulation results for 4  4 network size with random
data.
123
The whole result.
128
5.9
xvii
LIST OF SYMBOLS
Nx
-
Array of mesh-connected processors in x -axis.
Ny
-
Array of mesh-connected processors in y -axis.
R
-
Successful routed nets.
aij
-
Matrix representing sequence number and nets.
m
-
Total number of nets.
i
-
Sequence number.
j
-
Nets.
E
-
Energy.
d ij
-
Total number of communication links used to connect source
and target node.
Ni
-
Net i .
Nj
-
Net j .
Q
-
Level of congestion.
Qu
-
Upper street congestion.
Ql
-
Lower street congestion.
D
-
Interstreet crossing or dogleg.
A
-
Adjacency matrix.
x
-
Eigenvector of A .

-
Eigenvalues of A .
I
-
Identity matrix.
Ts
-
Spanning tree of Gs .
T
-
Temperature.
Li
-
Netlist.
xviii
Tk
-
Temperature.
Si
-
Source node.
Ti
-
Target node.
p p
-
Network size.
xix
LIST OF APPENDIX
APPENDIX
1
TITLE
Publication / Presentations in Journals / Conferences
PAGE
148