Implant Dose Sensitivity of 0.1µm CMOS Inverter Delay
H. C. Srinivasaiah and Navakanta Bhat
ECE Department, Indian Institute of Science, Bangalore−560 012, India
e−mail:srinivas@protocol.ece.iisc.ernet.in or navakant@ece.iisc.ernet.in
Abstract
The simulation experiment is performed to characterize
the impact of process level fluctuations on the circuit
performance variation for the 0.1µm CMOS technology.
The 0.1µm NMOS and PMOS transistors are optimized
using four different ion implantation steps namely super
steep retrograde channel (SSRC) implant, deep s/d
implant, shallow s/d extension implant and halo implant.
We demonstrate that the fluctuations in the nominal
values of these implant doses result in the significant
variation in DC (Ioff, Ion, Vt) and AC (Cgg) parameters of
the transistors. The DC and AC parameter variations of
these devices in turn have their effect on the performance
of the inverter circuit. In particular, the halo implant has
the maximum impact resulting in ∆Ioff=122% (97.48%)
and ∆Ion=4.82% (5.29%) for NMOS (PMOS) transistor.
The worst case delay variation is more than ±10% for a
±10% random variation in the implant dose parameters.
1. Introduction
With the down scaling of MOSFET dimensions in the
Deep Sub−micron (DSM) technology, the device and the
circuit parameters are strongly nonlinear function of the
process parameters [1]. The fluctuations in the process
parameters have impact on the performance of the
circuit and on the manufacturing yield. The transistor
parameter fluctuations is caused by intrinsic and extrinsic
process parameter variations [2, 3, 4]. The intrinsic
variation includes random dopant number in the channel,
interface state density, etc. and the extrinsic variations
includes random variation in gate oxide thickness,
channel length, implant dose etc. [2]. In the DSM
technology, the increasing difficulty of improving
manufacturing tolerance leads to the greater relative
variation of the device parameters around the nominal
technology point. In order to relate the process level
fluctuations, to the circuit level fluctuations (delay
fluctuation in the critical path), various statistical
techniques are followed with different accuracy and
complexity [1]. Here we have used the simplest approach
of identifying the worst case corners (±3σ). One can
Proceedings of the 15th International Conference on VLSI Design (VLSID’02)
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relate the circuit delay fluctuation to some of the
important SPICE parameter fluctuation using Monte−
Carlo circuit simulation as,
∆τ = f1( ∆vt0, ∆γ, ∆Cj, ∆Tox . . .)
where "f1" is a function to be determined by experiment,
τ=circuit delay, vt0=threshold voltage, γ=body effect
factor, Cj=junction capacitance, Tox=oxide thickness and
∆ indicates the fluctuation around the nominal value.
However each of these SPICE parameters are controlled
by multiple process parameters as,
implant energy, anneal
vt0 = f2(implant dose,
temperature, oxidation temperature. . .),
implant energy, anneal
γ = f3(implant dose,
temperature, oxidation temperature. . .) and
Cj = f4(implant dose, implant energy, anneal
temperature, oxidation temperature. . .)
where "f2, f3 and f4 " are functions to be determined by
experiment. In other words it becomes impossible to
relate circuit level fluctuations to the underlying
processes.
In [5] an approximate functional relationship between
process level to device level parameters has been
established for 0.18µm technology, by the technique of
statistical design of experiment. There are no generalized
techniques to relate process level to circuit level
fluctuations, applicable to all technology nodes, because
of the strong nonlinearity that exists between process and
circuit parameters in DSM regime [1]. This relationship
becomes necessary in DSM regime to guide process
engineering with respect to process control. We propose
to perform mixed mode simulations which bring the
process simulated devices directly into the netlist of a
circuit wherein both circuit and device equations are
solved simultaneously. This technique bypasses
parameter extraction for the process simulated device. It
is the mixed mode simulation technique that we have
followed to characterize the delay parameter of an
inverter chain. One can develop a functional relationship
between circuit and process parameter by an appropriate
choice of the design of experiment. For example: delay
fluctuation, ∆τ can be related to the process as,
∆τ = f(∆implant dose, ∆implant energy, ∆anneal
temperature, ∆oxidation temperature. . .) where "f" is a
function to be determined by experiment.
We have designed and optimized a "nominal"
0.1µm gate length NMOS and PMOS transistors
using disposable spacer
technique. The transistor
performance variations are characterized as a function
of the variations of the different implant doses around the
nominal value. The two stage inverter circuits
corresponding to nominal (C0), worst (C1) and best (C2)
case process corners of the NMOS and PMOS transistors
are simulated in mixed mode to assess the impact on
circuit delay.
Table 1: The process sequence for the nominal
NMOS and PMOS device, D0 with
important process parameter values.
(Quantities in brackets are for PMOS
device).
2. Transistors Design Methodology
In realizing our devices, we have used standard TCAD
tool from ISE (Integrated System Engineering) which has
the process simulator DIOS−ISE and device simulator
DESSIS−ISE. In simulating the I−V characteristics of the
transistors, Hydrodynamic model has been used to
account for the velocity overshoot, Vandort’s model has
been used to account for carrier quantization in the
channel [6].
The short channel effects in our 0.1µm transistor are
suppressed with pocket halos, super steep retrograde
channel and shallow source drain (s/d) extension. The
process steps and the important parameter values for our
nominal device are listed in Table 1, with the four
implant steps being highlighted. Both NMOS and PMOS
devices are optimized for Ioff=1.0 nA/µm and Ion for
NMOS is 0.954mA/µm and that for PMOS is
0.397mA/µm in the saturation region (Vd=1.5V). Process
simulated two dimensional cross sections for both NMOS
and PMOS are shown in Figure 1.
3. Design of Experiment
The four highlighted parameters in the Table 1 are
varied ±10% from that of NMOS and PMOS nominal
devices (D0). This results in total of 8 devices (D1−D8).
Further we have included two more devices (D9 and D10)
for both NMOS and PMOS, for the worst case current
fluctuations corresponding to simultaneous variations in
all the implant steps. The device label definitions are
given in Table 2. Devices D1−D10 are process simulated
for both NMOS and PMOS devices by DIOS−ISE. For all
these devices DC and AC characteristics are extracted by
DESSIS−ISE. The relative deviation of any parameter x,
about its nominal value xnom is calculated as ∆x=(x−
xnom)/xnom.
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Process Steps and Parameter values
1.
In(Sb) SSRC: 5.7×1012 cm−2 /180 keV
(5.7×1012 cm−2 /200 keV)
2.
20 Å Gate oxide @ 800o C.
3.
4.
0.1µm Gate Poly thickness.
2 nm Poly−reoxidation @ 800o C.
5.
96 nm Disposable Nitride spacer.
6.
As(B) s/d: 6×1015 cm−2 /30 keV (1×1015 cm−2 /
5 keV)
RTA: 1050o C, 20 sec.
Etch the 96 nm disposable spacer
7.
8.
9.
As (B) s/d extension:1×1015 cm−2 /7 keV
(1×1014cm−2 /1.0 keV).
10.
B(P) Halo:30o/6.65×1012 cm−2 /10 keV
(30o /5.85×1012 cm−2 /25 keV).
11.
Final RTA: 1050o C/4 sec.
12.
13.
Deposit 40 nm final spacer.
Cobalt Silicidation and Al metallization.
Table 2: Device label definitions( − and + signs
correspond to 10% decrease in dose and
10% increase in dose respectively)
Devices
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
Definitions
nominal
Halo−
Halo+
SSRC−
SSRC+
Deep s/d implant−
Deep s/d implant+
s/d extension implant−
s/d extension implant+
Simultaneous deviations in the implant
parameters causing decrease in the currents.
Simultaneous deviations in the implant
parameters causing increase in the currents.
Doping Conc.
/cm3
+2.792e+20
+1.922e+19
+1.323e+18
+9.110e+16
+6.272e+15
+4.260e+14
-5.436e+13
-1.219e+15
-1.774e+16
-2.577e+17
-3.743e+18
(a)
Corresponding to a 10% deviation in implant dose,
percentage deviations in DC parameters (Ioff, Ion and Vt
in the saturation region) are tabulated in Table 3 for both
NMOS and PMOS devices. It can be seen that the halo
implant step has the biggest impact on the variations,
suggesting that this step has to be very tightly controlled
in manufacturing.
Figure 2 shows the Id−Vg
characteristics for the nominal device (D0) and the worst
and best case corner devices (D9 and D10) for both
NMOS and PMOS.
The AC extractions are performed at 100kHz over the
full range of gate voltage from 0−1.5V. Figure 3 shows
the Cgg−Vg characteristics for D0, D9 and D10 for both
NMOS and PMOS devices in the saturation region. The
percentage deviation in Cgg is tabulated in Table 4 and 5
in linear and saturation region for both NMOS and PMOS
devices respectively. Both halo and SSRC implants are
important in controlling the capacitance value. The
variation in the gate capacitance Cgg is typically lower
compared to the variation in DC parameters, since the
gate capacitance is mainly dominated by the oxide
thickness. However, for the accurate prediction of CMOS
circuit delay, the CV/I metric is affected by the
capacitance variations as well.
Table 3: Percentage deviation in DC parameters
in the saturation region for both the
NMOS and PMOS devices.
Doping Conc.
/cm3
+2.891e+18
D1
D2
D3
NMOS NMOS NMOS PMOS PMOS PMOS
∆Ioff
∆Ion
∆Vt
∆Ioff
∆Ion
∆Vt
Vds=
Vds=
Vds=
Vds=
Vds=
Vds=
1.5V
1.5V
1.5V −1.5V −1.5V −1.5V
122
4.82 −13.55 97.48
5.29 −10.29
−52.7 −5.66 11.6 −47.2 −4.53 10.66
33.3 −2.41 −5.16 74.76
11.1 −9.84
D4
D5
D6
D7
−16.85 −5.03
−7.03 −1.36
7.87
1.26
−23.15
−2
2.58
1.29
−1.94
2.58
30.49
−23
33.7
−26.9
6.95
−3.02
3.02
−4
−5.74
6.1
−5.15
6.19
D8
D9
28.7
−71.3
2
−13.1
−4.52
19.35
35.83
3.78
−69.9 −11.59
−5.1
20.7
D10 203.52
7.97
−18.71 540.8
Devi
−ces
+1.854e+17
+1.189e+16
+7.589e+14
-2.286e+12
-7.947e+14
-1.244e+16
-1.940e+17
-3.026e+18
-4.719e+19
-7.360e+20
(b)
Figure 1: Cross section of simulated (a) NMOS
and (b) PMOS devices. ( approximate
dopant concentration can be read
from color palette given ).
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24.18 −31.24
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
∆Cgg@
Vds=
0.05V,
and
Vg=0.0V
0.02
0.01
0.53
−0.49
−0.26
0.28
−1.17
1.06
−1.91
1.36
∆Cgg@
Vds=
0.05V,
and
Vg=1.5V
0.05
−0.01
−0.81
−8.07
−1.8
1.21
−0.05
−0.05
−9.21
1.29
∆Cgg @
Vds=
1.5V,
and
Vg=0.0V
−0.15
−0.16
−0.55
−0.84
−0.36
0
−1.57
1.21
−2.17
1.21
∆Cgg @
Vds=
1.5V,
and
Vg=1.5V
0
−0.33
−4.56
7.5
−1
1
−0.58
0
−8.33
0.92
Table 5: Percentage deviation in total gate
capacitance Cgg in the linear and
saturation region for PMOS devices.
D1
D2
∆Cgg @
Vds=
−0.05V,
and
Vg=0.0V
−1.88
−2.86
∆Cgg @
Vds=
−0.05V,
and
Vg= −1.5V
−0.91
0
∆Cgg @
Vds=
−1.5V,
and
Vg=0.0V
0.52
−0.45
∆Cgg @
Vds=
−1.5V,
and
Vg= −1.5V
−0.09
−0.35
D3
D4
1.01
−0.14
−1.66
−2.87
2.41
1.29
0.18
−1.23
D5
D6
−3.03
1.44
−1.66
1.06
−0.69
0.69
−1.59
1.23
D7
D8
−4.76
0
0
0.08
−2.41
2.24
−0.79
0.7
D9
D10
−5.87
5.63
−1.66
0.08
−3.1
6.28
−3.17
2.95
Devi
−ces
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Drain Current Id (Amp/Micron)
Devi
−ces
1E−2
1E−3
1E−4
1E−5
1E−6
D0_PMOS
1E−7
D9_PMOS
D10_PMOS
1E−8
D0_NMOS
1E−9
D9_NMOS
D10_NMOS
1E−10
−1
0
1
Gate Voltage(Volts)
Figure 2: Id−Vg characteristics for D0, D9 and
D10 for both NMOS and PMOS
devices, in the saturation
region
(w=1µm).
Total Gate Cap. Cgg(F/Micron)
Table 4: Percentage deviation in total gate
capacitance Cgg in the linear and
saturation region for NMOS devices.
1.2e−15
1e−15
D0_PMOS
8e−16
D9_PMOS
D10_PMOS
D0_NMOS
D9_NMOS
6e−16
D10_NMOS
−1
0
1
Gate Voltage Vg(Volts)
Figure 3: Cgg−Vg characteristics for D0, D9 and
D10 for both NMOS and PMOS
devices, in the saturation region
(w=1µm)
Vdd
PMOS1
Vout1
PMOS2
Vout2
NMOS1
NMOS2
Voltage (Volts)
Vin
1.5
C_Vin
C0_Vout1
1
C0_Vout2
C1_Vout1
C1_Vout2
C2_Vout1
0.5
C2_Vout2
0
1e−11
2e−11
3e−11
4e−11
5e−11
Time (sec)
(a)
Figure 4: A two stage CMOS inverter Circuit.
4. Transient simulations
Two stage inverter circuit as shown in Figure 4 is
simulated at Vdd=1.5V. According to the circuit label
definition of Table 6, three, two stage inverter circuits
C0, C1, C2 were configured by generating SPICE−netlist
and mixed mode simulated for an input pulse. Input
pulse had a width of 150 ps and rise and fall time of 5 ps.
The output waveforms for all the three circuits, nominal
(C0), worst (C1), and best (C2) are superimposed at the
rising and falling edges of the input pulse as shown in
Figure 5 (a) and 5 (b) respectively. This figure gives a
comparison of delay for all the three circuits in both
rising and falling edge of the input pulse. Various
terminal voltages as defined in Figure 4 alongwith the
circuit label give the identification of the corresponding
curve. Table 7 consolidates the percentage deviation in
delays relative to the nominal circuit, for both the rising
and falling edge for the first stage loaded with an
identical inverter. Significant deviation in the circuit
delay is evident from these results. Also the variations
will get amplified with the complexity of the circuit as is
evident from the difference in the first and second stage
outputs of the inverter chain.
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Voltage (Volts)
1.5
C_Vin
C0_Vout1
1
C0_Vout2
C1_Vout1
C1_Vout2
0.5
C2_Vout1
C2_Vout2
0
1.6e−10 1.7e−10 1.8e−10 1.9e−10
Time (sec)
(b)
Figure 5: Transient waveforms of the two
stage inverter circuit (a) at the
rising edge and (b) at the falling edge
of the input pulse.
underlying processes for the DSM technology. This
would facilitate guidelines for process engineering to
improve the manufacturing yield.
Table 6: Circuit label definitions
Circuit
C0
C1
C2
Definitions
Nominal delay circuit built by device D0
from both NMOS and PMOS
Worst delay circuit built by device D9 from
both NMOS and PMOS
Best delay circuit built by device D10 from
both NMOS and PMOS
Table 7: Percentage deviation in circuit delay
(∆T) parameters. The reference is the
rising or falling edge of the input pulse.
Acknowledgments
We express our gratitude to Prof. T. S. Vedavathy, ECE
department, Indian Institute of Science, Bangalore, for
her support, right through this work. We also thank her
for providing the computing facility, which enabled this
work.
References
1.
∆Tvout1 @
∆Tvout1 @
rising edge falling edge
of Vin
of Vin
Circ
uits
Vout1 delay
@ rising
edge of Vin
(ps)
Vout1 delay
@ falling
edge of Vin
(ps)
C0
8.97
8.35
−−
−−
C1
9.82
9.3
9.48
11.38
C2
7.5
8.02
−16.4
−3.95
2.
3.
5. Conclusions
Among the four implant parameters namely SSRC
dose, deep s/d dose, shallow extension dose and halo
dose, the pocket halo has the significant effect on the
transistor leakage and saturation currents, which finally
have effect on circuit delays. This process step has to be
tightly controlled in manufacturing to decrease mismatch
effect. The device mismatch in turn results in circuit
delay
variation which has implications on the
yield of the circuit. A proper physical model is
necessary to correlate the circuit performance to
Proceedings of the 15th International Conference on VLSI Design (VLSID’02)
0-7695-1441-3/02 $17.00 © 2002 IEEE
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