AN ABSTRACT OF THE THESIS OF
Yihai Xiang for the degree of Master of Science in Electrical and Computer
Engineering presented on Feb. 26th, 1997. Title: Design of High-Speed Adaptive
Parallel Multi-Level Decision Feedback Equalizer.
Redacted for privacy
Abstract approved:
David J. Allstot
Multi-level decision feedback equalization (MDFE) is an effective technique to remove inter-symbol interference (ISI) from disk readback signals, which uses the simple architecture of decision feedback equalization. Parallelism which doubles the symbol rate can be realized by setting the first tap of the feedback filter to zero.
A mixed-signal implementation has been chosen for the parallel MDFE, in which coefficients for the 9-tap feedback filter are adapted in the digital domain by 10-bit up/ down counters; 6-bit current mode D/A converters are used to convert digital coefficients to differential current signals which are summed with the forward equalizer (FE) output, and a flash A/D is used to make decisions and generate error signals for adaptation.
In this thesis, a description of the parallel structure and the adaptation algorithm are presented with behavioral level verification. The circuit design and layout were carried out in HP 1.2um n-well CMOS process. The design of the high-speed counter and the current-mode D/A are discussed. HSPICE simulations show that a symbol rate of
100Mb/s for the feedback equalizer is readily achieved.

Design of High-Speed Adaptive Parallel Multi-Level Decision Feedback Equalizer by
Yihai Xiang
A THESIS submitted to
Oregon State University in partial fulfillment of the requirements for the degree of
Master of Science
Completed February 26th, 1997
Commencement June 1997

Master of Science thesis of Yihai Xiang presented on February 26th, 1997
APPROVED:
Redacted for privacy
Major Professor, representing Electrical & Computer Engineering
Redacted for privacy
Head of Department of Electrical & Computer Engineering
Redacted for privacy
Dean of Graduate Sool
I understand that my thesis will become part of the permanent collection of Oregon State
University libraries. My signature below authorizes release of my thesis to any reader upon request.
Redacted for privacy
Yihai Xiang, Author

ACKNOWLEDGMENT
To my wife: thank you for everything you have done for me. Without your love and patience I would not be where I am today.
With the most respect and gratitude, I wish to thank my advisor Professor David
J. Allstot and Professor John G. Kenney not only for their continuing support and encouragement, but also for their insights and constructive critiques. Without their guidance, this work would not have been possible.
I would also like to thank Professor Sayfe Kiaei and Professor Daniel F. Farkas for taking time to serve on my graduate committee.
Thanks to our group members: Hiok-Tiaq Ng, Hairong Gao, Dan Onu and Priya
Parthasarathy for their help and cooperations. Special thanks to our group leader Hiok-
Tiaq Ng for his dedication to this project and great organizing job.
Thanks to my friends and colleagues Wenjun Su, Bo Wang, Yunteng Huang,
Haiqing Lin, Ravi Guptara, Jianjun Zhou and many others. Thanks for many valuable discussions with them.

TABLE OF CONTENTS
Chapter 1. Introduction
1.1 Background
1.2 Thesis Outline
Chapter 2. Architecture of the Parallel MDFE
2.1 Parallel MDFE
2.2 Adaptation for Parallel MDI-E,
2.3 Parallel MDFE Architecture
2.4 Behavioral Level Verification
Chapter 3. High-speed 10-bit Up/Down Counter
3.1 Logic Design
3.2 Cell and Carry Design
3.3 Interface Design
3.4 Simulation Results
Chapter 4. 6-bit High-speed D/A Converter and Multiplier
4.1 D/A Converter Structure
4.2 Current Source and Accuracy Consideration
4.3 Driver Design
4.4 Multiplier
Page
1
11
13
1
4
7
8
2
4
13
14
17
18
21
21
23
26
29

TABLE OF CONTENTS (Continued)
4.5 Summary
Chapter 5. Results and Conclusions
5.1 Simulations of the Feedback Equalizer
5.2 Layout of the Feedback Equalizer
5.3 Summary
5.4 Future work
Bibliography
Appendices
Appendix A. Mat lab Simulation Code
Appendix B. Layouts
Page
29
32
32
32
35
37
38
40
41
46

LIST OF FIGURES
Figure
1.1 Block diagram of DFE
2.1 Block diagram of MDFE
2.2 Equalized dibit response in MDFE (Symbol density = 3.75PW50)
2.3 Equalized dibit response in MDFE with sampling phase shift
2.4 Architecture of the parallel MDFE
2.5 Timing diagram of the parallel MDFE,
2.6 Behavioral level simulation for the parallel MDFE
3.1 Prototype of the synchronous binary up/down counter
3.2 The proposed T flip-flop
3.3 Simulation results of the proposed T flip-flop
3.4 The proposed carry circuit
3.5 Simulation results of the proposed carry circuit
3.6 Block diagram of the interface structure
3.7 10-bit synchronous binary up/down counter
3.8 Simulation results of the proposed up/down counter (up counting)
3.9 Simulation results of the proposed up/down counter (down counting)
4.1 Basic architecture of current-mode DAC
4.2 Segmented current-mode DAC
14
15
16
16
10
12
6
9
Page
2
4
5
17
18
19
20
20
21
22

LIST OF FIGURES (Continued)
Figure
4.3 Switched current source
4.4 The secondary current array
4.5 Symmetrical layout configuration for the current array
4.6 High-speed driver for current-mode DAC
4.7 Simulation results of the proposed driver
4.8 The current-mode 1-bit multiplier
4.9 HSPICE simulation results of the 6-bit DAC and the 1-bit multiplier
5.1 Schematic of the feedback equalizer
5.2 HSPICE simulation for the feedback loop
5.3 Post-layout simulation for the DAC and the counter
31
33
35
36
Page
23
25
25
27
28
29

Table
2.1 MDFE slicer input levels
LIST OF TABLES
Page
6

Design of High-Speed Adaptive Parallel Multi-Level Decision Feedback Equalizer
Chapter 1. Introduction
This thesis presents the design of a parallel multi-level decision feedback equalizer. The LMS algorithm with delayed coefficient adaptation [1] is modified to accommodate the parallelism. Behavioral level simulation based on a proper timing diagram is used to verify the system. Circuit designs for the major building blocks are discussed in detail. The system has been laid out and is ready for fabrication.
1.1 Background
As massive data storage systems are more and more desired, bit densities on hard disks increase constantly. As a result, inter-symbol interference (ISI) degrades both the signal-to-noise ratio (SNR) and the channel resolution and makes some techniques such as peak detection, one of the first and widely used concepts, no longer able to achieve acceptable performance.
To eliminate ISI, sampling detectors are being used in the read channel [2]. One of them is the decision feedback equalizer (DPE) [1], [3]. Figure 1.1 shows a simplified block diagram of a DFE-based hard-disk read channel. The forward equalizer is used to cancel pre-cursor ISI, while the DIVE uses a linear combination of the past binary decisions to eliminate post-cursor ISI. Since the past decisions are noiseless, this part of the ISI cancellation does not add noise to the slicer input. However, it does suffer from error propagation.

2
Forward
Equalizer r
Slicer
1
I
Digital Outputs
Feedback
Filter
DFE
L
Figure 1.1 Block diagram of DFE
Multi-level decision feedback equalization (MDFE) is a more recent development [4]. The concept of MDFE is based upon fixed-delay tree search with decision feedback equalization (FDTS/DF), while using the simpler architecture of decision feedback equalizer [5]. The major difference of this technique from DFE is that the input to the comparator is a multi-level signal.
1.2 Thesis Outline
The mixed-signal parallel MDFE was designed using 1.2um CMOS technology.
The target symbol rate is 100Mb/s and the circuits are operated using a single 5V power supply. In Chapter 2, the structure and signal processing of the parallel MDFE are described. The timing diagram for the system and the behavioral level verification results are also shown. Chapter 3 discusses the 10-bit up/down counter design where dynamic logic is used to achieve high-speed and small die area. Chapter 4 focuses on the design of the 6-bit high-speed current-mode D/A and the multiplier. Finally, simulation results

3 of the feedback filter, conclusions, and directions for future work are given in chapter 5.
The Appendix includes the behavioral level simulation source code and circuit layouts.

4
Chapter 2. Architecture of the Parallel MDFE
This chapter describes the algorithm and structure of the parallel MDFE. It shows that parallelism can relax the circuit speed to half of the symbol rate. The proposed block and timing diagram is verified by behavioral level simulation.
2.1 Parallel MDFE
MDFE specifically works on 2/3(1, 7) RLL code [4] [5]. This code, which has a minimum run length constraint of 1, disallows input sequences such as '+1 -1 +1' and '­
1 +1 -1'. MDFE depends on the presence of this constraint. Figure 2.1 shows a simplified
Slicer a k
Gc(s)
Figure 2.1 Block diagram of MDFE block diagram of MDFE which is very close to the block diagram of DFE. Gc(s) is a continuous-time low-pass filter serving as an anti-aliasing filter. Fc(s) is comprised of a first-order all-pass filter and a first-order low-pass filter. It equalizes the dibit to the impulse response shown in Figure 2.2. FB is the feedback equalizer which generates a

0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
0 2 4 6 8 10 12
Figure 2.2 Equalized dibit response in MDFE (Sym­ bol density = 3.75PW50)
(Courtesy of Dan Onu) linear combination of the previous decisions; i.e., it convolves the previous decisions with a model of the post-cursor ISI. At the summing node, we get:
X(k) = a(k) Po+ a(k 1) P1+ a(k 2) P2 +
...
2) d1 + a' (k 3) d2 + a' (k 4) d3 + ...
If we assume that the previous decisions are correct, and set the first coefficient of the feedback equalizer d1 = Po
input to the slicer is:
Y (k) = (a(k) + a(k
1) Pi
In 2/3(1, 7) code, the valid input combinations and corresponding Y (k) are listed in Table 2.1
5

6
Table 2.1 MD1-E slicer input levels a(k
+1
+1
-1
+1
-1
-1
2)
+1
+1
+1
-1
-1
-1
1) a(k)
+I
-1
+1
-1
+1
-1
Y (k)
P1
P1
P1
P1
2P0 P1
Decisions
+1
+1
+I
-1
-1
-1
It is obvious that only four levels, namely two inner levels and two outer levels, are valid for the slicer input. Most importantly, the signs of those levels are exactly the same as a(k 1)
, which enables a simple comparator with its threshold at zero to make the decisions.
Further observation of Figure 2.2 shows that by shifting the sampling phase by about T/5, we can set PO equal to P2 [6]. Figure 2.3 shows the equalized dibit response
0 2 4 6 8 10 12
Figure 2.3 Equalized dibit response in MDFE with sampling phase shift (Symbol density = 3.75PW50)
(Courtesy of Dan Onu)

7 with this constraint. In this case, the first tap of the feedback filter is set to zero. Now, we get:
4) d3 + a' (k
...
Since Z(k) can be evaluated without the decision of a' (k 2)
, it's possible for us to construct parallel MDFE.
2.2 Adaptation for Parallel MDFE
In order to achieve the best bit error rate (BER), the coefficients of the feedback equalizer must be adapted to match the post-cursor ISI. The least-mean-square (LMS) algorithm has been successfully used in DFE system to determine the feedback equalizer coefficients [7]. In parallel MDPE, we must wait for one clock cycle to determine whether the inner or outer level the slicer is decoding on, which means that the error signal is not immediately available. Thus the LMS algorithm with delayed coefficient adaptation is used. It has been shown that the delay in coefficient adaptation has only a slight influence on the steady-state behavior of the LMS algorithm
adaptation step is small [1]. The Delayed LMS (DLMS) minimizes the mean square of
1) = a' (k
.
Once the MDFE has adapted, then do = 1)
1 for 2
_. .
I 1 M
With the optimal coefficients, the feedback filter will cancel significant post-cursor ISI.
To simplify the circuit design, the coefficients will be adapted every time an inner level occurs. The coefficients are adapted using [7]: d n(k + 1) = dn(k) + 13 e(k 1 D) a' (k n D) for 2 n S M , and

do(k + 1) = do(k) +13 e(k
1
D)
8
(1) where 13 « 1 is the update gain, k is the time index, D is the delay factor and do is the coefficient of the DC tap which is used to cancel out DC offset in the detector.
The digital circuit complexity can be further minimized by using the sign of the error signal. If we set 13 = 2-L
, where L is an integer, equation (1) can be realized by up/ down counters. System level simulation shows that L = 10 is adequate for steady state and L = 7 enables fast convergence.
2.3 Parallel MDFE Architecture
Figure 2.4 shows the architecture of the parallel MDFE in which two detectors work in an interleaved fashion. The timing diagram for this structure is shown in Figure
2.5.
Two non-overlapping clocks, denoted as cI3i and 02, are generated by the timing recovery block. Each clock is running at a frequency of 50-MHz which is half the symbol rate. The output of the forward equalizer is tracked and hold for each detector at a 50­
Mhz rate, where 01 drives the T/H stage of detector one and 02 drives the T/H stage of detector two.
There are ten counters in the system. Each detector utilizes a single counter to
coefficients of the feedback filter. They are divided equally between the two detectors to balance the clock load for (111 and 12
.
Each counter can be initialized or read through the 6-bit data bus. The 4-bit address bus is used to select a specific counter for read/load operation. There is one main delay chain in each detector which stores the previous

'1'
FE
'1'
Differential signal
Digital signal
Figure 2.4 Architecture of the parallel MDFE ic13 I
A/D
Error
Logic
0
1.1 decision
Error
Logic
CD

Phi 1:
CmpOutl :
D1:
Dchain 1 :
Error-1:
Beta -1:
Cnt-1:
Phi2:
K-2
K K+2 K+4 ak_5 ak_5
0 ak_3
0 ak-i .4 ak+1 k-7 ak_5
ak-1
betak_6
40 betak_4
0
4 betak_2
0 betak
K+3 K -1 K+ 1 ek+1
'4 k +1
444
K+5
CmpOut2:
D2:
Dchain2:
Error-2:
Beta-2:
Cnt-2: k+2 ak+2 ek-6
04 betak_5
04 betak_3
'.4 betak_i
04 ek+2 betak+l
4111111111111111111411111111111114=11111111111.4
Figure 2.5 Timing diagram of the parallel MDFE,
0

11 decisions made by the same detector. The other delay chain is used to store the previous decisions made by the other detector. In each detector, nine DAC's convert the digital coefficients from counters into differential currents. Those currents are multiplied by previous decision values and added to the output of the forward equalizer at the summing node. After the output of the summing node settles, the slicer, which is replaced by a flash
A/D, starts to make a decision, and at the same time, generate the error signal for adaptation. Inner levels are found when a' (k 2) = a' (k) and signal BETA is set to enable adaptation. For each counter, control logic decides based on the error signal and the previous decision whether it should increment or decrement.
From the timing diagram, it is easy to see that signal BETA comes up after the corresponding error signal by one symbol delay. So, the delay factor, D, in equation (1) is one for our case.
2.4 Behavioral Level Verification
The architecture of the proposed parallel MDFE is verified by behavioral level simulation. In this simulation, each register or counter has its own variable and the evaluations are done sequentially based on the timing diagram; thus, it can closely imitate the behavior of the real system.
Figure 2.6 shows the simulation results for the parallel MDFE. The slicer inputs for several conditions, i.e. with/without ideal initial setup, with/without DC cancellation and with/without additive random noise, are plotted. It is shown that even in the presence of random noise and without initial settings for the coefficients, the slicer inputs converge to the four desired levels which demonstrates that the proposed architecture functions as expected.

500 1000 1500 a) Simulation with preloaded coefficients, without adaptation
0 500 1000 1500 b) Simulation without initializa­ tion and DC tap
500 1000 1500
without initialization
500 1000 1500 d) Simulation with noise (SNR =
25dB)
Figure 2.6 Behavioral level simulation for the parallel MDFE (plots of the slicer inputs)
12

13
Chapter 3. High-speed 10-bit Up/Down Counter
The design of a high-speed 10-bit up/down counter is discussed in this chapter.
In order to adapt the coefficients once per clock cycle, a synchronous configuration is chosen to achieve high speed. Dynamic logic design greatly reduces die area and further improves speed performance.
3.1 Logic Design
Based on the system level design requirements, specifications for the counter are:
10 bits
100-Mhz clock rate (clock synchronized)
Up/down counting modes
Different counting steps
Load/read function
Based on the specifications, a prototype of the up/down synchronous counter is chosen from [8]. Figure 3.1 shows its simplified logic diagram. In this prototype, the carry bit is generated by AND-OR gates. The fan-in for the AND gate increases linearly as the length of the counter increases. The carry for the MSB of a 10-bit counter will have two 11-input AND gates which are too complex and slow to be implemented by CMOS complementary logic. Therefore dynamic logic is adopted for the carry design. Since the output value of a dynamic logic gate might change twice (pre-charge and evaluate) in one
to avoid malfunction, which excludes some simple high-speed designs such as true single phase logic (TSPL) [9] [10].

Reset
Set
Clock
T
R
Q
T
Rd
Q
Q
Figure 3.1 Prototype of the synchronous binary up/down counter
QO
Q1
Q2
14
A straight-forward method for the counter to count by eight instead of by one is to disable the three LSB's. However, the carry chain has to be changed to that of a 7-bit counter. In our design, the three LSB's will be set to high (low) during every evaluate phase when the counter counts up (down). Thus, the carry-in bit for the fourth LSB will be set to high for each clock cycle and the counter will behave as a 7-bit (7 MSB's) one while the carry chain remains unchanged.
3.2 Cell and Carry Design
In some D flip-flop or J-K flip-flop designs [11], the T flip-flop is triggered by the rising edge of the T signal instead of the clock signal. A design which meets our requirement is shown in Figure 3.2. In this circuit, by taking advantage of the presence of both Q and Q and providing both T and T , a simple XOR gate will be able to generate the next state for the T flip-flop. Transmission gates driven by clock signals are used to

15
D
Figure 3.2 The proposed T flip-flop synchronize the state transitions. Set or reset signals enter through the D port while the output of the XOR gate is blocked by the transmission gate. Again, dynamic design reduces transistor counts and improves speed performance. Figure 3.3 gives the simulation result for the proposed T flip-flop which shows that it can operate at 250
MHz.
As mentioned above, the carry is designed using dynamic logic. For an AND gate, there may be as many as 11 PMOS transistors in parallel. Since a PMOS transistor has smaller Gm than an NMOS transistor, larger size for the PMOS is usually required to achieve certain speeds. This also increases clock load which is not desired. However, noticing that most inputs of one AND gate are exactly the inverting version of the inputs of another AND gate, we can use complementary logic, namely, an OR gate to realize the same logic function without additional cost (extra inverters). Thus the total gate area as well as clock load are reduced. An OR gate based carry circuit is shown in Figure 3.4.
Its worst-case simulation result is shown in Figure 3.5.

AID
DI
D mCo
00 mD mC> mD
^4,
C>
C>
PE
C>
GE
D mC>
C, cup
16
0
L
T
L
V
0
L
T
L
1,1
V
0
L
T
L
5_0 _
DAWET OUTPUT FILE /HOME/xIAWGII/MDFE/CWT/HIx_TFF.SP,
97/02/11 19100!47
4.0 =
3_0 1-­
...
2.0
1
. 0
MIx_TFF.TPO
CLK
0.
5_ _
I
1 =
MIx_TFF.TPO
CK
4.0
3.0=
2.0
1 .
0_
:1
J
I 0
5_0=
L
4.0= in
4- AT
3_0
1
2 _ 0
. 0 =
I
I
1 t
L i
--f
0 . a-1-0-1--1-i-4.-1-1-L--0-
.1-1-
O.
5.0W 10.0W 15.0W
..-4 ,--.1,
20.0W
TIME CLIW3
,
-1..-1 , L..11
25.0V '30.0W' '35.014
40.0W lipx_TFF.TPO
Figure 3.3 Simulation results of the proposed T flip-flop
D SS
Figure 3.4 The proposed carry circuit

17
O
L
T
V
0
L
T
4.0
r DAWET OUTPUT FILE ,/HOME/XIAMGY//MDFE/CMT/O_CPI9.5Ps
97/02/12 11119146
2 0
0_
4.0
2
J
5.5944
4.0
O_CP19.TPO
CLL
:
_1?CP19.TPO
_
Pffk.TY_ 2:4-ER
XCPY_M_690 y
T
L
5 2370
0.
0_
5.0M
1
.­
TIME
10. OW
CLIWI
15.0W
20.0M
D_C P19 TR 0
CRY
C P15
Figure 3.5 Simulation results of the proposed carry circuit
3.3 Interface Design
In order to test the parallel MDFE chip, each counter should be readable and loadable. Figure 3.6 shows the interface structure for the counters. a 6-bit I/O data bus and a 4-bit address bus are designed to facilitate the read/load operation. Each counter connects to the data bus through two sets of transmission gates. Bus drivers are used to enhance the counters' driving ability. When one of the counters is to be accessed by inputting its address, one set of transmission gates are turned on based on the state of
Read/Load signal. The selected counter is then ready to be read or loaded.

Data bus
6-bit
Address bus
(1.)
-0
O
C.) a)
ICI
Load
Driver
Load/Read
Figure 3.6 Block diagram of the interface structure
I/O
18
3.4 Simulation Results
The circuit of a 10-bit up/down counter is shown in Figure 3.7. There are four control signals in this circuit: The ENBL signal is used to enable/disable the counting function. If it is set to low, the counter will stay in its current state; The STARTUP signal is used to shift the counter between 10-bit counting mode and 7-bit counting mode; The
LOAD signal enables/disables loading data into the 6 MSB's of the counter; Finally, the
UP/DOWN signal tells the counter to count up or count down. Simulation results are shown in Figure 3.8 and Figure 3.9 for counting up and counting down, respectively. In both cases, the counter was preloaded with '110101' for the 6 MSB's. An operating speed of 160-MHz is achieved for the proposed counter.

STARTUP
! r
-!
LOAD ­
'
NI
.
ENBL
-:
11.
.­
UP
CLK
CLKb imal a a a a aa a
1.
.
.
.
.
..
a a
1. a
.
.
_
Figure 3.7 10-bit synchronous binary up/down counter
_--,

0
L
T
L
H
0
L
T
Li
H
* DRWET OUTPUT FILE ,/HOME.exIAW0II/MDFE/EWT/CWT_109.5P5 *
97/02/12 11143100
4_0
......
2.0
0
L
T
Li
H
0.
5_2639
.0
2.0
0
L
T
O.
5.2156
4.0
.......
AL.
CWT_108.TPO
ICCLK a
IC LORD
CMT_108.TPO
v[01 v[02
V103
1
I
-
CMT_109.TPO
v[04 v[05 v(06
2.0
H
.1
I.
4
CWT_108.TPO
v[07
4.0
2.0 v[09
O.
O.
10.011
.
.
20.01J 30.01J
TIME CLIIJ)
4 0 . i
50.011
60.011
Figure 3.8 Simulation results of the proposed up/down counter (up counting)
20
0
L
T
4
* DAWET OUTPUT FILE /1401.1E/xIAWGYI/HOFE/CWT/CWT_100.OP,
*
97/02/12 11:52119
1
..........
0 =-­
CWT_109.TP0
vCLORD
2.0
H v
0
L
T
L
I
14
V
0
L
T
L
5.2909:
4.0
2.0
O.
5.2270::
_
4.0
2.
11
0
5_0820
4.0
T
2.0
0.
O.
10.0W 20.0W 30.0W
TIME [LIN)
40.0W
-
C14T_109 _TRO
5(01 v(02
5100
CAIT_IOR_TPO
5104
A v[05 v103
-
CWT_1013.TPO
5107 v[09
V(00
50.0W
E. 0 . OH
Figure 3.9 Simulation results of the proposed up/down counter (down counting)

21
Chapter 4. 6-bit High-speed D/A Converter and Multiplier
Current steering is an important concept which is often used in high-speed circuit design. In this chapter, a 6-bit current-mode D/A converter is designed which achieves a
200-MHz conversion rate. A current-mode single-bit multiplier is also designed for multiplying the DAC outputs by the previous decision values.
4.1 D/A Converter Structure
Recently, the weighted current array or current matrix technique has been widely used in designing high-speed CMOS DAC's [12]-[15] to allow fast and accurate settling.
Figure 4.1 shows the basic structure of a binary weighted current-mode DAC. Weighted current sources are switched between two output loads according to the value of the input bits which control the output voltage of the drivers to the source-coupled current switches. There are two major drawbacks of this basic structure. First, parameter
Differential current output
I­
IMSB-1
=
GND
IMSB
GND
=
GND
Figure 4.1 Basic architecture of current-mode DAC

22 gradients across a wafer and random mismatches of current sources result in large variations in the performance of the fabricated DAC's. Second, 2n
1 equally sized
CMOS current sources are required for a n-bit DAC. Thus both wiring and switching complexity and silicon area are increased significantly. Large area also makes the mismatch error among current sources more serious.
The local matching technique and threshold-voltage compensation have been used to overcome the linearity errors caused by threshold-voltage gradients over a wafer
[15]. However, extra circuits and power are usually needed. Another approach is the segmented technique where the input bits are divided into several groups [13][15]. The current sources are binary weighted only in each group and the currents from different groups are summed together at the output node according to different ratios. A 6-bit
Secondary current cells
Primary current cells
=
GND
Figure 4.2 Segmented current-mode DAC segmented current-mode DAC is shown Figure 4.2. In this approach, a primary current array is used for the 3 MSB's and a secondary current array is used for the 3 LSB's. Thus only 8 primary and 8 secondary equivalent unit current sources are required for a 6-bit
DAC. The 8 secondary unit current sources are automatically scaled to one eighth of a primary current source as long as they equally divide the primary current source. In this structure, no accurate current mirror which is hard to design and consumes extra power

23 is required to sum the currents from two segments as in [13]. Since only 16 current sources are required, it is much easier to achieve compact layout for the DAC, which reduces the gradient mismatch among current sources.
4.2 Current Source and Accuracy Consideration
A switched current source is shown in Figure 4.3 where a cascode current source is used to increase the output impedance. Transistor M2 is designed smaller than M1 to reduce the output node capacitance without having much effect on current source matching. As mentioned above, the linearity of the DAC is mostly determined by the
OUTN OUTP
BIAS2
D
INP
D
BIAS I
AVSS
Figure 4.3 Switched current source
INN matching of the current sources. If channel-length modulation is neglected, the current I can be expressed as:
=
K W
(V gs V th)2

24
K' = P-nCox where p.ti is the surface mobility, C is the channel oxide capacitance per unit area, W is the channel width, L is the channel length, and Vth is the MOS threshold voltage. If we assume that all random variables are uncorrelated, the variance of the output current is
[12]:
02 02 rT2
I
IC' W
/2 K W
2 ai d
L2
02
(V gs th
)2
For the right side of the above equation, the first term gives a negligible contribution.
Since the current source in our circuit is realized as a parallel connection of many equal elementary sources with nominal current i = I/n, the variation of W and L due to fluctuations of the photolithographic process, are reduced by a factor of n. Thus the second and third terms are also negligible. From the above analysis, we know that current mismatch is mainly due to threshold variations. Specifically, the relative current error due to the threshold variation AVth equals 2 A Vth/( Vgs Vth)
.
In our case, there are only 16 current sources in a 6-bit DAC and the maximum output current is about 200 uA.
It is reasonable to assume that all current sources are closely matched where the threshold mismatch is as low as 3 mV. For the worst case, to limit the current mismatch for the
MSB whose nominal value is 2n-ILSB to under 1/2 LSB, the overdrive voltage
( Vgs Vth) must be larger than 2n + I Mith. In our design, ( Vgs Vth) is set to about
430 mV.
Figure 4.4 shows the circuit for the secondary current array. The Vds of M1 is slightly higher than that of M1 in Figure 4.3 due to the replacement of the cascode transistor by 8 transistors in parallel. To avoid the current error caused by channel-length

25 modulation effects, the M1 transistors are designed to be long channel devices. This also improves matching of the current sources.
Figure 4.4 The secondary current array
The mismatch of current sources due to linear parameter gradients can be further reduced by a symmetrical layout as shown in Figure 4.5. The basic idea is that by symmetrically distributing the unit current sources that form each single bit across the line, the gradient errors of different current sources should be odd symmetrical and cancel when summed together.
BIT2 BIT1 BITO
® ®
Figure 4.5 Symmetrical layout configuration for the current array

26
4.3 Driver Design
In order to achieve high switching speed, several aspects must be taken into consideration: a) The differential current switches should not be turned off or on simultaneously.
If the differential switches are turned off at the same time, the common source node of the differential switches will be rapidly discharged toward ground while the output node of the DAC will be charged toward the power supply voltage. It takes time for the following operation to recover from this status. On the other hand, if the differential switches are turned on simultaneously, the tail current will be split between two differential switches which is not desired. This also increases the settling time of the
DAC. To meet the above requirements, we paid special attention to the crossing point of the rising/falling waveforms of the driver outputs. The ideal cross point should be higher than the middle of the output swing where the current of each side is half of the tail current. b) The driving waveform should be clamped to the minimum allowable voltage for the following reasons: First, extra voltage swing will slow down the switching operation due to the continuous charging and recharging of the common source node of the differential switches. Second, it takes more time to charge and discharge the driver output nodes with high voltage swing. And finally, extra voltage swing creates more feedthrough noise. The minimum overdrive voltage is determined by:
2/
L ifMSB
IC' W
In order to ensure a complete switching operation, the actual minimum waveform swing
AV is about 200-300 mV higher than V0,
.

27 c) The transition time of the driver outputs should be small and the waveform should be symmetrical.
Another important performance parameter of a DAC is the transient differential nonlinearity (glitch). To reduce the DAC output glitches, the differential switches for different bits should switch at the same time and at the same speed. Thus the digital inputs for the drivers should be synchronized and the driver sizes should be scaled based on their load capacitances.
It is difficult to design a driver which meets all requirements stated above. Some trade-offs have to be made based on the specific application. In our case, the DAC is designed for a sampled system. Hence output glitches are of no concern as long as the output currents settle before the sampling instant.
A high-speed switch driver is given in Figure 4.6. In this circuit, transistors M3 and M4 are cross coupled forming a positive feedback loop. Complementary digital
VDD
MI M2
1=> OUTN
1=> OUTP
M3 M4
INP
BIAS P
M5
M7 LI M9
..=
GND
Figure 4.6 High-speed driver for current-mode DAC

28 signals are applied to the gates of M5 and M6 which trigger the positive feedback. Thus the transition time of the output waveform is greatly reduced. The output swing is determined by adjusting the geometric ratio of the input pairs, the cross coupled transistors, and Mg. The transistors M7 and M9 are used to adjust the output level. Since only NMOS transistors are used in the driver design, it is less sensitive to process variations.
Simulation results of the proposed driver are shown in Figure 4.7. The driver was loaded by one unit current sources during the simulation. The output waveform has a transition time of 1.5 ns and a voltage swing of about 0.8 V which ensures that one of the differential switches is completely off and the other one drives all the current.
5.0
* ORNET OUTPUT FILE ,IHOME/xIANGYI/MDFE/D5E/682.SPI
97,02/12 13 50:59 r
4.50 :
4.0 :
3.50
0
L
V
0
T
L
I
2.50 :
2.0:
1.5D:
1.0;
500.0M
0.
3.20
3.10,
3.0,
2.9D,
2.90:
2.70
2.60­
2.50
0.
5.0N 10.04
-, -r41
15.0N
TIME OLIN)
20.0N
-r­
=
612.100
INN
= A
= IMP
612.TPD
OUTW
_ A
OUTP
25.0N
29.ON
Figure 4.7 Simulation results of the proposed driver

29
4.4 Multiplier
In the parallel MDFE, the coefficients of the feedback filter are multiplied by the previous decision values. Since the previous decisions are a sequence of +1 and -1 values, the multiplication can be done simply in the analog domain. Actually, two pairs of cross coupled differential switches (Figure 4.8) work as a multiplier by swapping the differential currents which are generated by DAC.
OUTN OUTP
IINN
A
AVSS
Figure 4.8 The current-mode 1-bit multiplier
IINP
4.5 Summary
In this chapter, the design considerations for a high-speed segmented currentmode DAC are discussed. It is shown that the driver of differential switches and the

30 current source matching are two critical parts of the design. The design also benefits from the segmented structure which reduces the number of unit current sources from 63 to 16 for a 6-bit DAC.
The simulation results for the DAC and the multiplier are given in Figure 4.9. It
nonlinearity (DNL) and integral nonlinearity (INL) are less than 0.1 LSB. The power consumption is about 4.5 mw with maximum differential output currents of 200 uA.
O
L
5 0
4.50
4.0
3.50 =
3.0f
2.50
2_0 =
1 _50
1.0
500_ OH
104.0U
102.0U
100.00
99.00
95.00
94.0U
92.0U :
0.
DAWET OUTPUT FILE </HOME/KIA14GII/HOFE/D2C/D2C.5P1,
97/02/14 22122111
5.014
11_111.
1 1
10.0W
1
15.014
TIME CLI143
I. 20.0W
1.
4
5
=
DAC HULT_TRO
OW
25.014
27.014 a) Differential current output of the proposed DAC for small step case

31
V
0
L
5.0
4_50
* DAWET OUTPUT FILE 1/HOME/xIANGII/MDFE/DAC/DAC.SP1,
*
97/02/14 23:09:23
4.0
=
3.50
3.0
2_50
2 0
1 _50
1.0
500.0M
0_
225.0U
200.0U
175.0U :
150.0U :
125.0U :
100.0U
75.0U :
50.0U
25_0U :
D. :
J.
.......
1 rN
0 ­
2.50W
5 .0
7.50W
TIME (LOW)
10.0W
=
12.50W 15.0W
17.0W
DAC_MULT_TPO
IM
_
=
EIGAFINULT.TPO
A I
I C
M2 b) Differential current output of the proposed DAC for large step case
V
0
L
T
L
5.0
1
DAWET OUTPUT FILE /HOME/xIAWGrI/MDFE/DAC/OAC_SPI, *
97/02/14 23122111
4.0
3.0
2.0 =
1.0 ­
111
P
133.364U
120.0U
100.0U
!Ns,
0 DAC_MULT_TPD
=
=
IN
A
IWP es,
10
DAC_MULT_TRO
Irvil 1
ICvM2
90.0U
P
60.0U
137.654U
120.0U
100.0U _
90.0U nnultiplier outputs (\ E lin48YVT"
I C v HOU T
5 .
20.0W 25.0W
27.0W 0.
II
II
10.0W 15.0W
TIME (LIN) c) Simulation for the proposed multiplier
Figure 4.9 HSPICE simulation results of the 6-bit DAC and the 1-bit multiplier

32
Chapter 5. Results and Conclusions
The feedback equalizer of the parallel MDFE has been designed using the circuits presented in the previous chapters. The critical timing path has been verified by Hewlett-
Packard transistor level simulations, and the layout of the equalizer has been completed using the 1.2-urn CMOS technology.
5.1 Simulations of the Feedback Equalizer
The feedback equalizer of the parallel MDFE has been designed based on the architecture shown in Figure 2.4. A 6-bit latch is added to each DAC to sample and latch the counter outputs during each clock cycle. The load/read circuitry for the counters including data bus, address bus and decoder are also added to facilitate chip testing. The
ENBL signal is used to fix the counters by setting it to low. Therefore, the adaptation is disabled and the feedback equalizer will use the preloaded coefficients. The STARTUP signal is used to change the adaptation speed. The schematic of the feedback equalizer is shown in Figure 5.1. HSPICE simulations have been performed to verify the critical timing path and the system function. Summing node circuitry was connected to the feedback equalizer as a realistic output load in the simulations. Some simulation results for verifying the feedback loop are given in Figure 5.2 which shows that all signals are well synchronized by the clock signals and able to settle before being sampled.
5.2 Layout of the Feedback Equalizer
technology. Fully customized layout for both analog and digital circuits helps to improve

34
V
0
L
T
L
V
0
L
T
* ORWET OUTPUT FILE /HOME/xIAW6vI/MDFE/FOL/FOLSIMP
*
97/02/04 15:10:13
1
4_0 r
2. 0
I f
-1 o.
1
11
T 0
IFIBLSIMP_TPD a 4.0
_
FOLSIMP.TRO
CLt1 a
: B__ _ _ _
It
2_0
0
O.
5_1654 =
4.0
1,1
V
0
L
T
L
2.0 o.
5.1663 =
4.0
2.0
FPLSIMP.TPO
DIA
A
02A
D3A
F9L6IMP_T90
O
O 19
029
0­
03B
I
I 0
0 W
I-
-t-
-I I-1.I
I
I.;
20.0W 30_0W
TIME CLIW)
40 ON
0
50 OW 60.0W
62_0W a) Simulation of the delay chain
* ORWET OUTPUT FILE g/WOME/xIRWGyI/MDFE/F9L/FRL6IMP, *
97/02/05 00 46:44
F9LSIMP_TPD
CLK1
CLt2 v
0
L
T
L
I
W
V
0
L
T
L
5_1539 =
4.0
I
2.0
I-1
O.
5 _2089 5*--0.-­
4_0 I­
0_
_...L
1­
1
FBLSIMP.TPO
Q APIA[0]
TRP1RE11
VI_556_W_233
I­
-
FRLSIMP_TPD
PETRI xI_556.1,1_130 xI_556_13ETRO
1.1 b
A dil
&I C.4
1
TIME [LIN
00 ON
L
J
.....
L
.
, .
_ . _A_I
Y
T
1
150.0W
182.0W
FOLSIMP.TP0
EPP2
134A xI_556.W_13
(Enbl) b) Simulation of the counter and adaptation logic

35
DAWET OUTPUT FILE
.,,140ME/x1ANGII/HOFE/FDL/FDLSIHP$
97/02/04 15:10:13
L
O 1
L
L
O
1
L
4.
2.0T
=A_ -1­
0
4.0
2_0:
_s-
A L
200.0U _ loo.ou
11.1
; f
4--).1 j. ­ r
0.
150.011
A L
H I
P A
100.0U ;
50-0U ­
199.413U _
A L
H
I p
100_0U _
1 .7499U :
A L
H
1
P A
400 DU
200.0U
-w' r
10 .
I
20.014 30.011
TIME CLIW)
4 0 011
50.01
0.
_
FDLSIHP.TPO
CLL1
A
CLK2
FDLSIHP_TPO
- DIA
DID
=
-M FBL5THP_TP0
IlvDACIIM
­
=
ICODOCIIP
=
FDLSIMP_TP0
Ifv0AC2114 ilAiCv0AC21P
F9L5IMP.TPO
icvoacolu a
ICvDACOIP
= UH--­
A
=
ICvFDLIP c) Simulation of the DAC' s and the differential feedback currents
Figure 5.2 HSPICE simulation for the feedback loop speed performance and reduce die area. Guard rings around the digital blocks are used to reduce noise coupling from the digital section to the analog circuits through the common substrate. The layouts of each major block and the equalizer are shown in Appendix B.
Post-layout simulations for the DAC and the 10-bit counter given in Figure 5.3 show that even with some speed degradation due to the wiring capacitances, the decision feedback filter can achieve the desired speed.
5.3 Summary
In this thesis, the parallel structure of the multi-level decision feedback equalizer has been explored. Circuit designs for several major building blocks are carefully discussed. Extensive HSPICE simulations have been done to verify the circuit and

0
L
L
* FILE! !HOHE,XIANGTI/HEIFE/C4JT,EIVT_POST1.5P_ CPEATIOW TIME 1 0.7 FEB 15
97/02/15 15120140
4.0
7r­
CHT_PD51-1.71
VECLK vELOP,0
2_0 v
O
L
I
14
0.
5.1158
-
4.0
1
I
2.0[1 i I
5.0911
-
4.0
1 r
0
L
T
L
I
W
2_0
0
L
T
I
W
EL
5_0445
4_0
2.0
0_
0_
I
I
1
1
I
I
I
.
I ,
100.0W
)
I
1
_J.
Jiff
1 1
I
200:0WL
TIME [LIN]
_IF
L
_LL
I
I t
I i
I
I
1
I
300:0W
1
17_ ii2LT,POST1_71
1.7 0(22______
VE04
_
.
19 EWT_PD5T1.T1
0(05
-
CHT_POS.T1.71
0E07
VE00
0[09
4100-t0W
420.0W
36
0
T
L
* FILE! !HOHE/XIAWBTI/HCIFE/DgMg5TE07.i37EPERTIOW TIME! HOW FEB 10 2
5.0
4.0
F
1
-
=
-
DAC_POST TOO
IHP a
BIT2P
3_0 r
2_0,
1.0,
....JILL.,
II
H
P
175.01
150.0U
125.0U
100.0U
75.0U :
50.0U;
25.0U
175.0U :
150_0U
125.0U :
100.0U :
75.0U
50.0U
25.0U ;
0_
I I
!
---,---
--i
11111
1 10.0W 15.0W
TIME (LOW)
.1--...,...
v./
20.014 fie
25.0W i
_53
DAC_PO5T.TPO
Icvm1
.
=
=
Vc5,7,gN-ITJ-T"
ICvHOUTP
30. ON
32 OW b) Post layout simulation for the DAC and the multiplier
Figure 5.3 Post-layout simulation for the DAC and the counter

37 system design. It has been shown that the proposed parallel MDFE is able to achieve 100­
Mbs symbol rate.
5.4 Future work
In the feedback equalizer of this version, each tap has it is own counter and DAC to generate the digital coefficient and convert it to differential currents, respectively.
However, in the circuit design, both the DAC and the counter can work much faster than required by the system architecture. It's possible to share the counters and DAC's by adding some control logic and current copiers. Thus both the die area and power consumption would be greatly reduced.

38
Bibliography
[1]
[2]
[3]
[4]
[5]
G. Long, et al., "The LMS algorithm with Delayed Coefficient Adaptation,"
IEEE trans. on Acoustics, Speech, and Signal Proc., vol. 37, no. 9, pp. 1397­
1405, Sept. 1989
J.M. Cioffi, et al., "Adaptive Equalization in Magnetic-disk Storage Channels,"
IEEE Comm. Mag., pp.14-29, Feb. 1990
J.W. Bergman, et al., "Density improvements in digital magnetic recording by decision feedback equalization," IEEE Trans. on Mag., vol. 22, no. 3, pp. 157­
162, May 1986
J.G. Kenney, et al., "Multi-level Decision Feedback Equalization for Saturation
Recording," IEEE Trans. on Magn., vol. 29, no. 4, pp. 2160-2171, July 1993
J.G. Kenney et al., "Multi-level Decision Feedback Equalization: An Efficient
Realization of FDTS/DF," IEEE Trans. on Magnetics, vol. 31, no. 2, pp. 1115­
1121, Mar. 1995
[6]
[7]
J.G. Kenney, et al., "Pipelining for Speed doubling in MDFE," Proceedings of the IEEE International conference on Communications, vol. 1, pp. 561-565,
June 1996.
J.E. Brown, et al., "A 35-Mb/s Mixed-Signal Decision-Feedback Equalizer for
Disk-Drive Applications," IEEE J. Solid-State Circuits, vol. 31, no. 9, pp. 1258­
1266, Sep. 1996
[8]
[9]
J.C. Boyce, Digital Logic Operation and Analysis, Prentice-Hall, Englewood
Cliffs, N.J., 1982
J.-R. Yuan, et al., "High-Speed CMOS Circuit Technique," IEEE J. Solid-State
Circuits, vol. 24, no. 1, pp. 62-70, Feb. 1989
[10] J.-R. Yuan, et al., "Fast CMOS Nonbinary Divider and Counter," Electronics
Letter, vol. 29, no. 13, pp. 1222-1223, June 1993
[11] J.F. Wakerly, Digital Design Principles and Practice, Prentice-Hall, Englewood
Cliffs, N.J., 1990
[12] A. Cremonesi, et al., "A 100-MHz CMOS DAC for Video-Graphic Systems,"
IEEE J. Solid-State Circuits, vol. 24, no. 3, pp. 635-639, June 1989
[13] K. L. Fong, et al., "A 10 Bit Semi-Algorithmic Current Mode DAC," Proc. IEEE

39
Int. Symp. on Circuits and Systems, pp. 978-981, Chicago, 1993
[14] C. A. A. Bastiaansen, et al., "A 10-b 40MHz 0.8-urn CMOS Current-Output D/
A Converter," IEEE J. of Solid-State Circuits, vol. 26, pp. 917-921, July 1991
[15] S.-Y. Chin, et al., "A 10-b 125-MHz CMOS Digital-to-Analog Converter (DAC) with Threshold-Voltage Compensated Current Sources," IEEE J. of Solid-State
Circuits, vol. 29, pp. 1374-1380, Nov. 1994

Appendices
40

Appendix A. Mat lab Simulation Code
% File SimMDFE.m
:
% Programmer Yihai Xiang
:
% Note Simulation of MDFE (Parallel structure)
:
%%%%%%%%%%Generate random RLL(1,7) input code%%%%%%%%%%
N = 4000; u = randn(N + 10, 1); u = sign(u); st = 1; for i = 1 N + 10
: if u(i) == 0 u(i) = 1; end if st == 1 u(i) = 1; st = 2; elseif st == -1 u(i) = -1; st = -2; elseif st == 7 u(i) = -1; st = -1; elseif st == -7 u(i) = 1; st = 1; elseif st > 1 if u(i) == 1 st = st + 1; else st = -1; end else if u(i) == -1 st = st 1; else st = 1; end end end
%%%%%%%%%Generate MDFE input (FE output)%%%%%%%%%%%%%% noise = 0.25; %Channel noise offset = 0.1; %Offset
41

42
%P = [0.5 0.8 0.5 -0.18 -0.35 -0.24 -0.15 -0.09 -0.04 -0.02
0.011];
%P = [-0.01 -0.02 -0.04 -0.09 -0.15 -0.24 -0.35 -0.18 0.5
0.8 0.5];
%P = [1.0863 2.0000 1.1161 -0.2774 -0.8367 -0.8032 -0.6616
0.5103 -0.3594 -0.2432 -0.1662]
P = [-0.1662 -0.2432 -0.3594 -0.5103 -0.6616 -0.8032 -0.8367
0.2774
...
1.1161 2.0000 1.0863]; x = zeros(N, 1); for i = 11 N + 10
: x(i 10) = sum(P .* u(i 10
: i)'); end x = x + offset + randn(N, 1)*noise;
%%%%%%%%%Simlate MDFE (My structure) % % % % % % % % % % % % % % % % % % % % %%
ENBL = 5;
Gain = 3;
Pf = zeros(8, 1); % 8 taps (counters)
Pf_dcl = 0; %DC tap for channell
Pf_dc2 = 0; %DC tap for channel2 beta = 1/2'1; %Adaptation step
Achl_Odd = zeros(4, 1); %Delay chain for channell
Ach1_Even = zeros(5, 1); %Delay chain for channell
Ach2_Odd = zeros(6, 1); %Delay chain for channel2
Ach2_Even = zeros(4, 1); %Delay chain for channel2
PfS1 = Pf; %S/H for channell counter ouputs
PfS2 = Pf; %S/H for channel2 counter ouputs
%Initial counters
Pf = [0.2774 0.8367 0.8032 0.6616 0.5103 0.3594 0.2432
0.1662];
Pf = Pf/Gain;
Y_chl = zeros(floor(N/2) + 1, 1); %Summing node ouputs for channell
Y_ch2 = zeros(floor(N/2) + 1, 1); %Summing node ouputs for channel2
Err_chl = 1; %Error signals
Err_ch2 = 1;
CompOutl = 0; %Comparator ouputs
CompOut2 = 0; offset_chl = 0.1; %Offset created by channell offset_ch2 = -0.1; %Offset created by channel2 preset_offset = -0.4; %Preset offset for both channels
A = zeros(N, 1); %MUX outputs (decision sequence)

43 for i = 1 N
: idx = floor(i/2) + 1; if i == 400 %End of startup beta = 1/2^10; end if (idx 1) -= i/2
%%%Channell%%%
Z_chi = PfS1(1)*Achl_Odd(1) + PfS1(3)*Achl_Odd(2) +
PfS1(5)*Achl_Odd(3)
...
+ PfS1(7)*Achl_Odd(4) + PfS1(2)*Achl_Even(1) +
PfS1(4)*Achl_Even(2) ...
+ PfS1(6)*Achl_Even(3) + PfS1(8)*Achl_Even(4);% + Pf_dcl
+ preset_offset;
Y_chl(idx) = x(i) + Z_chl*Gain + offset_chl;
%%%Comparator of channell: A(i
1) if Y_chl(idx) >= 0
CompOutl = 1; else
CompOutl = -1; end
%%%Sample and hold counter outputs
PfS1(1) = Pf(1); PfS1(3) = Pf(3); PfS1(5) = Pf(5);
PfS1(7) = Pf(7);
PfS1(2) = PfS2(2); PfS1(4) = PfS2(4); PfS1(6) = PfS2(6);
PfS1(8) = PfS2(8);
%%%Delay chain of channell
Achl_Odd(2:4) = Achl_Odd(1:3);
Achl_Odd(1) = CompOutl;
Achl_Even(2:5) = Achl_Even(1:4);
Ach1_Even(1) = Ach2_0dd(1);
%%%Counters & adaptatation logic of channell if ENBL == 1 if Achl_Odd(1) == -Achl_Odd(2) %Inner level, adapta­ tion needed for index (i
2)
Pf(1) = Pf(1) + beta *Err_ch2 *Achl_Even(2);
Pf(3) = Pf(3) + beta*Err_ch2*Achl_Even(3);
Pf(5) = Pf(5) + beta *Err_ch2 *Achl_Even(4);
Pf(7) = Pf(7) + beta*Err_ch2*Achl_Even(5);
Pf_dc2 = Pf_dc2 + beta*Err_ch2; end

44 end
%%%Error generater logic: calculate error for index (i
1) if Achl_Odd(1) == 1 if Y_chl(idx) >= P(10)
Err_chl = -1; else
Err_chl = 1; end else if Y_chl(idx) <= -P(10)
Err_chl = 1; else
Err_chl = -1; end end
%%%End of Channell%%% else
% % %Channel2 % %%
Z_ch2 = PfS2(1)*Ach2_0dd(1) + PfS2(3)*Ach2_0dd(2) +
PfS2(5)*Ach2_0dd(3)
...
+ PfS2(7) *Ach2_Odd(4) + PfS2(2)*Ach2_Even(1) +
PfS2(4)*Ach2_Even(2)
...
+ PfS2(6)*Ach2_Even(3) + PfS2(8)*Ach2_Even(4);% + Pf_dc2
+ preset_offset;
Y_ch2(idx) = x(i) + Z_ch2*Gain + offset_ch2;
%%%Comparator of channel2: A(i
1) if Y_ch2(idx) >= 0
CompOut2 = 1; else
CompOut2 = -1; end
%%%Sample and hold counter outputs
PfS2(2) = Pf(2); PfS2(4) = Pf(4); PfS2(6) = Pf(6);
PfS2(8) = Pf(8);
PfS2(1) = PfS1(1); PfS2(3) = PfS1(3); PfS2(5) = PfS1(5);
PfS2(7) = PfS1(7);
%%%Delay chain of channel2
Ach2_Odd(2:6) = Ach2_0dd(1:5);
Ach2_0dd(1) = CompOut2;

45
Ach2_Even(2:4) = Ach2_Even(1:3);
Ach2_Even(1) = Ach1_0dd(1);
%%%Counters & adaptatation logic of channel2 if ENBL == 1 if Ach2_0dd(1) == -Ach2_0dd(2) %Inner level, adapta­ tion needed for index (i
2)
Pf(2) = Pf(2) + beta *Err_chl *Ach2_Odd(3);
Pf(4) = Pf(4) + beta*Err_ch1*Ach2_0dd(4);
Pf(6) = Pf(6) + beta *Err_chl *Ach2_Odd(5);
Pf(8) = Pf(8) + beta *Err_chl *Ach2_Odd(6);
Pf_dcl = Pf_dcl + beta *Err_chl; end end
%%%Error generater logic: calculate error for index (i
1) if Ach2_Odd(1) == 1 if Y_ch2(idx) >= P(10)
Err_ch2 = -1; else
Err_ch2 = 1; end else if Y_ch2(idx) <= -P(10)
Err_ch2 = 1; else
Err_ch2 = -1; end end
%%%End of Channel2 % %% end
%%%Output MUX if (idx 1) -= i/2
A(i) = CompOutl; else
A(i) = CompOut2; end end

Appendix B. Layouts
Appendix B.1 Layout of the decoder
46

Appendix B.2 Layout of the 6-bit DAC
47
.111:41
" lin Mimi II I ri lir
MUT)
WO .004ellWilli
Egg
70,1

Appendix B.3 Layout of the multiplier
48
NOPOISAWC:ON

Appendix B.4 Layout of the 10-bit up/down counter, latches and control logic
49
j,;;,;:iii%:71
1F1

WM. VI *WM
I : C
17! Z
47.11 r
_
171, mi.!".
WV-1-n--t-:
I.
I
I
-46
6W
Mimil .."
111
!
,
,r.
.L
4ni
I set
V.
1.1.
Qui 11111 cal r in III ail huh n
;
4,911 hUt 1111 lull
' ' ii''
...
.!palm! ma, Illp iiiP 111.
# 4.
. .
.1 .1
.
Illb
,
1101 hti
WAN; I
_
1 /111,1 MI 11.1 iii
III M.
4 pm Hip
. 4 a lbw." el ji
.
.
II limn i
I ot...1
.
Tr.
I
_ots
N
7 1k
J
.
Ito
Irp.....", -7
......r....-7.:.:.71L1.'ILI.11­
11 111
IL-6-01-nrig:
. i.
1,
1
. r trmmiu.­
1 Im,...--.
.
'
.
Orittil.,,,1111:,,.
I
'11
.
_
. ... ,,.. ..., ,,,,
!. . '.
. .
.
Jim pill! 111111 III '
I. 1* i'
.
-." .in
. .....
_
*
. i
V T iii iiiii sem 11114 ilii
1 !AI
Emil mac
. d
/Pi!
t
.
.
itiumno Jai ail:
I. ;­
.1111
Iii I hut if
V --1 i . ,.. 'Ai - 'I -.011 . i
4, IIII A111,1 1 1111 PEI till mu illi
<
11.111111111111! TIM
#
11111 1
IIIP
;I._
,
A
1
: ?
.1\
IV.;
4
.
! '-'
,.. men......_ a
M tog i I
..
It
!
.
II wig
I
1.
. "Tr 1.1MOrd
I aiiram
NM
4
1 7 t,
11: