# cont. October 13, 2005 1. The saturation regime 2. Backgate characteristics

```6.012 - Microelectronic Devices and Circuits - Fall 2005
Lecture 10-1
Lecture 10 - MOSFET (II)
MOSFET I-V Characteristics (cont.)
October 13, 2005
Contents:
1. The saturation regime
2. Backgate characteristics
Howe and Sodini, Ch. 4, &sect;4.4
Announcements:
Quiz 1: 10/13, 7:30-9:30 PM, (lectures #1-9); open book; must
have calculator.
have
6.012 - Microelectronic Devices and Circuits - Fall 2005
Lecture 10-2
Key questions
• How does the MOSFET work in saturation?
• Does the pinch-oﬀ point represent a block to current
ﬂow?
• How come the MOSFET current still increases a bit
with VDS in saturation?
• How does the application of a back bias aﬀect the
MOSFET I-V characteristics?
Lecture 10-3
6.012 - Microelectronic Devices and Circuits - Fall 2005
1. The saturation regime
Geometry of problem:
y
0
L
VDS
VGS
n+
S
-tox
0
ID
G
IS
D
n+
n+
xj
inversion
layer
VBS=0
depletion
region
p
B
x
Regimes of operation so far (VBS = 0):
• Cut-oﬀ: VGS &lt; VT , VGD &lt; VT :
no inversion layer anywhere underneath gate
ID = 0
• Linear: VGS &gt; VT , VGD &gt; VT (with VDS &gt; 0):
inversion layer everywhere underneath gate
W
VDS
− VT )VDS
ID = &micro;nCox (VGS −
L
2
Lecture 10-4
6.012 - Microelectronic Devices and Circuits - Fall 2005
Output characteristics:
ID
VDS=VGS-VT
VGS
VGS=VT
0
0
VDS
Lecture 10-5
6.012 - Microelectronic Devices and Circuits - Fall 2005
2 Review of Qn, Ey , Vc , and VGS − Vc(y) in linear regime
as VDS increases:
|Qn(y)|
VDS=0
Cox(VGS-VT)
VDS
0
0
L
y
|Ey(y)|
VDS
VDS=0
0
0
L
y
Vc(y)
VDS
VDS
VDS=0
0
L
0
y
VGS-Vc(y)
VDS=0
VDS
VGS
VDS
local gate
overdrive
VT
0
L
y
Ohmic drop along channel debiases inversion layer
⇒ ID rises more slowly with VDS
Lecture 10-6
6.012 - Microelectronic Devices and Circuits - Fall 2005
2 Drain current saturation
As VDS approaches:
VDSsat = VGS − VT
increase in |Ey | compensated by decrease in |Qn|
⇒ ID saturates to:
IDsat = IDlin(VDS = VDSsat = VGS − VT )
Then:
W
IDsat =
&micro;nCox(VGS − VT )2
2L
VDSsat=VGS-VT
ID
linear
saturation
VGS
VGS=VT
0
0
cutoff
VDS
Lecture 10-7
6.012 - Microelectronic Devices and Circuits - Fall 2005
W
IDsat =
&micro;nCox(VGS − VT )2
2L
Transfer characteristics in saturation:
ID
VDS&gt;VDSsat=VGS-VT
0
0
VT
VGS
6.012 - Microelectronic Devices and Circuits - Fall 2005
Lecture 10-8
2 What happens when VDS = VGS − VT ?
Charge control relation at drain-end of channel:
Qn(L) = −Cox(VGS − VDS − VT ) = 0 No inversion layer at end of channel??!! ⇒ Pinch-oﬀ
At pinch-oﬀ:
• charge control equation inaccurate around VT
• electron concentration small but not zero
• electrons move fast because electric ﬁeld is very high
• dominant electrostatic feature: acceptor charge
• there is no barrier to electron ﬂow (on the contrary!)
G
D
- -
+
- - - - - - - ++ + ++
+++ + +
-- - - -
n+ drain
inversion layer
p
depletion regions
L
y
Lecture 10-9
6.012 - Microelectronic Devices and Circuits - Fall 2005
2 Key dependencies of IDsat
• IDsat ∝ (VGS − VT )2
Voltage at pinch-oﬀ point (Vc = 0 at source):
G
-
��
D
- -
--
-
-
-
p
+
-+
n+
++++ +++++
-- - - -
Vc(L)=VDSsat=VGS-VT
Drain current at pinch-oﬀ:
∝ lateral electric ﬁeld ∝ VDSsat = VGS − VT
∝ electron concentration ∝ VGS − VT
⇒ IDsat ∝ (VGS − VT )2
• IDsat ∝
1
L
L ↓ → |Ey | ↑
6.012 - Microelectronic Devices and Circuits - Fall 2005
Lecture 10-10
3&micro;m n-channel MOSFET
Output characteristics (VGS = 0 − 4 V, ∆VGS = 0.5 V ):
6.012 - Microelectronic Devices and Circuits - Fall 2005
Lecture 10-11
Transfer characteristics in saturation (VDS = 3 V ):
Lecture 10-12
6.012 - Microelectronic Devices and Circuits - Fall 2005
2 What happens if VDS &gt; VGS − VT ?
Depletion region separating pinch-oﬀ point and drain widens
(just like in reverse-biased pn junction)
G
D
-
- -
-
-+
+
n+
- - - ++++ +++++
-- - - -
Vc(L-∆L)=VDSsat=VGS-VT
p
L-∆L L
y
To ﬁrst order, ID does not increase past pinchoﬀ:
W
ID = IDsat =
&micro;nCox (VGS − VT )2
2L
To second order, electrical channel length aﬀected
”channel-length modulation”
(”channel-length
modulation”): VDS ↑⇒ Lchannel ↓⇒
ID ↑
1
∆L
1
(1 +
)
ID ∝
L − ∆L L
L
Lecture 10-13
6.012 - Microelectronic Devices and Circuits - Fall 2005
Experimental ﬁnding:
∆L ∝ VDS − VDSsat
Hence:
∆L
= λ(VDS − VDSsat)
L
Improved model in saturation:
W
IDsat =
&micro;nCox (VGS − VT )2 [1 + λ(VDS − VDSsat)]
2L
VDSsat
ID
VGS
VGS=Vth
0
0
VDS
Also, experimental ﬁnding:
1
λ∝
L
Lecture 10-14
6.012 - Microelectronic Devices and Circuits - Fall 2005
2. Backgate characteristics
There is a fourth terminal in a MOSFET: the body.
What does the body do?
VDS
ID
VGS&gt;VT
G
S
D
n+
n+
inversion layer
VBS
depletion region
p
0
L
y
B
Body contact allows application of bias to body with re
spect to inversion layer, VBS .
Only interested in VBS &lt; 0 (pn diode in reverse bias).
Interested in eﬀect on inversion layer
⇒ examine for VGS &gt; VT (keep VGS constant).
Lecture 10-15
6.012 - Microelectronic Devices and Circuits - Fall 2005
Application of VBS &lt; 0 increases potential build-up across
semiconductor:
−2φp ⇒ −2φp − VBS
Depletion region must widen to produce required extra
ﬁeld:
ρ
xdmax(VBS)
0
0
x
-tox
-qNa
Qn
E
Eox
VBS=0
Es
0
-tox
VBS&lt;0
x
0
xdmax(VBS)
φ
Vox
VGS+φB
0
VBS
-tox
-φp
0
x VB=-2φp
VB=-2φp-VBS
6.012 - Microelectronic Devices and Circuits - Fall 2005
Lecture 10-16
Consequences of application of VBS &lt; 0:
• −2φp ⇒ −2φp − VBS
• |QB | ↑⇒ xdmax ↑
• since VGS constant, Vox unchanged
⇒ Eox unchanged
⇒ |Qs| = |QG| unchanged
• |Qs| = |Qn| + |QB | unchanged, but |QB | ↑ ⇒ |Qn| ↓
layer
⇒ inversion la
yer charge is reduced!
Application of VBS &lt; 0 with constant VGS reduces electron concentration in inversion layer ⇒ VT ↑
Lecture 10-17
6.012 - Microelectronic Devices and Circuits - Fall 2005
How does VT change with VBS ?
In VT formula change −2φp to −2φp − VBS :
VTGB (VBS )
�
= VF B − 2φp − VBS + γ (−2φp − VBS )
In MOSFETs, interested in VT between gate and source:
VGB = VGS − VBS ⇒ VTGB = VTGS − VBS
Then:
VTGS = VTGB + VBS
And:
VTGS (VBS )
�
= VF B − 2φp + γ (−2φp − VBS ) ≡ VT (VBS )
In the context of the MOSFET, VT is always deﬁned in
terms of gate-to-source voltage.
Lecture 10-18
6.012 - Microelectronic Devices and Circuits - Fall 2005
Deﬁne:
VT o = VT (VBS = 0)
Then:
�
�
VT (VBS ) = VT o + γ( −2φp − VBS − −2φp )
ID
VBS
saturation
cut-off
0
0
VT
VGS
6.012 - Microelectronic Devices and Circuits - Fall 2005
Lecture 10-19
Backate characteristics (VBS = 0, −1, −2, −3 V, VDS =
3 V ):
6.012 - Microelectronic Devices and Circuits - Fall 2005
Lecture 10-20
Key conclusions
• MOSFET in saturation (VDS ≥ VDSsat): pinch-oﬀ
point at drain-end of channel
– electron concentration small, but
– electrons move very fast;
– pinch-oﬀ point does not represent a barrier to electron ﬂow
• In saturation, ID saturates:
IDsat =
W
&micro;nCox(VGS − VT )2
2L
• But..., due to channel-length modulation, IDsat increases slightly with VDS
• Application of back bias shifts VT (back-gate eﬀect)
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