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6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005 Lecture 8­1 Lecture 8 ­ PN Junction and MOS Electrostatics (V) Electrostatics of Metal­Oxide­Semiconductor Structure (cont.) October 4, 2005 Contents: 1. Overview of MOS electrostatics under bias 2. Depletion regime 3. Flatband 4. Accumulation regime 5. Threshold 6. Inversion regime Reading assignment: Howe and Sodini, Ch. 3, §§3.8­3.9 Announcements: Quiz 1: 10/13, 7:30­9:30 PM, (lectures #1-9); open book; must have calculator. 6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005 Lecture 8­2 Key questions • Is there more than one regime of operation of the MOS structure under bias? • What does ”carrier inversion” mean and what is the big deal about it? • How does the carrier inversion charge depend on the gate voltage? 6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005 Lecture 8­3 1. Overview of MOS electrostatics under bias VGB +­ "metal"� (n+ polySi) semiconductor� (p type) oxide contact -tox 0 contact x Application of bias: • built­in potential across MOS structure increases from φB to φB + VGB • oxide forbids current ﬂow ⇒ – J = 0 everywhere in semiconductor – need drift=­diﬀusion in SCR • must maintain boundary condition at Si/SiO2 inter­ face: Eox/Es � 3 How can this be accommodated simultaneously? ⇒ quasi­equilibrium situation with potential build up across MOS equal to φB + VGB 6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005 Important consequence of quasi­equilibrium: ⇒ Boltzmann relations apply in semiconductor [they were derived starting from Je = Jh = 0] n(x) = ni eqφ(x)/kT p(x) = ni e−qφ(x)/kT and np = n2i at every x [not the case in p­n junction or BJT under bias] Lecture 8­4 6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005 Lecture 8­5 2. Depletion regime For VGB > 0 gate ”attracts” electrons, ”repels” holes ⇒ depletion region widens For VGB < 0 gate ”repels” electrons, ”attracts” holes ⇒ depletion region shrinks ρ xd(VGB) 0 0 x -tox -qNa E Eox Es 0 -tox 0 x xd(VGB) φ VGB<0 VGB=0 VGB>0 φ B+VGB φB 0 xd(VGB) x -tox 0 log p, n Na p n ni2 Na -tox 0 xd(VGB) x 6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005 Lecture 8­6 In depletion regime, all results obtained for zero bias ap­ ply if φB → φB + VGB . For example: • depletion region thickness: xd(VGB ) = � � � � � � � �s 4(φB + VGB ) [ 1 + − 1] 2 Cox γ • potential drop across semiconductor SCR: qNax2d (VGB ) VB (VGB ) = 2�s • potential drop across oxide: qNaxd (VGB )tox Vox (VGB ) = �ox 6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005 Lecture 8­7 3. Flatband At a certain negative VGB , depletion region is wiped out ⇒ Flatband ρ ρ=0 0 0 x -tox E Eox=0 Es=0 0 0 -tox x φ VGB=0 VGB=VFB VGB=-φ B 0 0 x -tox log p, n p n -tox 0 Flatband voltage: VF B = −φB Na ni2 Na x 6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005 Lecture 8­8 4. Accumulation regime If VGB < VF B accumulation of holes at Si/SiO2 interface ρ 0 -tox 0 x Es x E 0 0 -tox Eox φ 0 -tox 0 x VGB-VFB log p, n p n -tox 0 Na ni2 Na x 6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005 Lecture 8­9 5. Threshold Back to VGB > 0. For suﬃciently large VGB > 0, electrostatics change when n(0) = Na ⇒ threshold. Beyond threshold, cannot neglect contributions of elec­ trons towards electrostatics. n(0)=Na log p, n Na p n ni2 Na -tox 0 xdmax x Let’s compute the voltage (threshold voltage) that leads to n(0) = Na. Key assumption: use electrostatics of depletion (neglect electron concentration at threshold). 6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005 Lecture 8­10 � Computation of threshold voltage. Three­step process: • First, compute potential drop in semiconductor at thresh­ old. Start from: n(0) = nieqφ(0)/kT Solve for φ(0) at VGB = VT : kT n(0) kT Na = ln |V = ln = −φp q ni T q ni φ(0)|VT φ VT+φ B 0 -tox -φ p 0 x xdmax φp Hence: VB (VT ) = −2φp VB=-2φ p 6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005 Lecture 8­11 • Second, compute potential drop in oxide at threshold. Obtain xd (VT ) using relationship between VB and xd in depletion: qNax2d(VT ) VB (VT ) = = −2φp 2�s Solve for xd (VT ): xd(VT ) = xdmax � � � � � � � 2�s(−2φp ) = qNa Then: Vox(VT ) = Eox (VT )tox � qNaxd(VT ) = tox = γ −2φp �ox φ Vox VT+φ B 0 -tox -φ p 0 x xdmax φp VB=-2φ p 6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005 Lecture 8­12 • Finally, sum potential drops across structure. φ Vox VT+φ B 0 -tox -φ p 0 x xdmax VB=-2φ p φp � VT + φB = VB (VT ) + Vox (VT ) = −2φp + γ −2φp Solve for VT : � VT = VF B − 2φp + γ −2φp Key dependencies: • If Na ↑ → VT ↑. The higher the doping level, the more voltage required to produce n(0) = Na. • If Cox ↑ (tox ↓) → VT ↓. The thinner the oxide, the less voltage dropped across it. 6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005 Lecture 8­13 6. Inversion What happens for VGB > VT ? More electrons at Si/SiO2 interface than acceptors ⇒ inversion. inversion layer log p, n Na n p ni2 Na -tox 0 xdmax x Electron concentration at Si/SiO2 interface modulated by VGB ⇒ VGB ↑→ n(0) ↑→ |Qn| ↑ ﬁeld­eﬀect control of mobile charge! [essence of MOSFET] Want to compute Qn vs. VGB [charge­control relation] Make sheet charge approximation: electron layer at semi­ conductor surface is much thinner than any other dimen­ sion in problem (tox , xd ). 6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005 Lecture 8­14 � Charge­control relation Let us look at overall electrostatics: ρ xdmax 0 0 -tox x -qNa Qn E Eox Es 0 -tox 0 xdmax x 0 xdmax x φ VGB+φ B 0 -tox log p, n Na n p -tox 0 ni2 Na xdmax x 6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005 Lecture 8­15 Key realization: |Qn| ∝ n(0) ∝ eqφ(0)/kT � |QB | ∝ φ(0) Hence, as VGB ↑ and φ(0) ↑, |Qn| will change a lot, but |QB | will change very little. Several consequences: • little change in φ(0) beyond threshold • VB does not increase much beyond VB (VT ) = −2φp (a thin sheet of electrons does not contribute much to VB ): VB (inv.) � VB (VT ) = −2φp • little change in QB beyond threshold • xd does not increase much beyond threshold: xd(inv.) � xd (VT ) = � � � � � � � 2�s(−2φp ) = xdmax qNa 6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005 Lecture 8­16 • All extra voltage beyond VT used to increase inversion charge Qn. Think of it as capacitor: – top plate: metal gate – bottom plate: inversion layer Q = CV ⇒ Qn = −Cox (VGB − VT ) for VGB > VT Existence of Qn and control over Qn by VGB ⇒ key to MOS electronics |Qn| Cox VT VGB 6.012 ­ Microelectronic Devices and Circuits ­ Fall 2005 Lecture 8­17 Key conclusions M VGB<VFB O ------ S (p-type) ++ ++ ++ ++ + accumulation flatband VGB=VFB VFB<VGB<0 VGB=0 0<VGB<VT VGB=VT VGB>VT + ++ + + + + +++ ++ + ++ + ++ ++ + + +++ + + + + + ++ + + ++++ ++ ++ + +++ + - depletion - -- - - - - zero bias - depletion - - - - -- - ---- -- -- - --- - - - --- - - - ----- - -- - - ---- - ---- - - ----- - - threshold inversion In inversion: |Qn| = Cox (VGB − VT ) for VGB > VT