Analysis and design optimization of enhanced swing CMOS LC
oscillators based on a phasor based approach
Roy, A. G., Mayaram, K., & Fiez, T. S. (2015). Analysis and design optimization of
enhanced swing CMOS LC oscillators based on a phasor based approach. Analog
Integrated Circuits and Signal Processing, 82(3), 691-703.
doi:10.1007/s10470-015-0490-6
10.1007/s10470-015-0490-6
Springer
Accepted Manuscript
http://cdss.library.oregonstate.edu/sa-termsofuse
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Analysis and Design Optimization of Enhaned Swing CMOS
LC Osillators based on a Phasor Based Approah
Ankur Guha Roy · Kartikeya Mayaram · Terri S. Fiez
Reeived: Aug 19, 2014 / Aepted: Jan 08, 2015
Abstrat
Analysis and design optimization of enhaned
frequeny generation. In WSN appliations, an open
swing, low power CMOS LC osillators is presented.
loop osillator is often used as a frequeny referene [1℄.
A phasor analysis based approah for determining the
The phase noise performane of on-hip osillators suf-
amplitude and phase noise of these osillators is used.
fers drastially from a redution in the supply voltage.
MOSFET operation in ut-o, linear and saturation
In order to ahieve good phase noise performane at
regions is inluded. The alulated steady state out-
a sub 0.5 V supply voltage, output swing enhanement
put amplitude and phase noise from this analysis are in
tehniques have been developed [13℄. These enhaned
good agreement with Cadene Spetre simulations for
swing osillators show performane omparable to the
dierent bias onditions. Appliation of this analysis
state-of-the-art urrent soure biased LC osillator im-
to the design optimization of LC osillators is demon-
plementations [4℄. Current soure biased LC osillators
strated.
Keywords
are extensively used for on-hip appliations and their
LC osillator, enhaned swing osillator,
Colpitts osillator, X-oupled, voltage biased, phase
noise, phasor model, ISF, PPV, spetrum onversion,
amplitude analysis, design optimization, design
oriented analysis, osillator design.
amplitude and phase noise expressions have been analyzed extensively [58℄. However, no detailed amplitude
and phase noise analysis is available for enhaned swing
osillators whih are inherently voltage biased osillators.
In a urrent biased CMOS osillator, the transistors
are fored to operate in a urrent limited regime [5℄.
1 Introdution
Wireless Sensor Networks (WSN) have been an important area of researh in reent years. A WSN usually
onsists of numerous independent sensor nodes. The
sensor nodes are usually implemented battery free and
are powered by energy harvesters, e.g., radio frequeny
(RF), thermoeletri or piezoeletri power generators.
These energy harvesters usually produe sub 0.5 V outputs. A redution in supply voltage produes many design hallenges for analog and RF iruits. Most RF
transeivers use an osillator with low phase noise for
Shool of EECS
Oregon State University
Corvallis, OR 97331
Tel: (541) 737-3617
This ensures that the transistors mostly operate in either the saturation or ut-o region whih simplies
the analysis. However, for voltage biased osillators,
MOSFET operation in the triode region adds signifiant omplexity in haraterizing their performane.
Furthermore, the analysis proedure for nding the amplitude and phase noise of urrent biased osillators
in [4℄ annot be diretly applied to the voltage biased,
enhaned swing osillators due to the absene of a tail
urrent soure. Even for a urrent biased Colpitts osillator, if the transistor is allowed to operate in the
triode region for a onsiderable time, the analysis leads
to expressions that are ompliated [9℄ and neessitates
the use of a non-linear equation solver.
In [10℄ it was shown that a phasor based approah
an be used to evaluate the osillation amplitude and
Fax: (541)-737-1300
phase noise of LC osillators. In this approah, all volt-
E-mail: guharoyaees.oregonstate.edu
ages and urrents are represented as a ombination of
2
Ankur Guha Roy et al.
phasors. The interation between these phasors in the
of the analysis for osillator design along with an ex-
steady state an be used to evaluate the amplitude. The
ample. Finally, onlusions are drawn in Setion VI.
phase noise an be omputed as a result of the interation of these phasors with the noise soures [11, 12℄.
Our work, for the rst time applies the phasor based
approah for amplitude and phase noise analysis to enhaned swing dierential and quadrature osillators.
Three enhaned swing osillator topologies are ompared and it is shown that this analysis is eetive
for these arhitetures. Our analysis aounts for transistor operation in the triode region and the ontribution of
1/f
noise for phase noise analysis. Prior work
in [9℄, [10℄ and [13℄ has addressed these issues partially.
In [9℄ a phasor based amplitude analysis of a urrent
biased Colpitts osillator with emphasis on triode region operation was proposed but it is not appliable
for enhaned swing voltage biased osillators. We have
generalized and extended the method of [9℄ for the enhaned swing, voltage biased osillators. In [10℄, the amplitude of a ross-oupled voltage biased osillator was
analyzed using a level-I MOSFET model and a polyno-
2 Amplitude Analysis of CMOS LC Osillators
An amplitude analysis approah for MOSFET based
voltage biased ross-oupled osillators was disussed
in [10℄, where the non-linear, MOSFET ross-oupled
5th order
pair harateristis are approximated by a
polynomial. In [9℄ and [16℄, the amplitudes for urrent biased Colpitts osillators and voltage biased rossoupled osillators were obtained respetively with the
square law MOSFET harateristis requiring no polynomial tting. In our work, the amplitude is evaluated
with the square law MOSFET level-I model. It will be
shown later that a level-I MOSFET model an give a
good estimate of amplitude and phase noise even for
deep sub-miron CMOS proesses. The generalized amplitude analysis method valid for both dierential and
quadrature osillators is desribed next.
analysis was developed only for the
mial approximation. Furthermore, a phasor based noise
1/f 2 region. In [13℄
2.1 Amplitude Evaluation for Dierential Osillators
a phasor based phase noise analysis valid for both the
1/f 3 and 1/f 2 regions was reported. However, the anal-
The two osillators analyzed in this setion are the En-
ysis was only appliable for urrent biased Colpitts os-
haned Swing Dierential Colpitts (ESDC) osillator [2℄
illators. Our work extends the noise analysis of [13℄ to
and the ross-oupled Colpitts (XCC) osillator [1℄ with
voltage biased enhaned swing osillators.
Simplied models of amplitude and phase noise of
a DC bias shift. They are shown in Fig. 1(a) and (b).
The single-ended equivalent iruit is shown in Fig. 1().
a osillator, based on devie dimensions and omponent parameters are useful for a iruit designer to nd
The MOSFET based osillators an be mapped from
the performane trade-os. A design tool based on suh
the original iruit in terms of a drain-to-gate feedbak
(k),
(n) and an
Ce at the drain. By seleting a
≫ cgs , in Fig. 1(b), n and Ce an be expressed as,
drain-to-soure feedbak fator
a model allows for a quik exploration of the design
fator
spae and to obtain the optimal parameters. However,
equivalent apaitane
no suh tool exists for the design and optimization of
Cbias
osillators. A few tehniques for osillator optimization
have been reported in [14, 15℄, where a iruit simulator was used internally to alulate the phase noise and
power onsumption of an osillator and an take hours
to onverge to an optimum solution. By replaing the
use of a iruit simulator with a simple MATLAB based
algorithm, the optimum design hoies an be quikly
obtained. We demonstrate the appliations of our analysis in a tool for osillator design optimization. The tool
is used for a rst pass design estimate without running
extensive iruit level simulations enabling fast design
of osillators.
The paper is organized as follows: Setion II presents
the amplitude analysis of various enhaned swing LC
n=
C1
C1 C2
; Ce =
C1 + C2
C1 + C2
where
(1)
C2
is the equivalent apaitane at the soure of
C2 = C2S − ω21L2 . k is
o
for an ESDC osillator and 1 for an XCC osillator.
the MOSFET and is given by,
0
The osillation frequeny
(ωo )
of the osillators an
be shown to be [2℄,
1
ωo ≈ √
L1 Ce
(2)
Assuming a nearly sinusoidal osillation, the output signal for an osillator an be approximated by
A cos (ωt)
where
A
is the amplitude of osillation. If
the tank iruit has a suiently high quality fator
osillator implementations. Setion III outlines the anal-
(Q > 3)
ysis approah for evaluating the phase noise of an en-
and gate voltages an be approximated by,
this assumption is valid [9℄. The drain, soure
haned swing LC osillator. Setion IV provides the
simulation results and Setion V shows the appliation
Vd = VD − A cos θ;
Vs = −nA cos θ; Vg = VG + kA cos θ
Analysis and Design Optimization of Enhaned Swing CMOS LC Osillators based on a Phasor Based Approah
VD
VD
R1
L1
C1
C1
VG
C2S
R2
L2
0 ≤ θ ≤ θn
(2π − θn ) ≤ θ ≤ 2π . A time varying small-signal
transondutane, gm (θ) and a small-signal output ondutane, gds (θ) for the transistor an be expressed as,
Similarly, it operates in the triode region for
and
Cbias
R1
L1

′W
, linear

k L Vds (θ)
∂Id (θ)
W
′
gm (θ) =
= k L [Vgs (θ) − VT ] , saturation
∂Vgs (θ) 

0
, cut − off
Rbias VG
C2S
R2
L2
3
(5)
(a)
(b)
VD
k=0, ESDC
k=1, XCC
R1
L1
VD-A cos(ωt)
-k
VG +
k.A cos(ωt)

′W

k L [Vgs (θ) − VT ] , linear
∂Id (θ)
gds (θ) =
= λId (θ)
, saturation
∂Vds (θ) 

0
, cut − off
C1 =Ce/(1-n)
(6)
-nA cos(ωt)
C2 =Ce/n
R2
Id (θ), gm (θ)
and
gds (θ)
are periodi and an be
expressed in terms of their Fourier series omponents
ID [nωo ], GM [nωo ]
(c)
Fig. 1 Dierential osillator arhitetures. (a) ESDC osilla-
tor. (b) XCC osillator with a DC bias shift. () Single ended
∞
X
Id (θ) =
equivalent iruit.
and
GDS [nωo ],
respetively. For ex-
ample,
ID [nωo ]ejnθ
(7)
n=−∞
(3)
If
A
is a known quantity, the time-domain wave-
Id (θ), gm (θ) and gds (θ) an be evaluated in
A using Eqs. (3), (4), (5) and (6). ID [nωo ],
GM [nωo ] and GDS [nωo ] an be evaluated analytially,
forms of
θ = ωt
where
of
C2
and it is assumed that the impedane
at the osillation frequeny is muh lower than
the impedane looking into the soure of
M1 .
A areful
design hoie an ensure this.
terms of
as in [9℄. Sine the objetive of our work is to implement a MATLAB based toolbox, the omputational ef-
In a voltage biased osillator, the transistors in the
fort an be redued by evaluating the harmonis nu-
iruit an operate in all three regions: saturation, tri-
merially using the MATLAB FFT funtion [17℄ from
ode and ut-o respetively. Assuming a Level-1 MOS-
the time-domain waveforms of
FET model the transistor urrent an be expressed as,
 ′
k W


[2(Vgs (θ) − VT ) − Vds (θ)]

 2 L

Vds (θ)(1 + λVds (θ))
Id (θ) =
k′ W

 2 L (Vgs (θ) − VT )2 (1 + λVds (θ))



0
where,
k ′ = µn Cox
is a onstant,
VT
and
is the following: if the osillator is operating at reso-
, saturation
, cut − off
(4)
λ
are the
In order to simplify the expressions, two angles
θc
are dened. They signify the saturationut-
o boundary and the triodesaturation boundary, re-
Vgs ≥ VT . This
i
VT −VG
(n+k)A . Similarly, the tran-
spetively. The transistor turns on if
translates to
−1
θc = cos
h
sistor operates in the triode region if
implies
θn = cos−1
h
i
Vgd ≥ VT .
This
VD −(VG −VT )
. Therefore, the MOS(1+k)A
FET operates in the ut-o region for
gds (θ).
boundary onditions [9℄. The rst boundary ondition
, linear
parameter of the transistor, respetively.
θn
and
osillator requires simultaneously solving two sets of
threshold voltage and the hannel length modulation
and
Id (θ), gm (θ)
Evaluation of the osillation amplitude for an LC
θc ≤ θ ≤ 2π − θc .
nane, the load seen at the transistor's drain is purely
resistive at the osillation frequeny. The fundamental
omponent of the drain urrent passes through this resistor and auses the output voltage swing. Therefore,
by following a methodology similar to [9℄, the steady
state amplitude
A
of an ESDC or XCC osillator an
be expressed as,
A = (1 − n)ID [ωo ]Rp
where
Rp
(8)
is the parallel tank resistane given by,
Rp = R1 ||(R2 /n2 )
(9)
This equation is valid under the assumption that
R2
does not onsiderably load the apaitive divider reated by
design.
C1
and
C2 ,
whih an be ensured by a areful
4
Ankur Guha Roy et al.
VD
R1
L1
R2
C2
gm(θ).Vs(θ)
gnr (θ) an be expressed in
terms of
gm (θ) and gds (θ)
as [10℄,
C1
C1
VG
of
gds(θ).Vds(θ)
L1
Rp
n
gm (θ) + gds (θ)
(1 − n)
(12)
If the transistor non-linearity an be expressed as a time
(b)
C2
gnr (θ) = −
varying ondutane
(a)
gnr,eq (θ) aross the the RLC tank
gnr,eq (θ) an be found from
shown in Fig. 2(d) then
Fig. 2() by observing that this ondutane appears
C1
gnr,eq(θ)
L1
C2
C1
gnr(θ)
Rp
L1
C2
(d)
Rp
(c)
Fig. 2 Evaluation of the equivalent negative resistane. (a)
ESDC osillator. (b) gm (θ) and gds (θ). () gnr (θ): equivalent ondutane of the ombination of gm (θ) and gds (θ). (d)
gnr,eq (θ):
saled version of
gnr (θ)
aross a apaitive divider formed by
gnr,eq (θ) = (1 − n)2 gnr (θ)
in Eq. (11) is given by [10℄,
where
Next onsider the seond boundary ondition. In a
urrent biased osillator, the average urrent through
the transistor is determined by the tail urrent soure
[9℄. If the tail urrent soure value is known, the seond boundary ondition an be established by setting
this value equal to the average urrent owing through
the transistor. Enhaned swing osillators are voltage
biased and do not have a xed bias urrent. If a voltage biased osillator is designed suh that the transistor is initially biased in saturation, the amplitude
would inrease progressively. Eventually, the MOSFET
is pushed into the triode region. As the devie spends
more time in the triode region, it introdues an average loss omponent aross the tank. The osillation
amplitude builds up until the point where the power
(modeled by a negative re-
GN R,eq [0] − GN R,eq [2ωo ]
time varying
Rp , Pdiss
.
(14)
nth Fourier oeient of the
ondutane gnr,eq (θ). GN R,ef f inludes
GN R,eq [nωo ]
is the
the loss omponent introdued by the MOSFET in the
triode region of operation.
Aording to Eqs. (5) and (6),
funtions of
A.
As
GN R,ef f
gm (θ)
and
is dependent on
gds (θ) are
gm (θ) and
gds (θ) it is also a funtion of A. If A is a known quantity,
GN R,ef f an be evaluated using the Level-1 MOSFET
equations desribed above.
If the two boundary onditions in Eq. (8) and Eq. (11)
are solved simultaneously the exat value of the amplitude an be determined. However, both
GN R,ef f
are impliitly funtions of
A
ID [ωo ]
and
and annot be
solved analytially. Alternatively these equations an
be solved numerially with the optimization toolbox in
MATLAB. Eqs. (8) and Eq. (11) an be merged into a
single equation,
sistane) is fully ompensated by the power dissipated
through the resistive load
(13)
It an be shown that the eetive ondutane dened
GN R,ef f =
Pnr
C2 . By an
and
in parallel with the RLC
tank.
driven by the transistor,
C1
impedane transformation,
C(A)
as follows,
2
1
C(A) = (A − (1 − n) ID [ωo ]Rp ) + GN R,ef f +
Rp
2
Therefore, the seond boundary ondition is given
by,
(15)
Pdiss = Pnr
(10)
As shown in [10℄, simplifying (10) yields the following result,
C(A)
is zero if Eqs. (8) and (11) are satis-
optimization toolbox of MATLAB omputes
dierent values of
1
= −GN R,ef f
Rp
where
Ideally
GN R,ef f
(11)
is a quantity alled the eetive on-
A. The
C(A) for
ed simultaneously, i.e., the orret value of
C(A)
A
and nds the value of
A
for whih
is zero.
2.2 Amplitude Evaluation for Quadrature Osillators
dutane of the non-linearity.
In the ESDC osillator in Fig. 2(a) there are two
The enhaned swing quadrature (ESQ) osillator shown
gm (θ) and gds (θ) both of whih
in Fig. 3(a) was reported in [3℄ as an extension of the
time varying resistanes
an be evaluated using the Level-1 model as shown in
ESDC osillator for quadrature generation. In [3℄ the
Eqs. (5) and (6). The eet of these two ondutanes
quadrature omponent
an be ombined into a single time varying ondu-
nent
tane
gnr (θ)
as shown in Figs. 2(b) and (). The value
(I)
iruit.
(Q)
leads the in-phase ompo-
and this is ensured by a apaitive oupling
Analysis and Design Optimization of Enhaned Swing CMOS LC Osillators based on a Phasor Based Approah
VD
VG
L1 Rp
Vop
M1 C1
Rbias
Isp
Cqc
The onstants
L2
Qsn
Isn
Cqc
Isp
−1
α1 = tan
Qsp
1−m
1+m
(18)
−1
;
α2 = tan
n − mn
1 + mn
Vgs and Vds are slightly phase
φe ). The fundamental ompoID [ωo ]) is in phase with Vgs and
It an be onluded that
skewed (say by an angle
L1 Rp
M1
Voq
C1
L2
Cic
C2S
Qsp
are given by,
R1 = An (1 + m)2 + (1 − m)2
p
R2 = A (1 + mn)2 + n2 (1 − m)2
VD
VG
α2
and
p
Rbias
Cic
C2S
R1 , R2 , α1
5
nent of
Id
(denoted as
an be expressed as,
ID [ωo ] = |ID [ωo ]| ∠φe
Qsn
Isn
(19)
ID [ωo ] an be evaluated if Vgs (θ) and Vds (θ) are known.
At the osillation frequeny, the resonant tank ir-
(a)
m=
Cqc
C1
; n=
C1+C2
Cqc+Cic
nAsin(ωt)
uit ompensates for
shift,
VD
L1
VQ
Rp
VD-Acos(ωt)
1-m
M1
VG+mnAcos(ωt)
+(1-m)nAsin(ωt)
Z=
-m
C1 =Ce/(1-n)
-nAcos(ωt)
C2 =Ce/n
−φe .
1
Rp
φe
1
+ jωCe +
=r
1
jωL1
= Rp cos (φe ) ∠ − φe
(b)
Fig. 3 ESQ osillator. (a) Arhiteture. (b) Single-ended
where
equivalent iruit representation.
by providing an extra phase
The tank impedane an be expressed as,
1
1
R2p
+ ωCe −
1
ωL1
2 ∠ − φe
(20)
1
φe = tan−1 Rp ωCe −
ωL1
.
From Eqs. (20) and (19) the osillation amplitude
an be approximated by,
The amplitude of an ESQ osillator an be evaluated
by using a single-ended equivalent iruit as shown in
Fig. 3(b).
A = (1 − n) |ID [ωo ]Z| = (1 − n) |ID [ωo ]| Rp cos (φe )
= (1 − n) Re{ID [ωo ]}Rp
To failitate the alulations, two quantities: oupling fator
(m)
and feedbak fator
(n)
(21)
are dened as
ID [ωo ] with Vds ,
|ID [ωo ]| cos (φe ).
The in-phase omponent of
follows:
Re{ID [ωo ]}
diretly gives
i.e.,
Following a methodology similar to the dierential
m=
C1
Cqc
, n=
Cqc + Cic
C1 + C2
(16)
From Fig. 3 it an be seen that if the osillation
amplitude is
A,
then
θc and θn an be dened. The
Vgs ≥ VT and it operates in the triode region if Vgd ≥ VT . These two onditions translate
i
i
h
h
−1 VT −VG
−1 VD −(VG −VT )
to θc = cos
and
θ
=
cos
,
n
R1
R2
osillators, two angles
MOSFET is ON if
respetively. Therefore, the MOSFET operates in the
θc ≤ (θ − α1 ) ≤ 2π − θc . Similarly, the
0 ≤ θ −α2 ≤
(2π − θn ) ≤ (θ − α2 ) ≤ 2π .
ut-o region for
Vgs (θ) =
VG + (mn + n)A cos(θ)
MOSFET operates in the triode region for
θn
+(1 − m)nA sin(θ)
The seond boundary ondition an be formed by
= VG + R1 cos(θ − α1 )
Vgd (θ) =
VG − VD + (m.n + 1)A cos(θ)
+(1 − m)nA sin(θ)
= VG − VD + R2 cos(θ − α2 )
Vds (θ) = VD − (1 − n)A cos(θ)
and
following a similar approah as in Eq. (10). Sine the
(17)
output waveform is
GN R,ef f
A cos(ωo t),
only the real part of
ontributes to power loss.
1
= −Re{GN R,ef f }
Rp
(22)
6
Ankur Guha Roy et al.
Therefore, the ost funtion,
C(A)
in this ontext is obtained from Eqs. (21) and (22) following a similar approah as in Eq. (15) and it is given
VD
VD
for optimization
i2n,R1
R1
L1
i2n,M1
C1
i2n,Rp
Rp
L1
i2n,M1
C1
by,
2
M1
(A − (1 − n) .Re{ID [ωo ]}.Rp )
2
C(A) =
1
+ Re{GN R,ef f } +
Rp
As in the dierential osillators
mized in terms of
A
C(A)
M1
(23)
R2
i2n,R2
L2
C2
C2S
an be opti-
to get an aurate estimate of
A.
Fig. 4 Output noise soures in the single-ended equivalent
iruit of the enhaned swing osillators (ESDC, XCC, ESQ).
3 Phase Noise Analysis of A Low Voltage,
Enhaned Swing LC Osillator
and
The most popular approah to derive an analytial phase
noise model of an osillator is the linear time varying
(LTV) analysis. There have been several LTV analysis
based models reported in literature [5,10℄. Among these
the impulse sensitivity funtion (ISF) based model [5℄
is a popular one. An ISF based approah using simulations an be applied for enhaned swing osillators.
However, to redue the omputational eort, the phasor
results alulated in the last setion (GM [nωo ],
and
ID [nωo ])
n is the feedbak fator dened in Eq. (1), ion,M1
ion,Rp are the ontributions of in,M1 and in,Rp to
where
GDS [nωo ]
an be exploited for evaluating the phase
noise.
In our approah the analysis of [13℄ was used and
the output node, respetively.
The noise ontribution of
M1
an be modeled as a
urrent-noise soure between the soure and the drain.
This noise soure has thermal and iker noise omponents.
i2n,M1 = i2n,thermal + i2n,f licker
(25)
The time varying thermal noise power spetral density (PSD) an be expressed as a urrent noise between
the drain and the soure of a transistor,
i2n,thermal (θ) = 4kT γgm(θ) + 4kT gds(θ)
= 4kT γg(θ)
has been generalized to voltage biased osillators. Fur-
(26)
thermore, the thermal and iker noise ontributions
from the transistor operating in saturation, triode and
where
γ
is the exess noise fator of the transistor,
the Boltzmann's onstant,
ut-o regimes is inluded.
If the osillator is used as a voltage ontrolled os-
ture and
g(θ)
g(θ) = gm (θ) +
PM onversion. The exat AM-PM onversion mehanism and its alulation was reported in [18℄. In order
to simplify the proedure, this eet is negleted in the
Assuming
k
is
is the absolute tempera-
is dened as,
illator (VCO), the additional varator may introdue
additional phase noise at the osillator output by AM-
T
gds (θ)
γ
(27)
γ ≈ 1,
subsequent analyses. However, the analysis an be ex-
g(θ) ≈ gm (θ) + gds (θ)
tended to inlude AM-PM onversion. The assumption
For a Level-1 MOSFET model,
(28)
that the AM-PM onversion is not the dominant noise
ontributor for a voltage biased osillator was shown
in [19℄.
There are three noise generators in the single ended
equivalent iruit of the ESDC, XCC and ESQ osilla-
M1 . The noise soures are shown in
Fig. 4. The eet of R1 and R2 an be ombined into
a single equivalent resistane Rp as dened in Eq. (9).
The ontributions of noise soures in,Rp and in,M1 to
tors:
R1 , R2
and
the output urrent noise through the tank an be evaluated by using a Norton equivalent iruit.
ion,M1
= 1;
in,Rp
ion,Rp
= (1 − n)
in,M1
gm (θ)|triode
≪ gds (θ)|triode
gds (θ)|saturation ≪ gm (θ)|saturation
(29)
gm (θ)|saturation ≈ gds (θ)|triode
whereby,
g(θ) =
(
k′ W
L [Vgs (θ) − VT ]
0
on
cut − off
The approximate expression of
g(θ)
(30)
in Eq. (28) devi-
ates from the atual value in Eq. (27) depending on the
(24)
value of
γ.
When the transistor operates in the satura-
tion region, the two expressions yield the same result.
Analysis and Design Optimization of Enhaned Swing CMOS LC Osillators based on a Phasor Based Approah
In the triode region the two expressions dier by the
γ . γ usually varies between 23 to 1.1, depending
on the hannel length. The thermal noise expression of
g(θ)
Eq. (26) with
gnorm(θ)
g(θ)
fator
gmax
1
t
approximated by Eq. (30) an thus
overestimate the noise by
10 log(γ) ≈ 1.6 dB
t
in
in the tri-
in
ode region. However in an osillator, the MOSFET pe-
gnorm(θ)
in2=4kTγg(θ)
riodially operates from saturation, triode, to ut-o
and vie versa. The transistor spends only a fration of
in2=4kTγgmax
(a)
Thermal Noise Spectrum
the overall time period in the triode region [20℄. Therefore, the thermal noise estimation error would be muh
smaller than
2kTγ/gmax
1.6 dB.
∆ω
A periodially time varying noise soure an be modeled as a stationary noise soure whih is modulated by
a periodi time varying waveform. If
maximum values
7
∆ω
ω
nωο
-nωο
g(θ) and Id (θ) have
Gnorm[nωο]
gmax and Id,max respetively, then the
modulating waveforms for the thermal noise and iker
g(θ)
and Id,norm (θ) =
noise soures are gnorm (θ) = g
max
Id (θ)
Id.max , respetively. The stationary urrent noise soures
kf licker Id,max
respewere modeled as 4kT γgmax and
fα
tively. Id,max is the maximum urrent owing through
the MOSFET.
ω
-(n−1)ωο
(n+1)ωο
Fourier Series of gnorm(θ)
(b)
Fig. 5 (a) Modeling a time varying noise soure as a sta-
tionary noise soure modulated by a periodi waveform. (b)
Mixing of noise by the modulating waveform.
The modeling of a time varying noise soure by
an equivalent stationary noise soure modulated by a
periodi time varying waveform is shown in Fig. 5(a).
the soure of the MOSFET an be expressed as,
The noise modulation proedure in the time domain
an be viewed as a onvolution in the frequeny do-
kf licker Id,max 1
2
|ID,norm [−ωo ] + ID,norm [ωo ]|
fα
4
kf licker 1
2
|ID [−ωo ] + ID [ωo ]|
=
Id,max f α 4
i2n,f licker =
main. Any periodi signal an be expressed as a omth
bination of its Fourier series omponents. Let the n
gnorm (θ) and Id,norm (θ) be
Gnorm [nωo ] and ID,norm [nωo ]. A stationary white noise
harmoni omponents of
soure has noise omponents at all possible frequen-
(nωo ± ∆ω). These omponents are onvolved by Gnorm [(n − 1)ωo ] and Gnorm [(n + 1)ωo ] and
are shifted to (ωo ± ∆ω) [13℄. Fig. 5(b) illustrates this
ies inluding
onept. Sine the thermal noise soure is white, all
harmoni omponents of
gnorm (θ)
ontribute to phase
(32)
This extra
1/4 fator in
The noise soure values in Fig. 4 are,
i2n,M1 = Ief f
noise through this mehanism.
The SSB urrent noise spetral density at
kf licker
+ 4kT γGef f
fα
=
n=1
|Gnorm [(n − 1)ωo ]
4kT
Rp
where
Gef f =
i2n,thermal
=
(33)
as [13℄,
∞
X
; i2n,Rp
(ωo + ∆ω)
due to all of the harmoni omponents an be expressed
4kT γgmax
Eq. (32) takes into aount the
orrelation of dierent sidebands [13℄.
Ief f
2
1
gmax
∞
X
n=1
|G[(n − 1)ωo ] + G[(n + 1)ωo ]|2
1
|ID [−ωo ] + ID [ωo ]|2
=
Id,max 4
1
(34)
+Gnorm [(n + 1)ωo ]|
=
4kT γ
gmax
∞
X
n=1
Using Eq. (24) the total output urrent noise is given
2
|G[(n − 1)ωo ] + G[(n + 1)ωo ]|
by,
2
(31)
i2o,noise = i2n,M1 (1 − n) + i2n,Rp
(35)
This output noise urrent ows through the tank
Similarly, the eetive translated iker noise urrent to the output at
(ωo + ∆ω) between the
drain and
iruit and gets onverted to voltage noise. If the tank
has a quality fator
Q,
the output impedane of the
8
Ankur Guha Roy et al.
tank iruit at an oset frequeny
ωo
∆ω
from the arrier
Z(ωo + ∆ω) ≈
iruit sine the individual noise soures are unorrelated. Therefore, the nal phase noise expression for
an be approximated by,
the dierential osillator iruit an be expressed as,
jRp ωo
2Q∆ω
(36)
where the tank quality fator at the osillation fre-
L{∆ω}|differential = 10 log
2
vo,noise,P
M
A2 /2
!
−3
(41)
queny is,
Q=
The analysis of the phase noise desribed above has
Rp
ωo L1
(37)
been derived in terms of the time varying funtion
g(θ)
given by, Eq. (30) in the thermal noise dominated re-
The output voltage noise power spetral density is,
2
= i2o,noise
vo,noise
Rp2 ωo2
4Q2 ∆ω 2
gion.
g(θ) depends only on the gate-soure voltage (Vgs (θ)).
Therefore, the phase noise expression in Eq. (41) an be
!
(38)
used for ESDC, XCC and ESQ osillators with the required modiations in
Vgs (θ)
to aount for the noise
R1
R2 remain unhanged for all the arhitetures. How-
eets of the MOSFET. The noise ontributions of
The voltage noise gets onverted to phase noise by
a non-linear mehanism [21, 22℄. It is assumed that only
and
ever, unlike the ESDC osillator, the XCC and ESQ
half of the total voltage noise power ontributes to the
osillators have an extra noise generator: the bias shift-
output phase noise. This is ommonly known as the
ing resistane
equi-partition theorem [5℄. The equi-partition theorem
sign hoie of
usually holds for white thermal noise. For slow fre-
output phase noise eventually making it onsiderably
queny noise soures suh as
1/f
noise, the ontribution
(Rbias ) as shown
Rbias an redue
in Fig. 1. A areful deits ontribution to the
less than the other noise generators. To understand the
of the time varying iker noise to the output phase
design trade-os, we need to examine how the
noise depends on the osillator arhiteture. An exat
noise aets the iruit's noise response.
proedure to nd the iker noise ontribution to the
the output phase noise in two ways. At high frequen-
output phase noise for a voltage biased ross-oupled
ies this resistane eetively appears in parallel with
osillator using an ISF based analysis was presented
Rp .
in [19℄. Although this method an be extended for en-
than
Rbias
Rbias an aet
haned swing osillators, the purpose of our analysis
Rbias is hosen one order of magnitude higher
Rp , its ontribution to the output noise an be negleted. At low oset frequenies, Cbias (Cic and Cqc for
is to get a fast estimation of the output phase noise
the ESQ osillator in Fig. (3)) ats like an open iruit.
within an error margin. For the osillator arhitetures
disussed in this paper, the equi-partition assumption
overestimates the output phase noise within a
3 dB
a-
uray in the iker noise dominated region. A similar
approah was used in [13℄.
The voltage noise ontribution to the output signal
phase is thus expressed as,
2
vo,noise,P
M =
If,
Rbias is not onneted to Rp . Thermal noise generRbias near d an be translated to the output
phase noise by modulation of the time varying gm (θ)
of the transistor. If Cbias (Cic and Cqc ) is hosen sufiently high, the noise generated by Rbias at lose-in
So,
ated by
oset frequenies is ltered out and its eet to the output is negligible. Therefore, suiently large values of
1
kf licker
2
+ 2kT γGef f (1 − n)
Ief f
2
fα
!
Rp2 ωo2
2kT
.
+
Rp
4Q2 ∆ω 2
(39)
The phase noise expression of the single-ended equiv2
vo,noise,P
M
with respet to the osillation amplitude,
alent iruit an be obtained by normalizing
Rbias
and
Cbias
ensure that the phase noise expression
in Eq. (41) holds for XCC and ESQ osillators without
any modiation.
4 Analysis Veriation With Simulation
Results
All of the osillators disussed in Setions II and III
were designed with a 5.5 GHz enter frequeny. In this
setion their amplitude and phase noise harateristis
L{∆ω}|single−ended = 10 log
2
vo,noise,P
M
A2 /2
!
3 dB
(40)
are disussed.
The seleted omponent values of the ESDC osillator are shown in Table 1. These values were hosen in
less noise
order to ompare it with the osillator reported in [2℄
ompared to this single-ended phase noise equivalent
whih was fabriated in an IBM130 RF-DM proess.
The dierential osillator iruit has
Analysis and Design Optimization of Enhaned Swing CMOS LC Osillators based on a Phasor Based Approah
9
Bsim3v3 model
Level−I model approximated by 10 harmonics
40
6
[mS]
ds
m
d
2
20
10
g
g [mS]
30
4
I [mA]
60
40
20
0
0
0
5
Phase, w t [rad]
o
(a)
10
0
−10
0
5
Phase, w t [rad]
o
(b)
10
0
5
Phase, w t [rad]
o
(c)
10
Fig. 6 Waveforms of the small-signal time varying omponents and their approximation with the rst 10 harmonis. (a)
gm (t).
(b)
()
For both the ESDC and XCC osillators, the pre-
Table 1 Component Values and Extrated Parameter Val-
ues
dited amplitude is within
Component
Value
Name
L1
L2
C1
C2S
R1
“ R
”2
W
L
MOS
Id (t).
gds (t).
Model
Value
12 % of
the simulated value.
From the plots, it is seen that the XCC osillator has a
Parameter
higher amplitude ompared to the ESDC osillator for
0.69 nH
1.25 nH
1.858 pF
2.704 pF
450 Ω
550 Ω
VT n
k′ = (µn Cox )
λ
γ
kf licker
α
0.21 V
410 µA/V2
0.46 V−1
1.55 × 10−13 A
0.86
80 µm
0.24 µm
-
-
the same bias onditions.
The predited amplitude of ESQ osillator is within
16 %
1.14
of the simulation results. This behavior an be
cgs and cgd of the transistors. The
oupling apaitors Cqc and Cic in Fig. 3 form a potential divider with cgs and cgd . This redues the signal
attributed to the
swing at the gate of the transistors. This swing reduThe extrated transistor parameters from the BSIM3v3
MOSFET model are also shown in the table.
For a diret omparison, the XCC osillator was de-
tion at the gate also redues the eetive transondutane
gm (θ)
of the transistor and onsequently redues
the amplitude of osillation.
signed with the same omponent values as the ESDC osillator. The extra resistor (Rbias ) and apaitor (Cbias )
in the level-shifter path were hosen to be
100 kΩ
and
5 pF, respetively. The ESQ osillator was designed with
the same omponent values as the ESDC osillator. The
Cic and Cqc in Fig. 3 were hosen as
500 fF and Rbias = 1 kΩ. The dierential and quadrature osillators were simulated for VG = 300 mV and
VD = 500 mV. The Id , gm and gds waveforms for the
oupling apaitors
ESDC osillator are shown in Fig. 6.
It is seen from Fig. 6 that harmonis above the
10
The phase noise of the three osillators was alulated
using Eq. (41). The analysis and simulated values of
phase noise for the three osillators are shown in Fig. 8.
In all ases the phase noise in both the thermal and
iker noise dominated regions is predited with an auray of
10 terms for all pratial
purposes.
3 dB.
The XCC osillator shows approximately 2.5 dB bet-
th
harmoni an be negleted. Therefore, the series in Eq. (34)
an be trunated after the rst
4.2 Phase Noise Results
ter phase noise performane than the ESDC osillator
in the thermal noise dominated region.
The phase noise of the ESDC osillator at a
3 MHz
n is
oset frequeny for a xed gate bias and varying
shown in Fig. 9. The gate bias is kept suiently high
4.1 Amplitude Results
(at
400 mV
for all simulations) to ensure start-up for
all possible values of
n.
The observed trend of phase
Spetre simulated amplitude results with the BSIM3V3
noise in this gure is monotonially dereasing. A simi-
transistor model were ompared to the analytial re-
lar trend an be seen from the phasor based analysis in
sults. The omparisons are shown in Figs. 7(a), (b) and
Setion III. Fig. 9 shows that the phase noise minimum
().
for a urrent biased Colpitts osillator at a feedbak fa-
10
Ankur Guha Roy et al.
Spectre Sim, VG=300 mV
Spectre Sim, V =300 mV
G
1.4
Spectre Sim, VG=400 mV
Spectre Sim, VG=500 mV
1.2
Analysis, V =300 mV
G
Analysis, VG=400 mV
1
Spectre Sim, VG=500 mV
Analysis, VG=300 mV
0.8
Analysis, VG=500 mV
1
0.45
0.5
0.55
Supply Voltage [V]
0.6
Spectre Sim, V =500 mV
G
Analysis, VG=300 mV
Analysis, VG=400 mV
Analysis, V =500 mV
G
1
0.8
0.8
0.6
0.4
Spectre Sim, VG=400 mV
1.2
Analysis, VG=400 mV
1.2
Analysis, VG=500 mV
Spectre Sim, VG=300 mV
1.4
Spectre Sim, VG=400 mV
Oscillation Amplitude [V]
Oscillation Amplitude [V]
Oscillation Amplitude [V]
1.4
0.4
0.45
0.5
0.55
Supply Voltage [V]
0.6
0.6
0.4
0.45
0.5
0.55
Supply Voltage [V]
(c)
(b)
(a)
0.6
Fig. 7 osillator output amplitude variation with supply voltage for dierent gate biases. (a) ESDC. (b) XCC. () ESQ.
−60
−80
−100
−120
−140
1k
100k
Frequency [Hz]
Analysis Result
Spectre Simulation
−60
−80
−100
−120
−140
10M
1k
100k
Frequency [Hz]
(a)
−40
Phase Noise [dBc/Hz]
−40
Analysis Result
Spectre Simulation
Phase Noise [dBc/Hz]
Phase Noise [dBc/Hz]
−40
Analysis Result
Spectre Simulation
−60
−80
−100
−120
−140
10M
1k
(b)
100k
Frequency [Hz]
10M
(c)
Fig. 8 Phase noise for dierent osillator arhitetures. (a) ESDC. (b) XCC. () ESQ.
tor,
n ≈ 0.3
reported in [4℄ does not hold for a voltage
−80
Analysis Result
Spectre Simulation
−126
−128
−130
Phase Noise [dBc/Hz]
Phase Noise @ 3MHz Offset [dBc/Hz]
−124
Measured data
Analysis result
−70
biased Colpitts osillator.
−90
1/f3 noise region:
−83 dBc/Hz @ 20kHz offset
−100
2
1/f noise region:
−135.7 dBc/Hz @ 3 MHz offset
−110
−120
−130
−140
−132
−150
−134
10k
−136
−138
0.2
100k
1M
Frequency [Hz]
10M
Fig. 10 Measured test-hip results of the ESDC osillator
0.3
0.4
0.5
Feedback Factor, n
0.6
with VD
analysis.
= 500 mV, VG = 300 mV
and omparison with the
Fig. 9 Phase noise at 3 MHz oset frequeny with dierent
feedbak fators for the ESDC osillator.
The phase noise results of the ESDC osillator with
5 Design Example
To demonstrate the appliation of the proposed analysis
this analysis mathes well with the fabriated hip re-
as a useful design tool, an ESDC osillator with the
sults in [2℄ shown in Fig. 10.
following speiations has been designed:
Analysis and Design Optimization of Enhaned Swing CMOS LC Osillators based on a Phasor Based Approah
Center frequeny (fo ) = 5.5 GHz;
of 4 mW, the value of
Power onsumption (Pdc )
suitable point from this graph has to be seleted that
Phase Noise 1 MHz
ensures proper start-up of the osillator. Any point in-
≤ 4 mW;
oset ≤ −122 dB/Hz;
The amplitude and phase noise expressions evaluated
in the previous setions an be used to determine the
average power onsumed in an ESDC osillator and it
is given by,
where
I(t)
should be between
side the shaded region has a loop gain
Figure-of-Merit (FoM): Highest possible.
(42)
0.2 − 0.5.
<1
A
and has to
be avoided. The phase noise performane for dierent
W
values of n and
L are shown in Fig. 12(b). n = 0.2 is
exluded sine it does not give an adequate phase noise
n should be hosen within the
W
There are multiple ombinations of L
values that satisfy the design requirement. The
performane. Therefore,
range
Pdc = 2VD I(t)
n
11
and
n
0.3 − 0.5.
best design hoie would be to use the most eient
is the average urrent through eah transis-
tor in the ESDC osillator.
The FoM of an osillator is a measure of its eieny to onvert the d power to the arrier power. It
up gain
is dened as [4℄,
F oM = 20 log
osillator among all possible options. Fig. 12() shows
that the osillator
has the highest FoM for n ≈ 0.4 with
40 µm
W
L ≈ 1.6 0.24 µm . In order to ensure suient start-
fo
∆f
− 10 log
Pdc
1 mW
W
L
=2
transistor size is
− L{∆f }
(43)
A higher FoM osillator has a higher eieny.
For start-up of any osillator, the loop gain (LG) of
the osillator should be higher than unity. To aount
40 µm
0.24 µm
≈ 2.5.
was hosen. The LG for this
The degradation of the FoM
with a larger transistor size is nominal as seen from
Fig. 12(). The optimal design values for
C1
2.02 pF and 3.03 pF, respetively. These
to (within 10 %) the design hoies of
are fairly lose
and
C2
are
[2℄. Therefore,
this analytial model an be used to searh through
LG > 2 is seleted.
the design spae muh faster than using iruit simula-
The detailed start-up analysis for an ESDC osillator
tions. For omparison, the MATLAB ode of the pro-
was derived in [2℄. For larity the nal result is shown
posed algorithm was run on a PC with 2.8 GB RAM
below:
and an Intel Quad Core 2.5 GHz Proessor. The Spe-
for the PVT variations, in pratie a
treRF PSS and PNOISE analysis for all 66 data points
3
LG(jω) =
gm ω L1 L2 C1
B(ω)
(44)
4.3 minutes.
Therefore,
tation an work as a valuable design assistant for a os-
−ω L1 L2 [G1 C1 + G1 C2 + (gm + G2 )C1 ]
illator designer and it an be used to rapidly nd out
the optimal design parameters. This design proedure
(45)
G1 and G2 are the equivalent parallel ondutanes of
L1 and L2 , respetively at the osillation frequeny, gm
is the transondutane of the transistor at the d operating point. The design proedure is summarized in
Fig. 11 as a ow-hart.
L1
an be designed with an ele-
tromagneti solver/optimizer suh as ASITIC [23℄. As
disussed in [2℄,
L1 .
whereas the MATLAB ode
the analysis model and its MATLAB based implemen-
3
+ω[L1 G1 + L2 (gm + G2 )]
than
66 minutes
produed omparable results in
where
B(ω) =
in Fig. 12 took
L2
should be hosen suiently higher
In order to verify the design hoies of [2℄, the
same values of
L1
and
L2
L1 = 690 pH,
1
frequeny, G1 =
450 S
are used, i.e.,
L2 = 1.25 nH. At the osillation
1
and G2 = 550 S. The total equivalent
is 1.21 pF.
tank apaitane
an be further automated by augmenting the existing
tool with a numerial optimization loop as in [14, 15℄.
The proposed design method an be a very eetive design tool if it is used along with a spae mapping based algorithm [24℄. The spae mapping algorithm simplies an optimization proedure by mapping
a omputationally intensive problem to a simplied problem and running the optimization over the simplied
problem. A level-I MOSFET model based analysis an
be used for rening the optimization proedure of a
more sophistiated and omputationally intensive BSIM3V3
model based approah, used in a iruit simulator.
Following the method desribed in Fig. 11, the tran40 µm
200 µm
0.24 µm to 0.24 µm
and the feedbak fator, n, was varied from 0.2 to 0.6.
6 Conlusion
The predited power, phase noise and FoM plots for
W
dierent values of n with varying
L values are shown
in the Figs. 12(a), (b) and (), respetively. It is evident
determining the amplitude and phase noise of CMOS
from Fig. 12(a) that for a maximum power onsumption
analysis has been desribed.
sistor dimensions were varied from
A generalized analysis tehnique has been developed for
low voltage osillator topologies. An osillator design
approah for optimal osillator design based on this
12
Ankur Guha Roy et al.
1
n=0.6
7
n=0.5
6
n=0.4
5
4
n=0
0.3
n=0.3
3
n=0.2
n=0
0.2
2
1
Phase Noise [dBc/Hz]
Power Consumption [mW]
8
-118
195
-120
194
n=0.2
-122
n=0.3
-124
n=0.4
FoM [dBc/Hz]
Fig. 11 Design ow-hart.
n=0.5
-126
n=0.4
n=0.5
193
n=0.3
192
191
no start-up
start up
1.2 1.6
2 2.4 2.8 3.2 3.6 4 4.4 4.8
Transistor Scaling Factor X[W/L]
(a)
-128
1.2 1.6
2 2.4 2.8 3.2 3.6 4 4.4 4.8
Transistor Scaling Factor X[W/L]
(b)
Fig. 12 Variation of (a) Power, (b) Phase Noise, and () FoM with
190
1.2 1.6
2 2.4 2.8 3.2 3.6 4 4.4 4.8
Transistor Scaling Factor X[W/L]
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