From last lecture TDDC05: Embedded Systems • How did the Mealy composition example work out? Simulation and Verification Lecture 3: Modelling, synchronous languages Simin Nadjm-Tehrani • Problems with definition of new operators? • This lecture: Wrapping up modelling… Real-time Systems Laboratory Department of Computer and Information Science Embedded systems simulation and verification Linköping university 21 pages Spring term 2006 Earlier … Embedded systems simulation and verification Linköping university 2 of 21 Spring term 2006 Example: functional model Landing gear controller: • • • • Architectural (component) Functional (input - output) Behavioural (over ”time”) Non-functional – dependability: reliability, safety, availability, maintainability,... – timeliness, • Other (size, weight, shape, cost, ...) Embedded systems simulation and verification Linköping university 3 of 21 Spring term 2006 Example: behavioural model Closing Opening Idle g2 – g3 ↔ closed ∨ [7] ∨ [4] g8 g5 Extending Embedded systems simulation and verification Linköping university • Where the guards (transition conditions) are: – g2 ↔ (¬cmd ∧ ([8] ∨ [2])) ∨ (cmd ∧ ([9] ∨ [3]) ) g4 g6 4 of 21 Spring term 2006 – g1 ↔ open ∨ [7] ∨ [1] g3 g1 Embedded systems simulation and verification Linköping university – g4 ↔ (cmd ∧ ([8] ∨ [5])) ∨ (¬ cmd ∧ ([9] ∨ [6]) ) g7 Retracting 5 of 21 Spring term 2006 – g5 ↔ out ∨ [9] ∨ [7] ... Embedded systems simulation and verification Linköping university 6 of 21 Spring term 2006 • And where conditions [k] are given by: Timed model g1 [l, u] – [2] ↔ ¬ open ∧ closed ∧ ¬in ∧ out g8 g5 – [9] ↔ ¬ open ∧ ¬ closed ∧ in ∧ ¬ out Parallelism Communication between subsystems Hierarchy Timing Data-flow/control-flow oriented Discrete/continuous state g7 Retracting Extending 7 of 21 Spring term 2006 Embedded systems simulation and verification Linköping university Expressiveness of language Embedded systems simulation and verification Linköping university g4 g6 – [8] ↔ ¬ open ∧ ¬ closed ∧ ¬ in ∧ out • • • • • • g3 Idle g2 – [3] ↔ ¬ open ∧ closed ∧ in ∧ ¬ out ... Embedded systems simulation and verification Linköping university Closing Opening – [1] ↔ ¬ open ∧ closed ∧ ¬in ∧ ¬out 8 of 21 Spring term 2006 Discrete models Example language/tool: • Untimed, parallel, hierarchical, synchronous – State-based (control-flow): Statecharts/STATEMATE – Block diagrams (Data-flow): Lustre/SCADE 9 of 21 Spring term 2006 Statemate model Embedded systems simulation and verification Linköping university 10 of 21 Spring term 2006 Simple example in Lustre node Stopwatch (start-stop, reset, hs: bool) returns (time: int; running: bool); let time = 0 -> if hs and running then pre(time) + 1 else if reset then 0 else pre(time); running = false -> if start-stop then not pre(running) else pre(running); tel Embedded systems simulation and verification Linköping university 11 of 21 Spring term 2006 Embedded systems simulation and verification Linköping university 12 of 21 Spring term 2006 Reactive systems • Conceptual notion • C.f. transformational systems that produce a result when the execution terminates • Reactive systems maintain a continuous interaction with their environments Embedded systems simulation and verification Linköping university 13 of 21 Spring term 2006 Compare with feedback • Consider a one-place buffer and a twoplace buffer as transformational programs • They are equivalent wrt the function • Are they equivalent if their outputs are fed in as inputs? Embedded systems simulation and verification Linköping university Some desirable properties 14 of 21 Spring term 2006 What is desirable here? • Abstraction: do not fix time granularity until very final stages of implementation • Causality: an event should not be able to trigger itself Not A /B B/A A/B B/A • Consistency: transitions taken in a step are not disabled by parallel transitions Embedded systems simulation and verification Linköping university 15 of 21 Spring term 2006 Embedded systems simulation and verification Linköping university Verification in Lustre 16 of 21 Spring term 2006 Environment models The bright side ☺ • Causality, determinism, consistency: dealt with by the compiler • Mode-automata combine automata states (for modes) with Lustre (for data flow in each mode) • Connections to formal verification and optimisation tools Mathematical approximations Embedded systems simulation and verification Linköping university 17 of 21 Spring term 2006 Embedded systems simulation and verification Linköping university 18 of 21 Spring term 2006 Which environment? Wrapping up: modelling • Many formal and informal modelling notations • This course treats – Informal notations for req. spec. – Formal language for design spec. • Lustre/SCADE • With Mealy machines as underlying semantics – Formal language for spec. of static reqs. (Next two lectures) Embedded systems simulation and verification Linköping university 19 of 21 Spring term 2006 Future: Components • Need not build from scratch • Design flow is changed Capture Specify Design Implement Find Test Select Maintain Adapt Deploy Compose Replace Embedded systems simulation and verification Linköping university 21 of 21 Spring term 2006 Embedded systems simulation and verification Linköping university 20 of 21 Spring term 2006