Lecture 11
Digital Circuits (I)
THE INVERTER
Outline
• Introduction to digital circuits
–The inverter
• NMOS inverter with resistor pull-up
Reading Assignment:
Howe and Sodini; Chapter 5, Sections 5.1-5.3
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1. Introduction to digital circuits: the inverter
In digital circuits, digitally-encoded information is
represented by means of two distinct voltage ranges:
V
VMAX
logic 1
VOH
VOL
undefined �
region
logic 0
VMIN
The Static Definition
•
Logic 0:
VMIN V VOL
•
Logic 1:
VOH V VMAX
•
Undefined logic value: VOL V VOH
Logic operations are performed using logic gates.
Simplest logic operation of all: inversion inverter
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Ideal inverter
OUT=IN
IN
IN
OUT
0
1
1
0
Circuit representation and ideal transfer function:
VOUT
v+
V+
+
+
VIN
VOUT
-
-
VOUT=VIN
V+
2
0
0
+
V�M= V
2
V+ VIN
Define switching point or logic threshold :
•
VM input voltage for which VOUT = VIN
– For 0 VIN < VM
– For VM < VIN V+
VOUT = V+
VOUT = 0
Ideal inverter returns well defined logical outputs (0 or
V+) even in the presence of considerable noise in VIN
(from voltage spikes, crosstalk, etc.)
signal is regenerated!
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“Real” inverter
VOUT
logic 1
VMAX
VOH
slope=-1
transition �
region
logic 0
VOL
VMIN
0
0
V+
VIN
In a real inverter, valid logic levels defined as follows:
•
Logic 0:
– VMIN output voltage for which VIN = V+
– VOL smallest output voltage where slope = -1
•
Logic 1:
– VOH largest output voltage where slope = -1
– VMAX output voltage for which VIN = 0
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Two other important voltages:
VOUT
VMAX
VOH
logic 1
slope=-1
undefined �
region
logic 0
VOL
VMIN
0
0
VIL
VIH
V+
VIN
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Define:
VIL smallest input voltage where slope = -1
VIH highest input voltage where slope = -1
If range of output values VOL to VOH is wider than the
range of input values VIL to VIH, then the inverter
exhibits some noise immunity. (|Voltage gain| > 1)
Quantify this through noise margins.
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Chain of two inverters:
noise
M
N
VOUT
VOH
VOL
VIN
NMH
VIH
VIL
NML
inverter M�
output
inverter N�
input
Define noise margins:
NMH VOH - VIH
NML VIL - VOL
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noise margin high
noise margin low
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Simplifications for hand calculations:
Logic levels and noise margins
It is hard to compute points in transfer function with
slope = -1.
Approximate in the following way:
VOUT
VOH=VMAX
slope= Av
VOUT=VIN
VM
VOL=VMIN
0
•
•
0
VIL VM VIH
V+
VIN
Assume VOL VMIN and VOH VMAX
Trace tangent of transfer function at VM
– Slope = small signal voltage gain (Av) at VM
•
•
VIL intersection of tangent with VOUT = VMAX
VIH intersection of tangent with VOUT = VMIN
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Transient Characteristics
Inverter switching in the time domain:
VIN
VOH
90%
50%
10%
0
VOL
tPHL
VOUT
t
tF
tR
tPLH
VOH
90%
50%
10%
0
tF
VOL
t
tR
tCYCLE
rise time between 10% and 90% of total swing
tR
tF
fall time between 90% and 10% of total swing
tPHL propagation delay from high-to-low between
50% points
tPLH propagation delay from low-to-high between
50% points
Propagation delay:
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tP =
1
(t PHL + t PLH )
2
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Simplifications for hand calculations:
Propagation delay
•
•
Consider input waveform is an ideal square wave
Propagation delay times = delay times to 50% point
VIN
VOH
tCYCLE
VOL
t
VOUT
tPHL
tPLH
VOH
VOH
50%
tCYCLE
VOL
t
• SPICE essential for accurate delay analysis
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2. NMOS inverter with “pull-up” resistor
V+=VDD
R
IR
ID
VIN
VOUT
CL
load capacitance
(from following�
stages)
Essential features:
•
•
VBS = 0 (typically not shown)
CL summarizes capacitive loading of the following
stages (other logic gates, interconnect lines, etc.)
Basic Operation:
•
If VIN < VT, MOSFET is OFF
– VOUT = VDD
•
If VIN > VT, MOSFET is ON
– VOUT small
– Value set by resistor / nMOS divider
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VDD
+
R
IR VR
-
VOUT
ID
VIN
Transfer function obtained by solving:
IR = ID
Can solve graphically: I–V characteristics of load:
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Overlap I–V characteristics of resistor pull-up on I–V
characteristics of transistor:
load line
IR=ID
VGS=VDD
VDD
R
VGS=VIN
VGS=VT
0
0
VDD
VDS =VOUT
Transfer function:
VOUT=VDS
VDD
�
0
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0
VT
VDD
Lecture 11
VIN=VGS
12
Logic levels:
VOUT=VDS
VMAX=VDD
�
VOUT=VIN
VM
VMIN
0
0
VT
VM
VDD
VIN=VGS
For VMAX, transistor is cut-off, ID = 0:
VMAX = VDD
For VMIN, transistor is in linear regime; solve:
W
V
V VMIN
μn Cox VDD MIN VT VMIN = IR = DD
L
2
R
ID =
For VM, transistor is in saturation; solve:
ID =
W
V VM
2
μn Cox (VM VT ) = I R = DD
2L
R
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Noise Margins:
VOUT=VDS
VMAX=VDD
�
VOUT=VIN
Av
VMIN
0
0
VDD
VT
VIN=VGS
Small signal equivalent circuit model at VM
(transistor in saturation):
R
D
G
+
+
vin
vgs
-
-
+
gmvgs
-
Av =
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vout
-
S
+
vin
ro
+
gmvin
(ro//R) vout
-
v out
= g m(ro // R) g mR
vin
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What did we learn today?
Summary of Key Concepts
• Logic circuits must exhibit immunity to noise in the
input signal
– Noise margins
• Logic circuits must be regenerative
– Able to restore clean logic values even if input is
noisy.
• Propagation delay: time for logic gate to perform
its function.
• Concept of load line: graphical technique to
visualize transfer characteristics of inverter.
• First-order solution (by hand) of inverter figures-of
merit easy if regions of operation of transistor are
correctly identified.
• For more accurate solutions, use SPICE (or other
CAD tool).
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