Name:________________________
PHGN/CHEN/MLGN435/535 Pre-Lab #8 – Solutions
Topics: Ohmic contacts, interconnects, planarization, metal liftoff
Reading: Campbell 15.7-15.10, 11.9
We have done fairly simple contact and device interconnection processes in class, but this
part of making integrated circuits can be more important than device designs itself. We’ll
just touch briefly on some of these issues here.
In addition, it is very important to learn about metal liftoff, as this is a process step we
haven’t had a chance to practice yet in Modules 1-6. Liftoff is likely how you’ll pattern
your metal contacts in your MOSFET design.
1. What is the difference between an Ohmic contact and a Schottky contact? How would
you achieve one vs. the other in a process?
A Schottky contact is a rectifying contact, meaning that current flow across the metalsemiconductor junction does not vary linearly with voltage. An Ohmic contact, on the
other hand, is a low resistance junction which has a linear current flow with voltage
across the junction.
The type of contact achieved depends on the metal and doping type. To make an Ohmic
contact to a p-type wafer, a metal with a workfunction greater than that of the
semiconductor must be chosen. If it is less than the semiconductor workfunction, a
Schottky contact will form. The opposite holes for contacts to n-type semiconductors.
2. If I wished to make a high (large) barrier height Schottky Barrier on n-type Si by
depositing an elemental metal, which metals would you suggest I try? What if we wanted
a large barrier on p-type silicon? (This later question is a bit tricky but from Fig. 15.19
and thinking about how work function affects barrier height you should be able to make a
good guess).
If it's n-type Si, then we are looking for metals with the largest work functions. From Fig.
15.19, we see this would be metals like Pt, Pd, and Au. If the Si were p-type, we would go
in the opposite direction toward small work function metals like Mg or Hf. A metal that
has a large work function and gives a large barrier on n-type silicon can be expected to
have a Fermi level close to the valence band edge, and so would give a small barrier
height on p-type silicon. In reality, these are just rules of thumb and the defect structure
at the interface introduced by the metal can completely change the real barrier height
from that predicted using work function and electron affinity differences.
3. Contact resistance can be lowered substantially in a Schottky contact by doping the
substrate heavily just under the contact. Using a couple of sentences, explain why this
works.
With high doping, the depletion width of a metal on semiconductor (Schottky) contact
gets very thin. Carriers can tunnel through the thin potential barrier substantially
reducing the resistance and making a good ohmic contact.
4. We have been making contacts in this course that are far from ideal. We have gotten
by with it either because contact resistance, even though large, was less than other
resistances, or because the silicon was heavily doped by diffusion. Typically Al contacts
are annealed to improve performance, and Si is added to the Al. Explain why Si is added
to the Al. That is, explain what problem this solves.
During annealing, Si diffuses along Al grain boundaries, and Al fills in the Si voids
leading to metallic spikes that extend as deep a 1um into the wafer. This can short circuit
an electrical junction. Using an Al:Si alloy instead of pure Al removes the driving force
for Si diffusion into Al. The ultimate solution, however, is to use an antidiffusion barrier
between the Si and the Al.
5. Research has been done into using porous silicon as an insulating layer between
interconnect (metal connection) layers on an integrated circuit. Porous silicon is silicon
which is electrochemically etched to create a structure filled with tiny voids. Because
much of the Si is removed, the dielectric constant of the porous silicon is much smaller
than that of crystalline Si. Explain why porous silicon might be an interesting material for
this application? Why might it not work well in this application?
Lowering capacitance and hence the RC time constant is the key to higher speed circuits.
To lower the interconnect capacitance, it's desirable to use a low dielectric material
between layers. Because porous silicon has large void space, it has a low dielectric
constant and could allow much higher speed interconnects. The main problem is it is
very fragile.
6. Electromigration is a key problem in interconnect technologies leading to premature
device failure. Describe what it is and how it can lead to failure. For full credit use your
own words. A drawing might help. Don't just copy a sentence from the book. (The same
for other questions above!)
As electrons travel through a metal line, they can hit the atoms in the metal. This gives
momentum to the atoms, knocks them loose, and causes them to move. Regions with a
constriction will have a higher current density. Atoms will preferentially move away
from these regions and accumulate in low current regions. This can open up shorts in
the lines and cause premature failures.
7. Provide the process flow for designing a lithographically-patterned metal contact on a
bare Si wafer using metal liftoff. (In Modules 5&6, you patterned a metal by evaporating
through a shadow mask—but a shadow mask is obviously not feasible for any sort of
precise device design!)
Process flows may vary. Below is one possibility:
1. Deposit photoresist.
2. Lithographically pattern so that the regions where you desire to have metal are
not covered with resist.
3. Hardbake resist.
4. Evaporate metal onto resist-patterned wafer.
5. Leave wafer in an acetone bath until liftoff occurs. Sonicate if necessary to help
the process.