Research Journal of Applied Sciences, Engineering and Technology 4(5): 452-457, 2012
ISSN: 2040-7467
© Maxwell Scientific Organization, 2012
Submitted: September 29, 2011
Accepted: November 04, 2011
Published: March 01, 2012
Design and Analysis of a Continuous-Time Common-Mode Feedback
Circuit Based on Differential-Difference Amplifier
Alireza Saberkari, Rasoul Fathipour and Hamidreza Saberkari
Department of Electrical Engineering, University of Guilan, Rasht, Iran
Abstract: The main purpose of this study is to introduce a new continuous-time Common-mode Feedback
Circuit (CMFB) based on Differential-Difference Amplifier (DDA) in order to achieve high speed, high loopgain, and simultaneously low distortion characteristics. Two control voltages with opposite variations used in
the proposed CMFB make the loop-gain and speed enhancement of the circuit. Additionally, reducing the dc
level and input signal amplitude of the CMFB by using source follower circuits helps to increase the effective
voltage of differential pairs and hence the linearity performance of the circuit. HSPICE simulation based on
0.35 :m CMOS process is done in order to evaluate the performance of the proposed CMFB circuit and the
results indicate that the proposed CMFB is faster than the typical one and has lower odd and even harmonics
in comparison with the conventional CMFB.
Key words: Common-mode feedback, differential-difference amplifier, high speed, low distortion, operational
amplifier, transconductance
In this study, a high speed, high loop-gain, and low
distortion continuous-time DDA-CMFB is introduced by
applying some modifications on the conventional CMFB
circuit (CMFB1).
INTRODUCTION
The Common-mode Feedback Circuits (CMFB) are
utilized to regulate the output Common-mode (CM)
voltage level of fully differential operational amplifiers by
adjusting their output CM current. There are several
methods to implement a CMFB circuit that among of
them using the Differential-difference Amplifier (DDA)
is more prevalent due to the fact that it exhibits large
transconductance and does not resistively load the main
amplifier output (Silva-Martinez et al., 1992; Czarnul
et al., 1994; Luh et al., 2000; Kwan and Martin, 1991;
Zhang and Hurst, 2006). Symmetrical differential pairs
used in this structure obtain the output CM voltage level
of the main amplifier, Voc, and compare it with the
reference voltage, Vcm. The resulted error is returned to
the main amplifier to adjust its bias current. Figure 1
shows the typical DDA-CMFB, which is called CMFB1
in this paper, and the main amplifier.
There are some issues to be fulfilled when designing
a good CMFB circuit (Choksi and Carley, 2003). In most
applications, the slew rate and unity-gain frequency of the
CM loop should be comparable to that of the differential
loop to avoid output signal distortion resulting from
clipping due to slow settling of the output CM voltage.
Also, the gain of the CM loop should be sufficiently large
to obtain the CM voltage within the desired accuracy. The
number of parasitic poles in the CM loop should be
minimized. Furthermore, the CM loop should be
adequately compensated by ensuring a good phase margin
and a fast settling step response (Choksi and Carley,
2003; Johns and Martin, 1996).
LOOP-GAIN AND SPEED ENHANCEMENT
Without the CMFB in the main operational amplifier
shown in Fig. 1b when the total current of transistors M3
and M4 differs from that of M5, two cases may occur.
First, the total current of M3 and M4 is more than that of
M5. In this case, the output capacitors are charged and the
voltage level of output nodes is increased until M3 and
M4 enter to the triode region and their currents are
decreased. In second case, when the total current of M3
and M4 is less than that of M5 the output capacitors are
discharged and the voltage level of output nodes is
decreased until M1, M2, and M5 enter to the triode
region. The CMFB1 shown in Fig. 1a is responsible for
the accurate regulation of the current of M5 equal to the
total current of M3 and M4. For this purpose, the output
CM voltage level is sensed by two differential pairs (M9M12) and compared with the reference voltage. Then the
proportional current, Icms, is generated and mirrored to
the tail current of the main amplifier.
However, this mechanism is done through one path
in the CMFB1 circuit and the CM Control signal (CMC)
is applied to the gate of M5. In order to increase the loopgain and speed of the feedback loop, two control signals
with opposite variations are used in the proposed CMFB
(CMFB2), as shown in Fig. 2a which one of them is
applied to the gate of M5 (CMC1) and another one is fed
Corresponding Author: Alireza Saberkari, Department of Electrical Engineering, University of Guilan, Rasht, Iran
452
Res. J. Appl. Sci. Eng. Technol., 4(5): 452-457, 2012
(a)
(b)
Fig. 1: (a) Typical DDA-CMFB circuit (CMFB1), (b) the main operational amplifier
(a)
(b)
Fig. 2: (a) Modified CMFB for speed and loop-gain enhancement (CMFB2), (b) the main operational amplifier
to the gate of M3 and M4 (CMC2) of the main amplifier.
Hence in the main amplifier shown in Fig. 2b, if the
current of M5 is less than that of M3 and M4, one path
increases the current of M5 and simultaneously anther
path decreases the current of M3 and M4 and vise-versa.
and Vcm is the reference voltage. Even if this voltage
becomes large to force the transistors to be out of their
linear region, Eq. (1) can be expressed as bellow (Gray
et al., 2001):
I14  Icms  I8 
LINE ARITY ENHANCEMENT
2
 
 L 11
2  Vod 

(Voc  Vcm ) 4Vov

 2 
If it is assumed that the transistors of differential
pairs (M9-M12) in CMFB1 operate in the active region
and the difference of the main amplifier output CM
voltage and reference voltage could be treated as small
signal input, the following relation can be derived:
I14  I cms  I8  gm (Voc  Vcm )
 p Cox  W 
2
(2)

 




 



2
 1
 1  (Voc  Vcm )Vod  
V od
..
 
1  

2
2
4 2

 Vod   8 
2  Vod   


V
4
4
V
ov
  



 ov 

 2  
2   



(1)
where, Vov is the effective voltage of differential pairs
(M9-M12) and Vod is the output differential-mode voltage
of main amplifier. If |Vod/2|<<|2Vov|, Eq. (2) reduces to
(1).
where, gm is the transconductance of transistors M9-M12,
Voc is the output CM voltage level of the main amplifier,
453
Res. J. Appl. Sci. Eng. Technol., 4(5): 452-457, 2012
reduce the nonlinear terms which can be realized by a
variable resistor as shown in the CMFB2 circuit. In
balance conditions and without any error voltage, the
following relation can be extracted from Fig. 2:
15
Voc-Vcm (mV)
10
5
0
-10
-15
W
  (1  VDS 5 )
 L 5
-20
-25
-30
-35
0
5
10
15
20
Rv (Kohm)
25
W
  (1  VDS14 )
 L  14
30

 W

W
  (1  VDS15 ) 
   (1  VSD3 )


L
L
3
15


2
 W 

W


(
1

)
(
1

)
V
V
 
SD16
DS 13 
  


L
L
16
13


Fig. 3: Error voltage versus variable resistor
As it is obvious from Eq. (2), for Voc…Vcm, lcms has
terms that include even-order harmonics of Vod. Hence,
the even-order harmonics create in the frequency
spectrum of Icms and therefore in Voc that degrade the
overall linearity. As a primary solution for this issue,
decreasing the error voltage (Voc-Vcm) is a simple way to
(3)
If Eq. (3) is not valid due to the error voltage,
changing the variable resistor will change the drain-source
voltage of transistor M15 and hence Eq. (3) will be valid
Fig. 4: Modified CMFB for linearity enhancement (CMFB3)
Fig. 5: The proposed DDA-CMFB as well as the main amplifier
454
Res. J. Appl. Sci. Eng. Technol., 4(5): 452-457, 2012
again. The error voltage variation of the CMFB2 circuit
versus the variable resistor is shown in Fig. 3. However,
the prefect cancellation of the error voltage is not possible
due to the device mismatch, finite gain in the CMFB loop,
thermal effect, and etc. An alternative way is that the
effective voltage of differential pairs Vov is increased in
order to reduce the nonlinearity. But this method makes it
difficult that the transistors M7 and M8 stay in the active
region.
In order to determine the greatest effective voltage
for transistors M9-M12 in balance conditions, assume that
M9 is at the edge of cut-off region and all of the currents
of M7 pass through M10. In this case Vov10 = %2Vov where
Vov is the effective voltage in balance conditions. If the
minimum drain-source voltage required for transistors M7
and M8 remain in the active region is 250 mV and the
output dc voltage level of the main amplifier is set to 1.8
V, the following relation can be derived:
Path 1
Path 2
20db
0db
-20db
-40db
-60db
-80db
-100db
150
100
50
0
-50
-100
-150
1
10
100
1K 10K 100K 1M 10M 100M 1G
10G
Fig. 6: Loop-gain of the proposd DDA-CMFB
1.8v
1.6v
1.4v
18
.  (VTH , P  2Vov )  VDD  250mV
(4)
1.2v
1.0v
0.8v
where, VTH,P is the threshold voltage of PMOS transistor.
Assuming VTH,P = 750 mV and VDD = 3.3 V for a 0.35
:m CMOS process, Vov equals to 360 mV. Hence, in
order to decrease the nonlinearity and according to
|Vod/2|<<|2Vov|, Vod, should be very small that causes a
significant limitation on the output swing of the main
amplifier.
According to Eq. (4), Vov can be increased by
decreasing the output dc level of the main amplifier. Also
if the input signal amplitude of the DDA-CMFB is
decreased in such a way that the output of the main
amplifier remains constant, Vov/Vod will be increased and
thereby the linearity of the circuit will be improved. To
realize this idea, three source follower circuits with small
resistors at their source terminal can be utilized. But,
small resistors will increase the power dissipation of the
circuit. A simple solution for this problem is to take
advantage of relatively large resistors and dividing them
into two resistors, as shown in Fig. 4. By choosing
appropriate values for the resistors, reduction of the dc
level and signal amplitude can be done at the input of the
DDA-CMFB. In Fig. 4, transistor M15 acts as a current
source and provides the possibility of increasing the gain
without any increase of Vov14. Also the loop-gain
reduction due to the reduction of CMFB input signal
amplitude is compensated.
0.6v
Proposed CMFB
0.4v
CMFB 1
0.2v
0
10ns
20ns
30ns
40ns
50ns
1.8v
1.6v
1.4v
1.2v
1.0v
Proposed CMFB
0.8v
CMFB 1
0.6v
0.4v
0.2v
0
10ns
20ns
30ns
40ns
50ns
Fig. 7: Transient response of CMFB1 and the proposed CMFB
to a step voltage with 1 ns rise and fall time
Figure 6 shows the loop-gain of the proposed circuit
that includes two control paths. As can be seen, the
magnitude and phase of two paths are completely
matched for frequencies between 0 to fr (unity-gain
frequency) and so the overall loop-gain which equals to
the sum of the loop-gain of each path is twice of that in
the conventional CMFB (CMFB1).
In order to comparison the speed of the CMFB1 and
the proposed CMFB, a 0-1.8 V step voltage with rise and
fall time of 1 ns is fed to the Vcm. Figure 7 shows the
transient response of two circuits with 1pF load
capacitors. As it is obvious, the modified circuit has faster
response to the reference voltage variations.
Figure 8 shows the FFT spectrum of Icms and Voc
for the CMFB1 and the proposed CMFB. In both circuits
Voc-Vcm = 36 mV and Vod(Peak) = 800 mV, but Vov is 360
and 935 mV for the CMFB1 and the proposed
CIRCUIT CHARACTERIZATION
With regard to the above discussion, the transistor
level schematic of the overall proposed DDA-CMFB
circuit as well as the main amplifier is shown in Fig. 5. In
order to evaluate the performance of the proposed CMFB,
the circuit is designed and simulated in HSPICE based on
0.35 :m CMOS process.
455
-200db
-220db
-199.27
-198.89
-200db
-220db
-240db
-260db
-240db
2k 3k
4k 5k 6k
7k 8k
9k 10k 11k12k
0
1k
2k 3k
4k 5k 6k
f(Hz)
-57.21
-100db
-100db
-120db
-120db
-140db
-140db
-104.67
-80db
-104.06
-101.87
-40db
-60db
Voc (v)
-80db
-88.0
-60db
-88.72
-62.35
-40db
-86.54
-20db
-44.86
-20db
9k 10k 11k 12k
0db
-30.41
0db
7k 8k
f(Hz)
-104.29
1k
-102.16
0
Voc (v)
-196.76
-160db
-180db
-198.86
-198.63
Icms (uA)
-180db
-186.53
-160db
-140db
-186.24
-140db
-151.83
-100db
-120db
-189.38
Icms(uA)
-120db
-164.62
-100db
-147.69
-131.4
Res. J. Appl. Sci. Eng. Technol., 4(5): 452-457, 2012
-160db
0
1k 2k 3k
9k 10k 11k 12k
4k 5k 6k 7k 8k
f(Hz)
0
1k 2k 3k
4k 5k 6k 7k 8k 9k 10k 11k 12k
f(Hz)
(a)
(b)
-200db
-220db
-200db
-220db
-240db
0 1k 2k 3k
4k 5k 6k 7k 8k 9k 10k 11k 12k
0
-199.29
-104.69
-104.27
-102.15
-104.06
-124.5
-80db
-100db
-101.88
-60db
-57.21
-79.73
Voc (v)
-87.85
-88.73
-86.48
-20db
-40db
-62.34
-86.53
-72.91
-44.86
-30.41
-61.86
-20db
Voc (v)
f(Hz)
0db
0db
-80db
-198.90
4k 5k 6k 7k 8k 9k 10k 11k 12k
1k 2k 3k
f(Hz)
-60db
-196.74
-260db
-240db
-40db
-198.84
-198.48
-222.3
Icms(uA)
-186.5
-186.23
-140db
-160db
-180db
-151.83
-188.91
-100db
-120db
-189.4
-180db
-164.61
-189.37
Icms(uA)
-140db
-160db
-165
-120db
-175.8
-131.3
-100db
-147.7
Fig. 8: FFT spectrum of (a) CMFB1, (b) the proposed CMFB
-120db
-100db
-140db
-120db
-160db
-140db
0
0 1k 2k 3k
4k 5k 6k 7k 8k 9k 10k 11k12k
1k 2k 3k
4k 5k 6k 7k 8k 9k 10k 11k 12k
f(Hz)
f(Hz)
(a)
(b)
Fig. 9: FFT spectrum with 2% device mismatch for (a) CMFB1, (b) the proposed CMFB
CMFB, respectively. FFT spectrum reveals that the
proposed circuit has better linearity performance in
comparison with the typical CMFB due to the greater
effective voltage of its differential pairs.
456
Res. J. Appl. Sci. Eng. Technol., 4(5): 452-457, 2012
REFERENCES
The point that should be mentioned is that when
transistors of differential pairs in the CMFB are matched,
only even-order harmonics of Vod appear in Icms and
Voc as shown in Fig. 8. However due to the device
mismatch, both odd and even harmonics of Vod affect the
Icms and Voc (Zhang and Hurst, 2006). Figure 9 shows
the FFT spectrum of Icms and Voc with worst case
mismatch of 2% in each differential pair of the CMFB1,
source followers and differential pairs of the proposed
CMFB. The FFT spectrum indicates better linearity
performance of the proposed CMFB with device
mismatch.
Choksi, O. and L.R. Carley, 2003. Analysis of switchedcapacitor common-mode feedback circuit. IEEE
Trans. Circ. Syst. II, 50(12): 906-917.
Czarnul, Z., S. Takagi and N. Fujii, 1994. Common-mode
feedback circuit with differential-difference
amplifier. IEEE T. Circ. Syst. I, 41(3): 243-246.
Gray, P.R., P.J. Hurst, S.H. Lewis and R.G. Meyer, 2001.
Analysis and Design of Analog Integrated Circuits.
4th Edn., Wiley, New York.
Johns, D.A. and K. Martin, 1996. Analog Integrated
Circuit Design. 1st Edn., Wiley, New York.
Kwan, T. and K. Martin, 1991. An adaptive analog
continuous-time cmos biquadratic filter. IEEE J.
Solid-State Circ., 26(6): 859-867.
Luh, L., J. Choma and J. Draper, 2000. A continuous-time
Common-mode Feedback Circuit (CMFB) for highimpedance current-mode applications. IEEE T. Circ.
Syst. II, 47(4): 363-369.
Silva-Martinez, J., M.S.J. Steyaert and W. Sansen, 1992.
Design Techniques for high-performance Full-CMOS
OTA-RC continuous-time filters. IEEE J. Solid-State
Circ., 27(7): 993-1001.
Zhang, M.M. and P.J. Hurst, 2006. Effect of nonlinearity
in the cmfb circuit that uses the differentialdifference amplifier. Proc. IEEE Int. Symp. Circ.
Syst. (ISCAS’06), pp: 1390-1393.
CONCLUSION
A high speed, high loop-gain, and low distortion
DDA-CMFB is presented which consists of two control
voltages with opposite variations in order to increase the
loop-gain and speed of the circuit. On the other hand,
reducing the dc level and input signal amplitude of the
CMFB by using source follower circuits increases the
effective voltage of differential pairs and improves the
linearity of the circuit. HSPICE simulation based on 0.35
:m CMOS process has been done in order to evaluate the
performance of the proposed CMFB circuit and the results
indicate that the proposed CMFB is faster and has lower
odd and even harmonics in comparison with the
conventional CMFB.
457