Tentamen i kursen Datorarkitektur - TDTS 52, 1998-08-25, kl. 9-13

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TEKNISKA HÖGSKOLAN I LINKÖPING
Tentamen i kursen
Datorarkitektur - TDTS 52, 1998-08-25, kl. 9-13
Institutionen
för datavetenskap
Du
kan
skriva
på
svenska
eller engelska!
Petru Eles
Tentamen i kursen
Datorarkitektur - TDTS 52
1998-08-25, kl. 9-13
Hjälpmedel:
Inga.
Poänggränser:
Maximal poäng är 30. Rapporten om fallstudierna ger maximalt 10 poäng.
För godkänt krävs sammanlagt 22 poäng.
Resultat anslås:
Senast 1998-??-?? på IDAs anslagstavla för tentamensresultat.
Jourhavande lärare:
Erik Larsson, tel 28 4046
Good luck !!!
Tentamen i kursen Datorarkitektur - TDTS 52, 1998-08-25, kl. 9-13
Du kan skriva på svenska eller engelska!
1.
We distinguish four types of memory, depending on the “accessing method”: (1) sequential
access, (2) direct access, (3) random access, (4) associative memory.
Give a short characterization of each type: organization, how access is solved, access time.
To which of these types belongs the
- semiconductor memory
- disk
- magnetic tape.
(3p)
2.
Events on a communication bus can be coordinated in two ways: (1) synchronous timing, (2)
asynchronous timing.
Explain how the two alternatives work.
(2p)
3.
Explain how virtual memory functions. Illustrate by a figure.
(2p)
4.
5.
a)
b)
Consider the following statement (in Pascal, for example):
X := A*B - C*(D + E)
Show how this statement can be coded in assembly language, as a sequence of 3 - address
and 2 - address instructions.
(2p)
Explain: - indexed addressing;
- indexed addressing with autoincrement and autodecrement.
The following instruction sequence counts the number of non-zero elements in a table which
holds N integers:
MOVE
#0, R2
MOVE
#0, R0
NEXTEL COMP
#0, TABLE[R2]
BEZ
ISZERO
ADD
#1, R0
ISZERO
ADD
#1, R2
COMP
R2, N
BNZ
NEXTEL
MOVE
R0, NRNONZERO
Modify the sequence above so that you use indexing with autoincrement.
(4p)
Tentamen i kursen Datorarkitektur - TDTS 52, 1998-08-25, kl. 9-13
Du kan skriva på svenska eller engelska!
6.
What is the purpose of instruction pipelining? How does a pipelined unit work?
(2p)
7.
a)
b)
What is a data hazard in a pipelined unit? Give also an example.
Explain how some data hazards can be avoided by forwarding (bypassing)?
(2p)
8.
a)
b)
9.
Why is branch prediction important?
Illustrate your answer by showing how a certain instruction sequence, of your choice, passes
a pipelined unit, in the case of a correct and in that of an incorrect prediction.
(3p)
The design of RISC architectures is based on certain characteristics of currently used
programs. Enumerate at least five such characteristics.
(2p)
10. Explain the following two policies for instruction execution in superscalar architectures:
a) in-order issue with in-order completion;
b) out-of-order issue with out-of-order completion.
(2p)
11. Draw the basic block-diagram of a
a) hardwired control unit;
b) microprogrammed control unit.
(3p)
12. Flynn’s classification of computer architectures: give the definition of the alternative
architectures and draw for each one a block diagram.
(3p)
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