Design for Test of Digital Systems
TDDC33
Erik Larsson
Department of Computer Science
1
Invited lectures
 Lecture 7 Invited Talk by Dr. Ingemar Söderquist, SAAB,
September 28 at 13-15
 Lecture 8 Invited Talk by Dr. Thomas Granlund, SAAB,
October 05 at 13-15
2
Course Outline
 Introduction; Manufacturing, Wafer sort, Final test, Board and
System Test, Defects, and Faults
 Test generation; combinational and sequential test generation
 Design-for-Test techniques; test point insertion, scan,
enhanced scan
 Test data compression, Built-In Self-Test; Logic BIST and
memory BIST
 System Chip Test; test architectures, test planning, test
scheduling, and power constraints
 System Test and Boundary Scan
3
Making fault free electronic products
ok?
ok?
ok?
Test
specification
ok?
ok?
Test Preparation
Production Test
In-Field Test
4
Printed Circuit Board (PCB)
IC
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
Core
Logic
PCB
5
Probing for Test
6
Bed-of-Nails
Top view
Side view
PCB
IC
IC
IC
No testing
IC
Core
Logic
IC
Core
Logic
Bed of nails
IC
Core
Logic
Core
Logic
PCB
IC
IC
PCB
Testing
Bed of nails
7
Test Objectives
 Given a Printed Circuit Board (PCB) composed of a set of
components (ICs) where each component is tested good.
 The main objectives are to ensure that all components are:

correct (the desired ICs are selected)

mounted correctly at the right place on the board and

ensuring that interconnections are functioning according to
specification
 Problems that may occur:

A component does not contain logic

A component is not placed where it should be,

A component is at its place but turned wrongly,

A component is correct but the interconnection is not correct, for
example due to bad soldering.
8
Comparing SOC Test and Board Test
SOC Test
Board Test
 Cores are not tested prior to
chip fabrication
 All components (chips) are
tested prior board fabrication
 Focus on both core test
(internal test) and connection
test (external test)
 Main focus on test of
interconnections (external test)
9
IEEE 1500 Core Test Standard
 Goals

Define test interface between core and SOC

Core isolation

Plug-and-play protocols
 Scope

Standardize core isolation protocols and test modes

TAM design

Type of test to be applied

Test scheduling
10
IEEE 1500 Wrapper
Test stimuli
W
B
R
W
B
R
Test responses
Core
Functional data
W
B
R
W
B
R
WBY
Test control+
test stimuli
wrapper
WIR
Functional data
Test control+
test responses
WIP
11
WPP (optional)
Test Wrapper
WPC
WPO
WPI
WSP: Wrapper Serial Port
WSI: Wrapper Serial Input
WSC: Wrapper Serial Control
WSO: Wrapper Serial Output
WPP: Wrapper Parallel Port
WPI: Wrapper Parallel Input
WPC: Wrapper Parallel Control
WPO: Wrapper Parallel Output
Core
WSI
wrapper
WSO
WSC
WSP (mandatory)
 Interface between module and the rest of the chip; makes it possible
access core and isolate core from rest of the system.
 Test modes

Normal: Functional mode

InTest: test of module itself

ExTest: test of interconnection to other core
 IEEE 1500 Standard for Embedded Core Test
13
Test Wrapper: Modes
WFO
WFI
WSI
W
B
R
FO
Core FO
FI
FI
W
B
R
WFO
Normal mode
WFI
Normal mode
W
B
R
FO Core FO
FI
Test enable
Test enable
WBY
WBY
WSO
WIR
wrapper
WSI
wrapper
WSC
UDL
UDL
WSI
W
B
R
FI
FI
Normal mode
WSO
WIR
W
B
R
W
B
R
UDL
UDL
FO Core FO
FI
FI
Test enable
Test enable
WBY
WBY
WIR
Normal mode
WSC
FO Core FO
wrapper
FI
W
B
R
WSO
WSI
wrapper
WIR
W
B
R
WSO
15
WSC
WSC
Boundary Scan (IEEE std. 1149.1)
 The Joint European Test Action Group (JETAG), formed in
mid-80, became Joint Test Action Group (JTAG) in 1988 and
formed the IEEE std 1149.1. The standard consists of:

Test Access Port (TAP)

TAP Controller (TAPC),

Instruction Register (IR), and

Data Registers (DR)
19
Boundary Scan
BSC
BSC
BSC
Core logic
BSC
Core logic
BSC
BSC
BSC
BSC
Bypass
TDI
TDO
Instruction Register
TMS
TCK
TAP Controller
TRST
20
20
IEEE Std. 1149.1 and IEEE Std. 1500
(User-defined WPP = WPI+WPO+WPC)
BSC
BSC
BSC
W
B
R
BSC
Core logic
BSC
BSC
BSC
BSC
Bypass
FO
FI
FI
WFO
W
B
R
FO
FO
FI
FI
TDO
TAP Controller
W
B
R
WFO
WFI
Test enable
Instruction Register
TMS
TCK
W
B
R
Core
WFI
TDI
FO
WBY
WSI
wrapper
WIR
WSO
TRST
WSC: WRCK, WRST, SelectWR,
ShiftWR, CaptureWR, UpdateWR
21
Boundary Scan
Boundary Scan cell
Core
Logic
Core
Logic
IC
IC
TAP
TAP
TAP
IC
TAP
IC
Core
Logic
Core
Logic
Boundary Scan chain
TDI
TCK
TMS
TRST
TDO
PCB
22
Boundary Scan Cell (BSC)
SO
MODE
IN
ShiftDR
0
1
MUX
D FF
Q
D FF
MUX
OUT
Q
1
0
SI
ClockDR
UpdateDR
SO
IN
BSC
CTO
OUT
SI
CFI
WBC
CFO
CTI
Std. 1149
Std. 1500
23
Boundary Scan
BSC
BSC
BSC
BSC
Core logic
BSC
BSC
BSC
BSC
Internal
Registers
TDI
Bypass
TDO
Miscellaneous
Registers
Instruction Register
TMS
TCK
TAP Controller
TRST
24
Boundary Scan
Bypass Register
Boundary Scan Register
TDO
TDI
T
P
Design Specific Data Registers
ShiftDR
A
TAP Controller
TMS
TCK
TRST
Device ID Register
ClockDR
TDI: Test Data In
UpdateDR
Reset
Data Registers (DR)
ClockIR
ShiftIR
Instruction Decode
UpdateIR
Instruction Register (IR)
TDO: Test DataOut
TMS: Test Mode Select
TCK: Test Clock
Optional registers and signals are shown in dotted lines
25
TMS and TCK are used to control
the behavior of the TAP.
TAP Controller
TMS
Control of data registers
Control of instruction register
Test-Logic-Reset
1
Run-Test/Idle
0
1
0
1
1
Select-DR-Scan
1
Select-IR-Scan
0
Capture-DR
1
0
Shift-IR
0
Shift-DR
1
0
Exit1-DR
0
1
1
Update-DR
1
1
0
Pause-IR
1
0
Exit2-DR
0
1
Exit1-IR
Pause-DR
1
0
0
Capture-IR
Exit2-IR
1
Update-IR
0
1
0
26
Instructions
 Mandatory

Bypass; used to bypassing an IC

Extest; tests interconnection between ICs

Sample/Preload; used to sample (snapshot) and preload boundary
scan during operation
 Optional

Intest

Runbist

Clamp

Idcode

Usercode

Highz
27
Boundary Scan Description Language (BSDL)

BSDL is a subset of VHDL that describes how JTAG (IEEE 1149.1) is
implemented in a particular device.

For a device to be JTAG compliant, it must have an associated BSDL file.

Use BSDL file to work out how to access a device in the JTAG chain.

BSDL files contain the following elements:

Entity Description: Statements naming the device.

Generic Parameter: A value such as a package type.

Port Description: Describes the pins on the device.

Use Statements: References external definitions.

Pin Mapping(s): Maps logical signals in the device to physical pins.

Scan Port Identification: Defines the pins to access the JTAG capabilities (TDI, TDO,
etc - the Test Access Port).

Instruction Register Description: Signals to access JTAG device modes.

Register Access Description: Which register is placed between TDI and TDO for
each JTAG instruction.

Boundary Register Description: List of the boundary scan cells and their
functionality.
28
Mapping component data to the BScan
Chain
”Manual” composition of the scan data arrays –
Knowledge of position in the overall chain is required
TDI data
TDO data
Component data for one or more DR registers
29
BYPASS
BSC
BSC
BSC
BSC
Core logic
TDI
BSC
BSC
BSC
BSC
Bypass
TDO
Instruction Register
TMS
TCK
TAP Controller
TRST
30
EXTEST
Shift-DR (IC1)
TDI
Core
Logic
Core
Logic
IC
IC
TAP
TAP
To be tested
TCK
TMS
TRST
TDO
TAP
TAP
IC
IC
Core
Logic
Core
Logic
PCB
31
EXTEST
TDI
Core
Logic
Core
Logic
IC
IC
TAP
Update-DR (IC1)
TAP
To be tested
TCK
TMS
TRST
TDO
TAP
TAP
IC
IC
Core
Logic
Core
Logic
Capture (IC2)
PCB
32
EXTEST
TDI
Core
Logic
Core
Logic
IC
IC
TAP
TAP
To be tested
TCK
TMS
TRST
TDO
TAP
TAP
IC
IC
Core
Logic
Core
Logic
Shift-DR (IC2)
PCB
33
Scan and MBIST support with Boundary
Scan
Scan_out
Scan_en
Logic
BIST
controller
BIST
decoder
Scan
decoder
Memory
Compressor
Bist_sel
Mbist
Bist_so
Scan_in
Scan path
Int_scan
Decoder
TDI
TCK
TMS
Instruction register
TAP Controller
MUX
TDO
34
Making fault free electronic products
ok?
ok?
ok?
Test
specification
ok?
ok?
Test Preparation
Production Test
In-Field Test
35
Introduction
Backplane
36
Ring Architecture with Shared TMS
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
PCB
PCB
TDI
TCK
TMS
TRST
TDO
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
PCB
PCB
37
Ring Architecture with Separate TMS
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
PCB
TDI
TCK
TMS1
TMS2
TMS3
TMS4
TRST
TDO
PCB
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
PCB
PCB
38
Star Architecture
TDI
TCK
TMS
TDO
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
PCB
PCB
TDI
TCK
TMS
TDO
TDI
TCK
TMS
TDO
TDI
TCK
TMS
TDO
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
PCB
PCB
39
Multi-drop Architecture
Bus master
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
PCB
PCB
Multi-Drop
Device
Multi-Drop
Device
TDI
TCK
TMS
TDO
Multi-Drop
Device
Multi-Drop
Device
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
IC
Core
Logic
PCB
PCB
40
IEEE 1149 Standard Family
Number
Main objectives
Status
1149.1
Testing of digital chips and
interconnects between chips
Std. 1149.1-1990
Std. 1149.1a-1993
Std. 1149.1b-1994 (BSDL)
Std. 1149.1-2001
1149.2
Extended digital serial interface
Discontinued
1149.3
Direct access testability interface
Discontinued
1149.4
Mixed-signal test bus
Std. 1149.4-1999
1149.5
Standard module test and
maintenance (MTM) bus
Std. 1149.5-1995 (not endorsed by
IEEE since 2003)
1149.6
High-speed network interface
protocol
Std. 1149.6-2003
1149.7
Reduced-Pin and EnhancedFunctionality Test Access Port
Std.1149.7-2009
41
IJTAG P1687
 IJTAG P1687 Statement of Scope:

This standard will develop a methodology for access to embedded
test and debug features, (but not the features themselves) via the
IEEE 1149.1 Test Access Port (TAP) and additional signals that
may be required. The elements of the methodology include a
description language for the characteristics of the features and for
communication with the features, and requirements for interfacing
to the features
42
Interface and scan-path
43
Farrokh Ghani Zadegan, Urban Ingelsson, Gunnar Carlsson and Erik Larsson, “Test Time Analysis for IEEE
P1687”, IEEE 19th Asian Test Symposium(ATS2010), Shanghai, China, Dec. 2010
Analysis of IEEE P1687 network

The control data for the SIB is transported on the same wire as test data

Control data is transferred to the status register when the JTAG state
machine does ”apply and capture”

“CUC” : Apply Capture Update Cycle : 5 clock cycles in the FSM
44
The infrastructure
45
Analysis: Hierarchical architecture
Concurrent test schedule
46
Analysis: Hierarchical architecture
Concurrent test schedule
47
Analysis: Hierarchical architecture
Concurrent test schedule
48
Analysis: Hierarchical architecture
Concurrent test schedule
49
Analysis: Hierarchical architecture
Concurrent test schedule
50
Analysis: Hierarchical architecture
Concurrent test schedule
51
Making fault free electronic products
ok?
ok?
ok?
Test
specification
ok?
ok?
Test Preparation
Production Test
In-Field Test
52
A Fault Management View
Network
Management
NMS
displays & correlates alarms
I/f: Mun, standard Alarm IRP
Sub-network
Management
OSS
• alarm subscriptions
• alarm list presentation
• standard interfaces
• alarm filtering
I/f: Mur, Mub
Element Management of
Network Elements
• alarm log
RBS
• alarm list
• alarm correlation within NE
53
Mudassar Majeed, Daniel Ahlström, Urban Ingelsson, Gunnar Carlsson and Erik Larsson, “Efficient embedding of
deterministic test data”, IEEE 19th Asian Test Symposium(ATS2010), Shanghai, China, Dec. 2010
Embedded deterministic test

Printed Circuit Boards with mounted ICs

In-field test (boot-up, regular checks)




Detects manufacturing test escapes

Detects faults that are due to wear-out, environmental impact etc.
In-field diagnosis

To determine which IC has the fault

Requires on-system test evaluation
Key problem: Storing the test data on the system

High memory requirements

Inflexible in applying different tests
The proposed solution

An embedded test controller to manipulate test data based on commands

With the help of structural information about the system

Reduces memory requirements and provides flexibility

Supports diagnosis

Based on IEEE 1149.1 JTAG
54
Embedded test-specific circuitry
55
IEEE 1149.1
56
Memory requirements
57
Basic idea behind the solution
58
Kim Petérsen, Dimitar Nikolov, Urban Ingelsson, Gunnar Carlsson and Erik Larsson, “An MPSoCs demonstrator
for fault injection and fault handling in an IEEE P1687 environment”, IEEE 17th European Test Symposium (ETS
2012), Annecy, France, May 28-June 1, 2012.
Demonstrator
MPSoC
MEMORY
MASTER CPU
RM
IAI
IM
ACCELERATOR
FIPI
DSP
CPU
BLOCK
INSTRUMENT
FIM
MASTER CPU
Instrument Access Infrastructure
TAP
SIB
SIB
FIF
SIB
Segment Insertion Bit
(SIB)
M
SIB
SIB
FIF
DSP
SIB
SIB
FIF
CPU1
M
FIF
M
SIB
FIF
M
CPU2
SIB
FIF
M
CPU10
M
FIF
M
MASTER CPU
Instrument Access Infrastructure
TAP
Closed SIB
FIF
SIB
Opened SIB
M
SIB
SIB
FIF
DSP
SIB
SIB
FIF
CPU1
M
FIF
M
SIB
FIF
M
CPU2
SIB
FIF
M
CPU10
M
FIF
M
MASTER CPU
TAP
Fault Indication and Propagation
Infrastructure
SIB
SIB
FIF
SIB
Fault Indication Flag
M
SIB
SIB
Masking Bit
FIF
DSP
SIB
SIB
FIF
CPU1
M
FIF
M
SIB
FIF
M
CPU2
SIB
FIF
M
CPU10
M
FIF
M
MASTER CPU
TAP
RM
IM
0
System-Level
0
00
DSP
Component Type-Level
00
00
00
Fault injection
11
CPU1
Component-Level
00
00
CPU2
00
00
CPU10
00
0..0
0..0
MASTER CPU
TAP
RM
IM
0
System-Level
0
00
DSP
Component Type-Level
00
00
00
Fault injection
11
CPU1
Component-Level
00
00
CPU2
00
00
CPU10
00
1..0
0..0
MASTER CPU
TAP
RM
IM
0
System-Level
0
00
DSP
Component Type-Level
00
10
00
Fault injection
11
CPU1
Component-Level
00
00
CPU2
00
00
CPU10
00
1..0
0..0
MASTER CPU
Initiate identification
TAP
RM
Fault Detection
IM
1
System-Level
0
00
DSP
Component Type-Level
00
10
00
Fault injection
11
CPU1
Component-Level
00
00
CPU2
00
00
CPU10
00
1..0
0..0
MASTER CPU
Continue identification
TAP
RM
IM
1
System-Level
0
00
DSP
Component Type-Level
11
CPU1
Component-Level
00
10
00
00
00
CPU2
00
00
CPU10
00
1..0
0..0
MASTER CPU
TAP
RM
IM
Initiate re-execution on
Fault
source
identified
CPU
1 and keep
monitoring system
operation
1
System-Level
0
00
DSP
Component Type-Level
11
CPU1
Component-Level
00
10
00
00
00
CPU2
00
00
CPU10
00
1..0
0..0
MASTER CPU
TAP
RM
IM
0
System-Level
0
00
System has recovered
from a
00
00
DSP
00
soft
fault
Component Type-Level
00
CPU1
Component-Level
00
00
CPU2
00
00
CPU10
00
0..0
0..0
Design for Test of Digital Systems
TDDC33
Erik Larsson
Department of Computer Science
70