2012 2nd International Conference on Information Communication and Management (ICICM 2012)
IPCSIT vol. 55 (2012) © (2012) IACSIT Press, Singapore
DOI: 10.7763/IPCSIT.2012.V55.26
Efficient On-Chip Crosstalk Avoidance CODECs using FTF-FNS
Venkateswara Rao J 1, Sudhakara Rao P 2
1
Associate Professor, Vignan Institute of Technology & Science
2
Dean R & D, Vignan Institute of Technology & Science
Abstract. VLSI design has marched into the realm of Deep Submicron (DSM) processes, where the
minimum feature size is well below 1 µm. These advanced processes enable designers to implement faster,
bigger and more complex designs. Integrated Circuit(IC) design has seen a revolutionary progress in the past
two decades with shrinking sizes of VLSI fabrication processes. This has an advantage of fabricating millions
of transistors in a single chip IC. On the other hand it also creates many challenges in Deep Sub-Micron
(DSM) technologies. One of the greatest challenges in DSM designs is inter-wire crosstalk, which becomes
significant due to coupling capacitance between wires. The effect of inter wire crosstalk is that it greatly
limits speed and increases power consumption of IC. This paper focuses on design and implementation of an
efficient CODEC which uses Forbidden Transition Free (FTF), Fibonacci based Number System (FNS) for
bus encoding. Our approach of CODEC design greatly increases the speed (approximately greater than 2.5
times) and decreases the power consumption with the best existing technologies.
Keywords: Crosstalk, Deep Sub-Micron, Forbidden Transition Free, Fibonacci Number System, On-Chip
bus, Crosstalk avoidance Codes, CODEC.
1. Introduction
With shrinking device sizes, increasing chip complexity and faster clock speeds, wire delay is becoming
increasingly significant [11]. The propagation delay through long cross-chip buses is proving to be a limiting
factor in the speed of some designs, and this trend is only expected to get worse. It has been shown that the
delay through a long bus is strongly dependent on the coupling capacitance between the wires. In particular,
the crosstalk effect when adjacent wires simultaneously transition in opposite directions is particularly
detrimental to the delay. When the cross-coupling capacitance is comparable to or exceeds the loading
capacitance on the wires, the delay of such a transition may be twice or more than that of a wire transitioning
next to a steady signal. This delay penalty is commonly referred to as the capacitive crosstalk delay. The
capacitive crosstalk delay strongly depends on the transition activities of the adjacent signals, hence the
crosstalk type. Type-4 and type-3 crosstalk have the worst delay characteristics, followed by type-2 and then
type-1. A few techniques involving selective skewing of bus data signals [12], transistor sizing [13], and
repeater sizing [14] to reduce capacitive crosstalk induced delay have been proposed. Encoding is one of the
more effective ways to reduce capacitive crosstalk delays. Here we present encoding techniques that focus
on reducing crosstalk delay. The rest of the paper is organized as follows. Section II explains about Crosstalk
Classification, Section III discusses about forbidden transition free crosstalk avoidance codes (FPF-CAC). In
Section IV, we discuss about Fibonacci Number System. In Section V, We discuss about circuit
implementation and experimental results. We conclude the paper in Section 6.
2. Crosstalk Classification
Figure-1 illustrates a simplified on-chip bus model with crosstalk. For simplicity we assumed three
concurrent wire lines. In the figure, CL denotes the load capacitance, which includes the receiver gate
capacitance and also the parasitic wire-to-substrate parasitic capacitance. CI is the inter-wire coupling
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capacitance between adjacent signal lines of the bus. In practice, this bus structure is typically modelled as a
distributed RC network, which includes the non-zero resistance of the wire as well.
Physical Layout
B
A
C
Circuit Model Aggressor net A
CI
Victim net B
Driver
CL
Receiver 2
Receiver 1
Aggressor net C
Fig. 1: On-chip bus model with crosstalk
Fig. 2: Delay impact of different crosstalk classes types
The on-chip bus crosstalk is classified into five types as shown in Table-1.
Table. 1: Transition Pattern Crosstalk Classification
Crosstalk Class
Sample Transition Patterns
Ceff
0C
CL
000→111
1C
CL(1+λ)
011→000
2C
CL(1+2λ)
010→000
3C
CL(1+3λ)
010→100
4C
CL(1+4λ)
010→101
This classification is based on the effective capacitance, in the jth line in a bus as, Ceff, j
Ceff, j = CL [1 + λ ((1 − δj, j−1) + (1 − δj, j+1))]
(1)
= CL + Clw, j + Crw, j
It separates Ceff, j into three components: the intrinsic capacitance CL, the crosstalk capacitance to the wire
on the left side, Clw, j = λ (1−δj, j−1) CL, and the capacitance to the wire on the right side, Crw, j = λ (1−δj, j+1)
CL. It is easy to see that Clw, j, Crw, j ∈ {0, 1CI, 2CI}.
3. Forbidden Transition Free Based Crosstalk Avoidance Codes
A forbidden transition is defined as the simultaneous transition (in opposite directions) on two adjacent
bits, i.e., 01 → 10 or 10 → 01. We first observe that to guarantee forbidden transition freedom on the
boundary djdj+1 between any two code-words in an FTF-CAC, the 01 and 10 patterns cannot coexist in the
same set of code-words. This can be easily confirmed by examining the transitions among codes in {00, 01,
and 11}, or {00, 10, 11}. If we eliminate 01 or 10 from all the boundaries in the code-words in a set of codewords R, we can guarantee that R is forbidden transition free. Therefore, once again, the problem of
eliminating forbidden transitions is transformed into a problem of eliminating specific patterns.
• Start with a complete set of 2n vectors and remove code-words that do not satisfy the boundary
constraints.
• Start with a set consisting of a single class 1 code-word and grow the FTF-CAC code-words by adding
compatible code-words to the set.
• Start from a small FTF set (say 2-bit FTF codes) and inductively append bits to the code-words in the
set until the code-word length reaches n-bits. Clearly, the first (pruning) method is impractical when n is
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large, since a complete set of code-words have 2n entries and searching through n − 1 boundaries requires O
(2(n−1) n) searches. Both the second and the third methods listed above actually “grow” the FTF code-words
instead of “pruning”, and therefore require less computation. The method of “growing” code-words by
appending bits to code-words in an existing set is given in Algorith-1.
Algorithm-1 is the pseudo code for generating the FTF code-words.
Table. 2: FTF-CAC Code-words generation Algorithm.
Algorithm-1 FTF code-word generation
S2 = {00, 01, 11}
else
for m > 2 do
for ∀Vm−1 ∈ Sm−1 do
if m is odd then
add 0 · Vm−1 to Sm;
for ∀Vm−1 ∈ Sm−1 do
if dm−1 = 1 then
add 1 · Vm−1 to Sm;
add 1 · Vm−1 to Sm;
if dm−1 = 0 then
end if
add 0 · Vm−1 to Sm;
end for
end if
end if
end for
end for
Table. 3: FTF-CAC Code-words for 2, 3, 4 & 5 Bit Busses.
2 bits
00
01
11
3 bits
000
001
100
101
111
4 bits
0000
0001
0100
0101
0111
1100
1101
1111
5 bits
00000
00001
00100
00101
00111
10000
10001
10100
10101
10111
11100
11101
11111
4. Fibonacci Number System(FNS)
The Fibonacci binary numeral system (FNS) was first mentioned in the context of CAC designs by
Mutyam in [4]. The author proposed an inductive code-word generation algorithm for the forbidden Pattern
free code. The algorithm is similar to those proposed in [6, 8]. However, [4] failed to address the mapping
scheme and CODEC design. We next describe our FNS-based mapping, and the resulting CODEC designs.
A numeral system is “a framework where numbers are represented by numerals in a consistent manner”.
The most commonly used numeral system in digital design is the binary numeral system, which uses powers
of two as the basis. For a number v, its binary representation is defined in Eq. 2. The binary numeral system
is complete and unambiguous, which means that each number has one and only one representation in the
binary numeral system.
Definition-1
v=
bk ∈ {0, 1}
(2)
=
dk ∈ {0, 1}
(3)
The Fibonacci-based numeral system N(fm, {0, 1}) is the numeral system that uses Fibonacci sequence as the
basis. The definition of the Fibonacci sequence is given in Eq. 4. A number v is represented as the
summation of some Fibonacci numbers, and no Fibonacci number is in the summation more than once, as
indicated in Eq. 5.
Definition-2
fm =
{0
if
m=0,
139
{1
if
{fm−1 + fm−2
if
m=1,
(4)
m ≥ 2.
Similar to the binary numeral system, the Fibonacci-based numeral system is complete, and therefore any
number v can be represented in this system. However, the Fibonacci-based numeral system is ambiguous. As
an example, there are six 7-digit vectors in the Fibonacci numeral system for the decimal number 19:
{0111101, 0111110, 1001101, 1001110, 1010001 and 1010010}. For clarity, we refer to a vector in the
binary numeral system as a binary vector or binary code; a vector in the Fibonacci numeral system is
referred to as a Fibonacci vector or Fibonacci code. All the Fibonacci vectors that represent the same value
are defined as equivalent vectors. Another very important identity of the Fibonacci sequence is
fm =
∑
m -2
k =0
fk
(5)
n
n
The n-bit binary vector can represent numbers in the range of [0, 2 -1], and therefore a total of 2 values
can be represented by n-bit binary vectors. From Eq. 5, we know that the range of an m-bit Fibonacci vector
is [0, fm+2−1], where the minimum value 0 corresponds to all the bits dk being 0, and the maximum value
corresponds to all dk being 1. Hence a total of fm+2 distinct values can be represented by m-bit Fibonacci
vectors.
5. Implementation & Experimental Results
Table-4 shows 6 bit code-words for 4 bit data-words which are generated using FTF-FNS codes. The
coded busses in the simulation were 6-bits wide. A 4- to-6-bit encoder and a 6-to-4-bit decoder logic were
implemented using mapping of data-words to code-words using FTF code-words. Our simulations using
Synopsys Design Compiler show that the maximum delay of both the encoder and the decoder was 10.23 ns.
Table. 4: 6 Bit FTF-FNS Code-words for 4 Bit Data-words.
4 bit data-words
(d3d2d1d0)
6 bit code-words
4 bit data-words
(c5c4c3c2c1c0)
(d3d2d1d0)
6 bit code-words
(c5c4c3c2c1c0)
0000
000000
1000
010101
0001
000001
1001
010111
0010
000100
1010
011100
0011
000101
1011
011101
0100
000111
1100
011111
0101
010000
1101
110000
0110
010001
1110
110001
0111
010100
1111
110100
Fig. 3: Gate Level Schematic for FTF-FNS Encoder
Fig. 4: Gate Level Schematic for FTF-FNS Decoder
This paper is based on the concepts proposed in [1]. The encoder and decoder presented in fig.3 and fig.
4 have a data arrival time of 4.08 ns and 6.15 ns respectively. The encoder and decoder proposed in [1] have
140
a data arrival time of 17.88 ns and 7.63 ns respectively. Thus the total delay for the CODEC is 10.23 ns
compared to encoder proposed in [1] have a total delay of 25.51 ns. So, we can say that our CODEC is
around 2.5 times faster than the CODEC proposed in [1]. When the data arrival time is small, it creates a
more positive slack, which makes the chip to work at higher frequencies.
Table. 5: Timing reports for FTF-FNS Encoder and Decoder.
Timing reports for FTF-FNS Encoder
Port/Point
Timing reports for FTF-FNS Decoder
Incr.
Path
Delay (ns)
Delay ( ns)
Port/Point
Incr.
Path
Delay (ns)
Delay ( ns)
Input/external
delay
0.00
0.00 r
Input/external
delay
0.00
0.00 f
b[2] (in)
0.00
0.00r
c[2] (in)
0.00
0.00 f
U34/Z (IV)
0.47
0.47 f
U53/Z (IV)
0.32
0.32 f
U33/Z (ND2)
1.25
1.72 r
U48/Z (NR2)
1.62
1.94 r
U29/Z (NR2)
0.34
2.06 f
U47/Z (ND2)
0.37
2.31 f
U28/Z (AO2)
1.56
3.63 r
U46/Z (IV)
0.93
3.25 r
U24/Z (AO3)
0.45
4.08 f
U44/Z (ND3)
0.70
3.94 f
c[2] (out)
0.00
4.08 f
U43/Z (AO7)
1.18
5.13 r
4.08
U42/Z (MUX21L)
0.45
5.58 f
U38/Z (ND2)
0.57
6.15 r
b[0] (out)
0.00
6.15 r
Data arrival time
Data arrival time
6.15
Table-5 shows the timing report of the data arrival time for the FTF-FNS encoder from input side to
output side. Prime-Time reports the worst delay path from input to output. The b[2] is the input port of the
encoder and the name in the bracket is the reference name for that port. Incr. path is the incremental path
delay. The delay from input port, b[2] to the output of and-or gate (U24/Z) which is the output port of
encoder, c(2) is 4.08 ns (See Fig-3). The f in the third column indicates a transition from 1 to 0 and r
indicates a 0 to 1 transition.Table-5 also shows the timing report of the data arrival time for the FTF-FNS
decoder from input side to output side. The c[2] is the input port of the decoder and the delay from input port,
c[2] to the output of nand2(U38/Z) which is the output port of decoder, b(0) is 6.15 ns (See Fig-4).
Table. 6: Timing, Power and Area Report.
Delay(ns)
Power(µw)
Area(µm2)
Encoder
4.08
4.7919
25
Decoder
6.15
6.4275
40
Any CODEC performance is quantified by measuring the area, power consumption and speed of the
CODEC which is required for any VLSI chip. Table-6 shows the reports generated using Design Compiler
Tool for both encoder and decoder. It has observed that the encoder and decoder occupied very small area
with low power consumption and very small delay.
6. Conclusion
FNS-based FTF encoding algorithms are very efficient in terms of area overhead. In this work, we
presented a novel method to avoid crosstalk using Forbidden Transition Free, Fibonacci Number System
CODEC. This work is much superior in terms of Speed, Power consumption and Area required for
implementing this CODEC. This CODEC has got an improved speed of around 2.5 times than the
implementation technique specified in [1].
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7. References
[1] Chunjie Duan, Victor Cordero, Sunil P. Khatri “Efficient On-Chip Crosstalk avoidance CODEC Design”
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65-nm CMOS technology”. In Proceedings of Int. Symposium on Quality Electronic Devices, pages312–317, 2006.
[3] C. Duan, K. Gulati and S.P. Khatri, “Memory-based Cross-talk Cancelling CODECs for On-chip busses”, ISCAS,
2006.
[4] Madhu Mutyam, “Preventing Crosstalk Delay using Fibonacci Representation”, Intl Conf. on VLSI Design, pp
685-688, 2004.
[5] S.R. Sridhara, A. Ahmed, and N.R. Shanbhag, “Area and Energy-Efficient Crosstalk Avoidance Codes for On-Chip
busses”, Proc. Of ICCD, PP 12-17, 2004.
[6] C. Duan and S.P. Khatri, “Exploiting Crosstalk to Speed up On-Chip busses:, DATE 2004.
[7] S.R. Sridhara and N.R. Shanbhag. “Coding for system-on-chip networks: a unified framework”. In Proceedings of
Design Automation Conference, pages 103–106. IEEE/ACM, 2004.
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[9] Duan .C, Tirumala .A and Khatri .S.P.,”Analysis and Avoidance of Cross-talk in On-chip Bus”, Hot Interconnects,
pp 133-138, 2001.
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The First Author J.Venkateswara Rao received B.Tech Degree from, VRSEC,
Nagarjuna University, Guntur, in 2000. M.Tech. Degree from NITW, Warangal, India
in 2003, pursuing Ph.D in the Department of Electronics and Communication
Engineering, JNT University, Hyderabad, INDIA. Currently he is working as Associate
Professor in the Department of Electronics and communication Engineering, VITS,
Hyderabad, INDIA, His research interest includes on chip crosstalk noise reduction in
VLSI Circuits. He published 4 papers on “on-chip crosstalk noise reduction in VLSI
circuits” in international journals and international conferences.
The Second Author Dr.P.Sudhakara Rao Completed Ph.D., Information and
Communication Engineering from Anna University, India, Masters in Electronics and
Communication Engineering from Anna University, India, Bachelors in Electronics
and Communication Engineering from Mysore University, India. Worked as deputy
Director, “Central Electronics Engineering Research Institute centre, India” for
over 25 years, 2 years as Vice-president, “Sieger Spintech Equipments Ltd., India”,
established an electronic department for the development of electronic systems for
nearly 2 years. Presently working with Vignan Institute of Technology and Science,
Nalgonda District, AP, INDIA as DEAN R&D, HOD ECE. He has one patent and 55 technical publications/
conference papers to his credit. Conducted many international and national conferences as chairman.
142
Author Index
A
Amnart Pohthong
Apisak Khankaewla
Arun Swaminathan
B
B. Arun Prasad
Bai Weixiong
Kyung-Min Park
108
126
67
1
8
C
Chenchen Zhang
Cheng-Jung Tsai
Chun-Cheng Peng
93
39
39
D
Dac-Nhuong Le
Deyu Feng
Dong Weisheng
Dr. V.M. Shenbagaraman
81
76
13
1
E
Eun-Ji You
62
F
Fu Xiaolong
8
G
Guangna Lv
H
Hoon Choi
I
Iain Phillips
J
Jayshree Suresh
Jiao Shuhong
Jiao Shuhong
Jizhang Fan
Jo-han Chang
Jukkrit Kluabwang
L
Lin Guan
Liu Jiayuan
Liu Mingzhu
87
62
98
117
13
51
113
34
126
143
98
51
13, 51
M
Md. Shahid Uz Zaman
Mehdi Asgarkhani
131
122
N
Narongrit Pimkumwong
Nguyen Le Dang
Nhu Gia Nguyen
126
81
81
P
P. Arun Kumar
Pan Liu
Pei-Cheng Cheng
Pengpeng Zheng
Phongsathon Fongta
Priyanka Ahlawat
1
76
39
44
28
19
R
Rajender Singh Chillar
19
S
S. Sundararajan
Shang Zhigang
Shaoying Huang
Sudhakara Rao P
Supat Sriyanaluk
Sutep Tongngam
117
8
44
137
108
72
T
Tae-Eun Yoon
Tatsana Thomthong
Tianyu Ding
Ting-Yi Chang
62
126
44
39
U
Usha Kumari
K
62
19
V
V.M. Shenbagaraman
Venkateswara Rao J
Vinh Trong Le
117
137
81
W
Wei Zheng
Wilawan Rukpakavong
Worasit Choochaiwattana
56
98
103
X
Xiangming Wen
Xiaohua Guo
Xiongfei Tao
Y
Yan Zhang
Yanan Fu
Yanhui Wang
Yanqiu Li
Yen-Lin Chen
Yi- ting Chen
Yuthapong Somchit
Z
Zhaoming Lu
Zhenmin Zhao
Zhicai Zhang
Zi Wang
56, 87
56
76
144
76
44
93
113
39
34
28
56
56, 87
87
93