2013-01-14
Computer Aided Design
of Electronics
[Datorstödd Elektronikkonstruktion]
Zebo Peng, Petru Eles, and Nima Aghaee
Embedded Systems Laboratory
IDA, Linköping University
www.ida.liu.se/~TDTS01
Electronic Systems
Zebo Peng, IDA, LiTH
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2013-01-14
Objectives

Basic principles of computer-aided design for
electronic systems (Electronic Design Automation).

Electronic system design at high levels of
abstraction.

Synthesis and optimization algorithms.

Test and design for testability techniques.

The hardware description language VHDL and its
use in the design/synthesis process.
Zebo Peng, IDA, LiTH
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TDTS01 Lecture Notes – Lecture 1
Course Organization

10 Lectures (Petru and Zebo):






Introduction and basic terminology.
VHDL: overview and simulation semantics.
Behavioral and structural modeling with VHDL.
High-level synthesis of digital systems.
Heuristics and optimization algorithms.
Testing and design for testability.

Invited industrial lecture (Björn Fjellborg, Ericsson)

Laboratory part (Nima):
 Three seminars on assignments and CAD systems.
 Lab assignments.
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Recommended Literature

G. de Micheli: “Synthesis and Optimization of Digital
Systems.”

Z. Navabi: “VHDL Analysis and Modeling of Digital
Systems.”
 Other VHDL books can also be used.
 A VHDL Cookbook is available at the course website.

Articles to be distributed, including:
 High-level synthesis of digital circuits.
 Optimization heuristics.
 Design for test and built-in self-test.

Lecture notes (www.ida.liu.se/~TDTS01).
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TDTS01 Lecture Notes – Lecture 1
Lecture I




Trend in microelectronics
The design challenges
Different design paradigms
The test problems
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The Technological Trend
Moore’s Law:
Number of transistors per chip
would double every 1.5 years
# of trans.
1000 M
750 M
Clock Frequency (every 2 years)
Performance
Memory capacity
50 M
25 M
year
75
80
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90
95
7
00
05
10
TDTS01 Lecture Notes – Lecture 1
Intel Microprocessor Evolution
Intel 8‐core Xeon
2.3 Billion Transistor
45nm Intel 4004
2.3 Thousands transistors
10000 nm
8
Images courtesy of Intel Corporation
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The SIA Roadmap
Year
2002 2005 2008 2011 2014
Feature size (nm)
2
Logic: trans/cm
Trans/chip
#pads/chip
Clock (MHz)
2
Chip size (mm )
Wiring levels
Power supply (V)
High-perf pow (W)
Battery pow (W)
130 100
18M 44M
67.6M 190M
2553 3492
2100 3500
430 520
7
7-8
1.5
1.2
130 160
2
2.4
70
50
35
109M 269M 664M
539M 1523M 4308M
4776 6532 8935
6000 10000 16900
620 750
900
8-9
9
10
0.9
0.6
0.5
170 175
183
2.8
3.2
3.7
SIA = Semiconductor Industry Association
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TDTS01 Lecture Notes – Lecture 1
System on Chip (SoC)
Hardware
Software
Microprocessor
Embedded
memory
ASIC
Analog
circuit
DSP
Source:
S3
Source: Stratus
Computers
Network
Sensor
High-speed electronics
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Lecture I
Trend in microelectronics




The design challenges
Different design paradigms
The test problems
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TDTS01 Lecture Notes – Lecture 1
Main Design Tasks

System specification (functional and requirement)

Hardware/software trade-offs

Architecture selection and exploration

Synthesis and optimization

Implementation

Testing and design for testability

Analysis and simulation

Verification and validation

Design management: storage of design data,
cooperation between tools, design flow, etc.
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Design Objectives


Unit cost: the cost of manufacturing each copy of the system,
excluding NRE cost.
NRE cost (Non-Recurring Engineering cost): The onetime cost of designing the system.




Size: the physical space required by the system.
Performance: the execution time or throughput .
Power: the amount of power consumed by the system.
Testability: the easiness of testing the system to make sure
that it works correctly.

Flexibility: the ability to change the functionality of the system
without incurring heavy NRE cost.

Correctness, safety, etc.
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TDTS01 Lecture Notes – Lecture 1
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Mixed Technologies for Electronics

Embed in a single chip:
Logic, Analog, DRAM blocks

Embed advanced technology
blocks:
 FPGA, Flash,
RF/Microwave
 MEMS (Micro Electro
Mechanical Systems)
Zebo Peng, IDA, LiTH
LOGIC
FLASH
Analog
FPGA
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SRAM
 Optical elements
DRAM
RF
Beyond Electronic

Logic
TDTS01 Lecture Notes – Lecture 1
The Challenges

System complexity
 Increasing functionality and diversity
 Increasing performance

Stringent design requirements
 Low cost
 Low power
 High reliability, testability, and flexibility

Technology challenges for cost-efficient implementation
 Deep submicron effects
 Issues related to process variation
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Possible Solutions

Powerful design methodology and tools.

Advanced architecture (modularity).

Extensive design reuse.
Design Paradigm
Shift
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TDTS01 Lecture Notes – Lecture 1
Lecture I




Trend in microelectronics
The design challenges
Different design paradigms
The test problems
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Capture and Simulate

The detailed design is
captured in a model.

The model is
simulated.

The results are used to
guide the improvement
of the design.

All design decisions
are made by the
designers.
Zebo Peng, IDA, LiTH
a
b
c
o
d
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TDTS01 Lecture Notes – Lecture 1
Abstraction Hierarchy



Layout/silicon level  The
physical layout of the integrated
circuits is described.
in
out
Circuit level  The detailed
circuits of transistors, resistors,
and capacitors are described.
Logic (gate) level  The design
is given as gates and their
interconnections.
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a
b
c
o
d
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Abstraction Hierarchy (Cont’d)



Register-transfer level (RTL) 
Operations are described as
transfers of values between
registers.
p
O
R1
R2
clk
For I=0 To 2 Loop
Wait until clk’event and clk = ´1´;
If (rgb[I] < 248) Then
P = rgb[I] mod 8;
Q = filter(x, y) * 8;
End If;
Algorithmic level  A system is
described as a set of usually
concurrent algorithms.
System level  A system is
described as a set of processors
and communication channels.
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TDTS01 Lecture Notes – Lecture 1
Gajski’s Y-Chart
Behavioral
domain
Structural
domain
System level
RT - level
Algorithms, processes
Register-Transfer Spec.
Logic level
Circuit level
Boolean Eqn.
CPU, Memory, Bus
ALU, Reg., MUX
Gate, Flip-Flop
Transistor functions.
Transistor
Transistor layouts
Standard-Cell/Subcell
Macro-Cell, chips
Board, MCMs
Physical/geometrical
domain
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The Three Domains

Structural domain — A component is described
in terms on an interconnection of more primitive
components.

Behavioral domain — A component is described
by defining its input/output response.

Physical/geometrical domain — A component is
described in terms of its physical placement and
characteristics (e.g., shape).
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TDTS01 Lecture Notes – Lecture 1
A Typical Top-Down Design Process
Behavioral
D om ain
Informal
Specification
Sy stem le v el
1
S tru ct u ral
D om ain
RT - lev e l
Lo gic le ve l
Algo rithm s, p roc e sse s
R eg iste r- Tran sfe r S pe c.
C PU , Me m ory, Bu s
AL U, R eg., M U X
C irc uit le v el
B oole an Eq n.
G ate , F lip -F lop
Tra nsisto r func tions.
Transistor
Tra nsistor lay ou ts
S ta nda rd -Ce ll/S ubc e ll
Ma cro-C ell, chips
B oard, M C M s
Physical D om ain
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Describe and Synthesize Paradigm



Description of a design in terms of behavioral
specification.
Refinement of the design towards an implementation by
adding structural details.
Evaluation of the design in terms of a cost function and
the design is optimized w.r.t. the cost function.
a
b
c
o1 = (a + b) c + d c;
o2 = (d +f) c;
o3 = (a + b) d + d f;
...
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d
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TDTS01 Lecture Notes – Lecture 1
High-Level Describe and Synthesize



Description of a design in terms of behavioral
specification.
Refinement of the design towards an implementation by
adding structural details.
Evaluation of the design in terms of a cost function and
the design is optimized for the cost function.
For I=0 To 2 Loop
Wait until clk’event
and clk=´1´;
If (rgb[I] < 248) Then
P=rgb[I] mod 8;
...
p
R
O
clk
enable
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Core-based Design
Utilization of pre-designed and pre-verified cores:

 Reuse of large IP blocks, such as CPU, DSP, memory modules,
communication infrastructure, and analog blocks.

Divide-and-conquer design methodology.

Flexibility based on different core description levels:
 Soft: RT level (synthesizable
VHDL/Verilog).
 Firm: Gate-level netlist.
DRAM
 Hard: Layout.
DSP
RF
SRAM
Legal issues:

CPU
FPU
 IP right protection.
UDL
 Liability in case of failures.
Zebo Peng, IDA, LiTH
ANALOG
ROM
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TDTS01 Lecture Notes – Lecture 1
Platform-based Design

A platform is a partial design:




for a particular application area;
includes embedded processor(s);
may include embedded software;
customizable to specific requirements.

A platform captures the good solutions to the important
design challenges in a given application area.

A method for design re-use at all abstraction levels
based on assembling and configuring platform
components in a rapid and reliable fashion.
 It reuses architectures.
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Platform-based Design Steps

Design the platform.
 A highly configurable system
architecture.
 Optimize for performance, power,
etc.
requirements
 Useful for a set of applications.
platform
 Tools to explore the different
configurations.

Use the platform.
 Modify hardware components for
the customer’s needs.
 Optimize the software.
user
needs
product
 HW/SW integration and test.
Zebo Peng, IDA, LiTH
past designs
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TDTS01 Lecture Notes – Lecture 1
Lecture I




Trend in microelectronics
The design challenges
Different design paradigms
The test problems
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Testing and its Current Practice



Testing aims at the detection of physical faults
(production errors/defects and physical failures).
Different from the design task, testing is performed on
each individual chip, after they are manufactured.
The common approach to perform testing is to utilize an
Automatic Test Equipment (ATE).
Automatic Test Equipment
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TDTS01 Lecture Notes – Lecture 1
Testing of Mixed Technologies
How to test the mixed chip?

DRAM
FLASH Analog
FPGA
SRAM
 Usually time
consuming.

LOGIC
RF
Use multiple ATEs for a
single chip: Logic ATE,
Memory ATE, Analog
ATE, etc.
Logic
Employ a super ATE
with combined
capabilities.
 Usually very expensive.
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High Complexity
# of transistors
increases
exponentially.

Implications of SIA Roadmap: Testing
Testing Complexity Index - [#Tr. per Pin]
# of access port
remains stable.

1.60E+ 5
1.40E+ 5
1.00E+ 5
8.00E+ 5
Implication:

6.00E+ 4
 # of transistors
per pin (Testing
Complexity
Index) increases
rapidly.
Zebo Peng, IDA, LiTH
4.00E+ 4
2.00E+ 4
0.00E+ 0
Year
1992
F. Size [m] 0.5
1995
0.35
1998
0.25
2001
018
2004
0.12
2007
0.1
Source: W. Maly, 1996
Source: SIA Roadmap
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TDTS01 Lecture Notes – Lecture 1
Built-In Self Test (BIST)
Solution: Dedicated built-in
hardware for embedded test
functions.






No need for expensive
ATE.
At-speed testing.
Concurrent test
possible.
Support O&M.
Support field test and
diagnosis.
Zebo Peng, IDA, LiTH
External
Test
Standard
Digital Tester
Limited
Speed/
Accuracy
Low
Cost-per-Pin
Built-In
Embedded Test
Pattern Generation
Result Compression
Diagnostics
Power Management
Test Control
Support for
Board-level Test
System-Level Test
Memory
Logic
MixedSignal
I/Os &
Interconn.
Source: LogicVision
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Challenges to CAD Communities







System specification with very high-level
languages.
Modeling techniques for heterogeneous system.
Hardware/software co-design.
Testing issue to be considered during the design
process.
Design verifications -> get the whole system right
the first time!
Very efficient power saving techniques.
Global optimization.
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TDTS01 Lecture Notes – Lecture 1
The Electronics System Designer
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Conclusion Remarks

Much of design of digital systems is managing
complexity.

What is needed: new techniques and tools to help
the designers in the design process, taking into
account different aspects.

We need especially design tools working at the
higher levels of abstraction.

If the complexity of the microelectronics technology
will continue to grow, the migration towards higher
abstraction level will continue.
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