2014-03-04
TDTS 01 Lecture 10
Built-In Self Test (BIST)
Zebo Peng
Embedded Systems Laboratory
IDA, Linköping University
Lecture 10




Introduction and basic
principles
Pattern generation techniques
Signature analysis methods
Final remark
Zebo Peng, IDA, LiTH
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2014-03-04
External Hardware Testing
Circuit Under Test (CUT)
Automatic Test Equipment (ATE)

Drawbacks of external testing:
ATE are expensive (typically several millions US$).
ATE will become more and more inefficient.
Increase of test data volume.
Increase of test application time.
Zebo Peng, IDA, LiTH
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TDTS01 Lecture Notes – Lecture 10
Basic Principle of BIST
Test Pattern Generation (TPG)
BIST
Control Unit
Circuitry Under Test
CUT
Test Response Analysis (TRA)
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Why BIST?

No expensive test equipment is needed.

Test during operation and maintenance becomes also
possible.

Uniform technique for production, system and
maintenance tests is achieved.

Dynamic properties of the circuit can be tested at speed.

High-speed testing is enabled.

Support concurrent testing.
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TDTS01 Lecture Notes – Lecture 10
BIST Costs

Silicon area overhead for:
 Test controller.
 Hardware pattern generator.
 Hardware response compacter.
 Testing of BIST hardware itself.

Pin overhead: at least 1 pin needed.

Performance overhead: extra path delays.

Yield loss: due to increased chip area.

Increased BIST hardware complexity: especially when
BIST hardware should also be testable.
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Tasks to be Solved

Methods for pattern generation.

Methods for response evaluation.

Test planning and control.

BIST architecture.
Test Pattern Generation (TPG)
BIST
Control Unit
Circuitry Under Test
CUT
Test Response Analysis (TRA)
Zebo Peng, IDA, LiTH
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TDTS01 Lecture Notes – Lecture 10
Lecture 10




Introduction and basic
principles
Pattern generation techniques
Signature analysis methods
Final remark
Zebo Peng, IDA, LiTH
8
TDTS01 Lecture Notes – Lecture 10
4
2014-03-04
Methods for Pattern Generation

Exhaustive pattern generation.

Pseudo-exhaustive testing.

Pseudo-random pattern generation.

Deterministic testing.
Zebo Peng, IDA, LiTH
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TDTS01 Lecture Notes – Lecture 10
Exhaustive Testing

All possible patterns are applied to the inputs.
 Complete for all static faults, If the module is
combinational.
 For test pattern generation, a counter or a complete
linear feedback shift register (LFSR) can be used.

It is usually not practical if the number of inputs,
n
n, is very large (2 patterns are needed).

It is generally not applicable to sequential
circuits.
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Pseudo-Exhaustive Testing

Reduced # of tests from 28 = 256 down to 25 x 2 = 64
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TDTS01 Lecture Notes – Lecture 10
Pseudo-Random Testing

Stimulate CUT with a random pattern sequence of length M.

The patterns are generated by a deterministic algorithm,
implemented in hardware.

Usually only a fraction of the total 2N patterns is applied (N is
the number of inputs).

If the response is correct for each pattern, the circuit is
assumed to be fault-free with certain probability P.
 How to determine M for a given P?
•
Usually by fault simulation.
 How to make sure that the test sequence is random?
•
Using Linear Feedback Shift Registers.
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Linear Feedback Shift Registers

Standard Linear Feedback Shift Register (LFSR)
Produces patterns algorithmically  repeatable;
Has most of desirable random-number properties.

A relatively long sequence is usually needed for good
fault coverage.
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TDTS01 Lecture Notes – Lecture 10
Problem of Pseudo-Random BIST
100%

Target FC
Pseudo-random
test problems:
Fault Coverage
 Very long test
application time
 Relatively low fault
coverage
Time
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A Solution to the BIST Problem
• Combination of pseudo-
100%
Fault Coverage
random test and
deterministic test to form
a hybrid BIST solution
in order to:
- increase the fault
coverage, and/or
- reduce the test cost
Time
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TDTS01 Lecture Notes – Lecture 10
Deterministic Pattern Generation

A fixed set of “optimal” test patterns—usually derived
from fault simulation or circuit analysis— is used.
Stored test patterns:
Area overhead for ROM
Encoded test patterns:
Computing complexity for encoding
Hardware complexity for decoding
Encoding techniques:
Store and generate
Non-linear feedback shift registers
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Store and Generate

Given:
 Deterministic test set T.
LFSR or Counter
ROM

Problems:
 Too many patterns in T.
(X1, X2 , ..., Xk )
 Too many bits per pattern.
 Need very large memory.

(Xk +1, Xk+2 , ... X n )
T’
Solution:
 Store only a few bits of a
few patterns.
 Generate the other bits
and patterns by an LFSR
or a counter.
Zebo Peng, IDA, LiTH
Decoding Networks
T
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TDTS01 Lecture Notes – Lecture 10
Store and Generate Example
101000
101001
101010
101100
101101
101110
101000
101001
101010
101011
101100
101101
101110
101111
LFSR or Counter
ROM
(X1, X2 , ..., Xk )
(Xk+1, Xk+2 , ... Xn )
T’
Decoding Networks
101 XXX
Zebo Peng, IDA, LiTH
T
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2014-03-04
Lecture 10




Introduction and basic
principles
Pattern generation techniques
Signature analysis methods
Final remark
Zebo Peng, IDA, LiTH
19
TDTS01 Lecture Notes – Lecture 10
Response Compaction

We have a huge amount of data in CUT’s responses to
LFSR patterns.
Ex.
 Generate 5 million random patterns
 CUT has 200 outputs
 5 million x 200 = 1 billion bits responses

Uneconomical to store and check all of these responses
on chip.

Responses must be compacted and only the signature is
compared.
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Methods for Response Evaluation

Compact test response into a single register value.
Ex.
 Parity check.
 One counting.
 Signature analysis.

Evaluate register content after test is completed.
Go/No-go decision is given at the end.

Problem: Information loss during compression.

 Aliasing: Content of register is correct while the CUT response
was faulty.
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TDTS01 Lecture Notes – Lecture 10
Modular LFSR Compacter Example
LFSR seed value is “00000”
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Multiple-Input Signature Reg.(MISR)

Problem with ordinary LFSR response compacter:
 Too much hardware if one of these is used to compact
each primary output (PO).

Solution: MISR – compacts all outputs into one LFSR.
Zebo Peng, IDA, LiTH
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TDTS01 Lecture Notes – Lecture 10
Built-in Logic Block Observer (BILBO)

Combined functionality of D flip-flop, pattern generator,
response compacter, and scan chain.
Zebo Peng, IDA, LiTH
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A Complex BIST Architecture

Testing phase I:
 LFSR1 generates tests for CUT1 and CUT2.
 BILBO2 and LFSR3 compact CUT1 and CUT2 responses,
respectively.

Testing phase II:
 BILBO2 generates test patterns for CUT3.
 LFSR3 compacts CUT3 responses.
Zebo Peng, IDA, LiTH
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TDTS01 Lecture Notes – Lecture 10
Summary

BIST is a very powerful technique with many
advantages.

It can support testing
in the wafer,
after packaging,
after assembling a chip in the board,
after integrating the board in the system, and
during operation and maintenance.

It will lead to built-in quality in the life-cycle of a
product.
Zebo Peng, IDA, LiTH
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TDTS01 Lecture Notes – Lecture 10
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2014-03-04
Lecture 10




Introduction and basic
principles
Pattern generation techniques
Signature analysis methods
Final remark
Zebo Peng, IDA, LiTH
27
TDTS01 Lecture Notes – Lecture 10
Examination and Feedback

Wednesday, March 19, 14:00-18:00.

Closed book.

Answers can be written in English or/and Swedish.

Cover mainly the topics discussed in the lectures:
 Follow the lecture notes when preparing for the exam.

Examples of previous exams available at the website.

Please provide feedback of the course:
 Please send me your comments by emails.
 Please fill in the web-based course evaluation!
Zebo Peng, IDA, LiTH
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TDTS01 Lecture Notes – Lecture 10
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