2014-02-21
TDTS 01 Lecture 9
Design for Testability
Zebo Peng
Embedded Systems Laboratory
IDA, Linköping University
Lecture 9



The test problems
Fault modeling
Design for testability techniques
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2014-02-21
What is Testing?

To examine a product to ensure that it functions correctly
and exhibits the properties and capabilities it was
designed to possess.
Automatic Test Equipment

Testing is an important activity in the life-cycle of an
electronics product.
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TDTS01 Lecture Notes – Lecture 9
Life-Cycle of an Electronic System
Specification
Design
Implementation
Production
Validation
Verification
Review
Inspection
Simulation
Test Preparation
and DFT
Production Test
Integration Test
Testing
System Test
Operation and
Maintenance
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Causes of Incorrect Functions

Design errors
 usually consistent

Fabrication (manufacturing) errors
 often consistent, e.g., wrong components
 usually mistakes by operators

Fabrication (manufacturing) defects
 inconsistent, e.g., impurity of materials

defects
Physical failures
 wear-out
 environmental factors
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TDTS01 Lecture Notes – Lecture 9
Defect Example
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The Stuck-At Fault Model

Every fault in a circuit changes its functionality as if
some nodes were steadily tied to either logic 0 or 1.
S-A-0
a
b
c
o
d
Total no of faults = 3

N
-1
A single stuck-at model is usually used. That is, we
assume that only one node at a time is tied to 0 or 1.
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TDTS01 Lecture Notes – Lecture 9
Single Stuck-At (SSA) Fault Model

Number of possible faults is small (2N).

Capable of representing many different physical faults.
Test patterns produced for SSA faults detect also many
other faults.
Facilitate the use of Boolean algebra mathematics in
deriving test patterns.
Technology independent.




SSA fault coverage remains an established metric for
test quality, and is still widely used in the industry.
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Bridging Faults
An AND-bridging example
a
b
c
o
AND
d



Technology dependent (e.g., a short-circuit can lead to
an AND-bridging, OR-bridging or dominance-bridging).
Faults are related to the placement of the components.
Fault activation and propagation are more difficult.
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TDTS01 Lecture Notes – Lecture 9
Composition of Costs of Testing

Cost of test equipment (hardware):





A test controller (usually a computer).
Interface drivers and receivers and cable-connections.
System of probe-contacts.
A controlled environment (e.g., a temperature chamber).
Cost of software supports:
 Test pattern generation programs.
 Test-design verification procedures (fault simulation and
analysis).

Testing time:
 Test development time.
 Test application time.
ATE
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Test = Optimization
Testing and DFT are optimization problems:
 To minimize the total test cost, C(x), defined as:
Ctest = Cdev + Cappl + Csilicon + Cquality

Subject to a set of constraints, Gi(x), i = 1,2, …k






test strategy and methods
fault coverage requirement
power consumption
ATE and tool limitation
test and DFT engineers
…
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TDTS01 Lecture Notes – Lecture 9
Types of Testing

Production test — testing of individual products to check
whether faults are introduced during the manufacturing
phase. It is assumed that the design is correct.

System test — testing of the product in the environment
where it is operating to ensure that it works correctly when
interconnected with other components.

Burn-in — testing at elevated temperature and voltage to
accelerate and detect early life failures.

Operation and maintenance test — testing of the product in
the filed for diagnosis or "preventive" purpose.

Prototype test — testing to check for design faults during the
system development phase. Diagnosis is required.
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Lecture 9



The test problems
Fault modeling
Design for testability techniques
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TDTS01 Lecture Notes – Lecture 9
Design for Testability (DFT)

To take into account the testing aspects during the
design process so that more testable designs will be
generated.

Advantages of DFT:
 Reduce test efforts.
 Reduce cost for test equipment.
 Shorten time-to-market.
 Increase product quality.

Limitations:
 Hardware overhead, 5-30%, and performance degradation.
 Increased design complexity.
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Controllability and Observability

The key to design for testability is the ability to control
and observe directly the internal states.

Controllability of an internal node - ability to set it to a
specific logic value.
Observability of an internal node - ability to observe its
specific logic value on primary output.

S-A-0
a
b
c
o
d
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TDTS01 Lecture Notes – Lecture 9
Ad Hoc DFT Techniques
Good design practices learnt through experience are used
as guidelines:

OP
Test point insertion:
C1
C1
a1
o1
C2
CP0
(a) original design
C2
CP1
(b) 0/1-injection and observation
 Very simple.
 Can be used in principle anywhere.
 Large overhead of I/O ports (-> multiplexing and addressing)
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Ad Hoc DFT Techniques (Cont’d)

Design circuits to be initializable.

Provide easy reset.

Eliminate asynchronous logic.

Control/bypass internal clocks and oscillators.
Q
Q
Q
Q
…
Q
Q
Clock
Reset
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TDTS01 Lecture Notes – Lecture 9
Ad Hoc DFT Techniques (Cont’d)

0
Redundancy must be avoided or controlled.
Stuck-at-0 on X is a redundant fault!
a
1b
1
2
01c
x
stuck-at-0
1
3
0
4
0
z = ab + bc + ac = ab + ac
z
a
b
c
z
A Hazard-Free Circuit

High sequential depth should be avoided.

Combinational feedback loops should be avoided since
they result in additional hidden storage elements.
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Disadvantages of Ad-Hoc Methods

Experts and tools not always available.

Test generation must often be manually performed
with no guarantee of high fault coverage.

Design iterations may be needed, which is very time
consuming.
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TDTS01 Lecture Notes – Lecture 9
Structural DFT Techniques
Can be applied to any design in a systematic way:

Full scan.

Partial scan.

Boundary scan.

Built-in self-test (BIST).
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Basic Scan Technique


Sequential circuits have poor controllability and poor
observability.
To address this problem, the flip-flops are connected into
a long shift register.
PI
Combinational
part
Scan Out
PO
PI
PO
Scan Out
In test mode,
the flip-flops will
be controlable
and observable.
Scan In
Scan In
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Combinational
part
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TDTS01 Lecture Notes – Lecture 9
Scan Design

Circuit is designed using pre-specified design rules.

Test structure is added to the completed design:
 Add a test control (TC) primary input.
 Replace flip-flops by scan flip-flops (SFF), and connect them
to form one or several shift registers in the test mode.
 Make input/output of each scan shift register
controllable/observable from PI/PO.

Full scan = all flip-flops are included in the scan path:
 The problem of ATPG for sequential circuits is reduced to
ATPG for combinational ones.
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Scan Design Rules

Use only clocked D-type of flip-flops for all state
variables.

At least one PI pin must be available for test;
more pins, if available, can be used.

All clocks must be controlled from PIs.

Clocks must not feed data inputs of flip-flops.
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TDTS01 Lecture Notes – Lecture 9
Correcting a Rule Violation

All clocks must be controlled from PIs.
Comb.
logic D1
Q
Comb.
logic
FF
D2
CK
Comb.
logic
Q
D1
D2
Zebo Peng, IDA, LiTH
FF
CK
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Comb.
logic
TDTS01 Lecture Notes – Lecture 9
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Scan Flip-Flop (SFF)
Master latch
D
Slave latch
TC
Q
MUX
SD
Q
CK
D flip-flop
Master open Slave open
CK
Normal mode, D selected
TC
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t
Scan mode, SD selected
t
TDTS01 Lecture Notes – Lecture 9
Scan Overheads

IO pins: One pin necessary.

Area overhead:
 Gate overhead = [4 Nff/(Ng + 10 Nff)] x 100%,
where Ng = No. of comb. gates; Nff = No. of flip-flops.
• Example: Ng = 100k gates, Nff = 2k flip-flops, overhead = 6.7%.
 More accurate estimate must consider scan wiring and layout
area.

Performance overhead:
 Multiplexer delay added in combinational path; approx. two
gate-delays.
 Flip-flop output loading due to one additional fanout; approx.
5-6%.
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Partial Scan

A subset of FFs is selected for the scan path.

Advantages:
 reduced area overhead.
 avoid performance degradation.
 reduced test application time.

Disadvantages:
 design time may increase.
 need a sequential ATPG tool.
 need a method for selecting the partial scan subset.
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TDTS01 Lecture Notes – Lecture 9
Partial-Scan Architecture
PI
PO
Combinational
circuit
CK1
FF
CK2
FF
SCANOUT
SFF
TC
SFF
SCANIN
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A Partial-Scan Method

Select a minimal set of flip-flops for scan to eliminate all
cycles.
Q
Combinational
Q
Q
Q
Q
Q

Alternatively, in order to keep the overhead low, only
long cycles will be eliminated.

In some circuits with a large number of self-loops, all
cycles other than self-loops will be eliminated.
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TDTS01 Lecture Notes – Lecture 9
Partial Scan Example
Circuit: TLC, 355 gates, 21 flip-flops
Scan
flip-flops
Max. cycle Depth* ATPG Fault sim. Fault
length
CPU s
CPU s
cov.
ATPG Test seq.
vectors length
0
4
14
1,247
61
89.01%
805
805
4
2
10
157
11
95.90%
247
1,249
9
1
5
32
4
99.20%
136
1,382
10
1
3
13
4
100.00%
112
1,256
21
0
0
2
2
100.00%
52
1,190
* Cyclic paths ignored
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Summary

Testing is mainly used to find physical defects introduced
during the manufacturing and operation phases.

It is an expensive and complex task, and is becoming more
and more difficult with the development of complex systems.

Testability must be taken into account at all stages of the
design and synthesis process.
 In particular, early testability consideration prevents costly design
iterations.

The key to successful testing lies in the design process!
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