1/30/2014
TDTS01
Computer Aided Design of Electronics
2nd Lab presentation
Nima Aghaee
Embedded Systems Laboratory
(ESLAB)
2014
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TDTS01
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2nd Lab presentation
QUESTIONS ?
2014
1
1/30/2014
Assignments
• Project specification and tool set experience
[deadline: 13-Feb]
• Compilable design and testbench
[deadline: 25-Feb]
• Synthesizable design
[deadline: 07-Mar]
• Manufacturing test
[deadline: 14-Mar]
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Assignment 2
• Compilable design and testbench
[deadline: 25-Feb]
• Demonstration
– Explain, briefly, the codes (design and testbench)
– Simulate the design with a testbench
• Correct functional output
• Correct timing behavior
– Explain, briefly, the wave window based on VHDL codes
• Report
– Should provide proofs that you have successfully completed all of it
• Explain, briefly, your codes and experiences you had during the development
• Email the codes and other files (e.g. do file and file that includes validation
data)
• Include shots of wave or transcript window with brief explanation
– Include the explicitly requested material in the report
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Example Design
• Reviewing the example design used in 1st assignment
• Project specification
– Functional behavior
• Example: eight 4-bit unsigned numbers are summed to make one 7-bit
unsigned number
– Timing behavior (in respect to hand-shaking signals)
• Inputs - example:
– BUSY indicates that the circuit is not busy. There are two 4-bit input ports, A_IN and B_IN.
– START signal initiates reading of pairs of inputs from A_IN and B_IN consecutively at every
CLK cycle, up to four cycles (reading 8 numbers)
– The busy signal is active until the computation is complete.
• Outputs - example:
– VALID signal indicates that the output is ready at the output port
– C_OUT, the only output port which is 7 bits wide
– The valid output remains active until the circuit receives a reset signal or a new
computation is started by receiving a START signal.
4
– Targeted design metric (area xor delay)
4
• In the example there are two designs (architectures)
A_IN
B_IN
VALID
BUSY
START
– Behavioral: Higher CLK frequency
– Less_States: Lower area
ARRAY_ACC
RST
CLK
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C_OUT
x
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Entity
• It basically says how the design is related to the
outside world
– For example its ports
• Pay attention to
– CLK and RST
– Types: std_logic and std_logic_vector
– Vector range is defined using “downto”
4
4
A_IN
B_IN
C_OUT
7
VALID
BUSY
START
ARRAY_ACC
RST
CLK
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Entity - Recommendations
• Always CLK and RST
– CLK: In this lab only synchronous circuits
– RST: Required for ASIC designs
• FPGA/CPLD designs sometimes can be done w/o it
• Use std_logic and std_logic_vector
– Shows things in simulation that otherwise might not be visible.
Most importantly
• “X” forced unknown and
• “U” uninitialized
– Supports High-Impedance (Z) bus design
• Use “downto” for vector range
– The MSB will be placed to the left (easy to interpret and work
with)
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Architecture – General Form
•
•
CLK: rising edge
RST: asynchronous and active-high
– Every signal, other than RST, has only an effect when the CLK’s rising edge happens
– This is why the circuit is synchronous but has an asynchronous reset
•
•
Reset (Initialize) all signals
Main code body works with rising CLK edge
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Architecture – less_states
• Show it from compendium …
• Draw the signals on the board …
• Why ('0' & A_IN) + ('0' & B_IN)?
– Equal bit-width in signal assignment
– To accommodate the carry, other alternatives
• Saturate
• Overflow signal
• Why INPUT_COUNT<=(others=>'0')?
– The circuit should accept successive inputs w/o
reset
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Architecture – Improvements
• Do you see any obvious modifications that will
not affect the correct operation of the design?
– Is there anything that could be
• Moved?
• Removed?
• Show the code again …
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Architecture – Discussion
• Clearing INPUT_COUNT<=(others=>'0') could
be done the same time that START signal
activates
• BUSY output is in fact WORKING_STATE signal
• The design could be simulated w/o a
testbench by using the wave window
capabilities
– Force…
– Clock…
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2nd Lab presentation
QUESTIONS ?
2014
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Testbench - Introduction
•
•
•
•
Entity without ports (everything is inside)
Does not need to be synthesizable
Use as many processes as you like
Generate CLK and RST
– Signal assignment is a process (driver is in the sensitivity list)
• Plug in (instantiate) your design
constant PERIOD
: time
:= 50 ns;
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Testbench - RAM
• This RAM is only for simulation
– Synchronous write
– Asynchronous read
• Used to keep validation data loaded from file
constant
subtype
type
signal
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RAM_DEPTH
: integer := 25;
RAM_WORD is std_logic_vector(10 downto 0);
RAM_MEMORY is array (0 to RAM_DEPTH - 1) of RAM_WORD;
RAM_1
: RAM_MEMORY;
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Tetsbench – Validation Data
• Could be generated by a computer program
– Using very high level description of the project
• Here, it is made manually
– Serial number
– Two input ports
– Four serially fed inputs
– The correct result
• Three validation sets
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Testbench – Loading into RAM
• Show LOAD_FILE_PROCESS in compendium …
• Important to notice:
–
–
–
–
How the file is opened
Wait for power-on-reset
How the serial number is checked (assert)
Concatenation
• (SERIAL_NUMBER_LOAD_FILE & C_LOAD_FILE & '0')
– Multiple assignments to RAM_WRITE_SIG
• No problem for the final circuit
• However, is not a good idea for SW programs
• May slow down the simulation (in general not an issue)
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Testbench - Validation
• Show VALIDATION_PROCESS in compendium …
• Important to notice:
– How it waits until FILE_IS_LOADED
– How it waits for BUSY_SIG
• How it activates START_SIG
– How RAM_DATA_OUT is parsed
• (10 downto 8)
• (7 downto 4)
– How it waits for VALID_SIG
– Validation (using assertion)
• Going for next validation set
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2nd Lab presentation
QUESTIONS ?
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Do file
• An script that minimizes your effort to run a new
simulation
–
–
–
–
Files to be compiled
The entity to be simulated
Signals to be added to the wave window
Execute for desired length of simulation time (in
simulation world not your computer’s run time)
– And more …
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Assignments
• Project specification and tool set experience
[deadline: 13-Feb]
• Compilable design and testbench
[deadline: 25-Feb]
• Synthesizable design
[deadline: 07-Mar]
• Manufacturing test
[deadline: 14-Mar]
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Assignment 3 - Synthesizable design
• Compilable design
– Compiles with ModelSim w/o errors/warnings
• Simulation completes successfully
• Synthesizable design
– LeonadroSpectrum synthesizes it
• Gate-level netlist is generated successfully
• The example design is also synthesizable
– It is fine if it happens in your case
– The design decisions should support targeted
design metric
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Assignment 3 - Demo
• Synthesizable design
[deadline: 07-Mar]
• Explain, briefly, how different the code (design) is
compared to the compilable design
– Problems you faced to achieve a synthesizable design and
how you solved them (if any)
• Simulate the design with the testbench
– Correct functional output
– Correct timing behavior
• Is there a visible difference between compilable and
synthesizable design in wave window?
• Explain, briefly, the design decisions made in favor of
the targeted design metric
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Assignment 3 - Report
•
•
•
Synthesizable design
[deadline: 07-Mar]
Should provide proofs that you have successfully completed all parts of
the assignment
Explain, briefly, how different the code (design) is compared to the
compilable design
– Problems you faced to achieve a synthesizable design and how you solved
them (if any)
– Explain, briefly, your code and experiences you had during the development
•
•
Email the codes and other files (e.g. do file and file that includes validation
data)
Include shots of wave or transcript window with brief explanation
– Is there a visible difference between compilable and synthesizable design in
wave window?
•
•
2014
Explain, briefly, the design decisions made in favor of the targeted design
metric
Include the explicitly requested material in the report
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Assignment 3 - Example
• VHDL codes written similar to the example are
synthesizable
– Not too abstract (High-level)
– Not with bad (non-synthesizable) details
• Targeted design metric, for the example’s
architectures
– BEHAVIORAL: Logic depth (and therefore the
critical path) is shorter => Faster
– LESS_STATES: Less states => Less memory
elements (registers, flip flops) => Smaller area
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Assignment 3 - Synthesis
• In case the design is not synthesizable
– Read the messages by Leonardo carefully
– Interpret the messages
• Sometimes looking into the simulation results helps
– Make changes that resolves the issue
– Simulate again to make sure that the design’s
functional and timing behavior is intact
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Assignment 3 – Design Metric
• One way of explaining design choices made
for targeted design metric is to assume
another design that would have worse
area/delay compared to the selected
architecture
– Name and explain the differences that made the
selected design a better (smaller/faster) design
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Optimization & Abstraction
• Design in a higher abstraction levels
– More opportunity for optimization
• Very little can be done for a design in “Layout” level
– Larger search space
• Time consuming to find a good solution
• What mixture of detail vs. abstractness is good?
– Probably needs experience with the
• Tools
• Designs (different algorithms and architectures)
• Target technologies
– Take into account the time you spent for the project
• You need to gain experience
– Try to do more than basic requirements of the lab
• Try to iterate over your design and improve it
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Prototyping
• Try the design on FPGA/CPLD before going to ASIC
• Sometimes, even, the initial production is done with
programmable logic
• The design issues could be easily resolved
– Customer feedbacks
– In-field experience
• When more orders received, move to ASIC
• Advantageous to design from the very beginning
compatible with both programmable logic and ASIC
– Manufacturability
– Testability
– Performance, area, and other design metrics
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Other Assignments
• Manufacturing test
[deadline: 14-Mar]
The last lab lesson is scheduled on 18-Feb-2014. In case you are planning to
finish the lab very early and therefore you have doubts and questions about the
last lab assignment (that will be covered later, in the last lab lesson) please feel
free to contact the lab assistant for questions or discussions. Such cases are
handled individually.
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2nd Lab presentation
QUESTIONS ?
2014
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