% ! $ !
$ # $ ! !# " $
%" &/ +(+. #(0 ,*"( (&-1&! .5/0( !&/,(5
)+*&0+. 0 &/ !"/&$*"! 0+ " ,(1$7 +),0&(" ."7
,( ")"*0 #+. +*2"*0&+*( )+*&0+./ +* / 3+.'7
/00&+* ,(0#+.)/ &* ,,(& 0&+*/ ."-1&.&*$ (&$%0". 3"&$%0
(+3". ,+3". +. /)((". #++0,.&*0 0%* !&/,(5/ %"
1/"/ * 7&* !&$+*( 0&2" )0.&4 0%&*7
#&() 0.*/&/0+. +(+. )+!1(" 0%0 %/ ."/+(10&+* +#
5 ,&4"(/ /"" &$
+ )&*0&* +),0&&(&05 3&0% / 0%" )+*&0+.
&/ !"/&$*"! 0+ ",0 *(+$ ."! $.""* *! (1" &*,10 /&$7
*(/ 3&0% +),+/&0" /5* +* 0%" $.""* (&*" *! 0%" /)"
2&!"+ !&/,(5 0&)&*$ 1/"! #+. 0%" / +* /0*!.!
3+.'/00&+*/ 1.&*$ &),(")"*00&+* 3" #+1*! 0%0 0%"
2&((" #(0 ,*"( !&/,(5/ (( %! !&$&0( &*,10/ *!
."-1&."! (+ ' /&$*( &* " )+*&0+./ !+*0 1/"
* The red and blue signals do not have sync pulses.
(+ ' 0%" ,&4"( (+ ' #+. 0%" #(0 ,*"( !&/,(5 %! 0+ "
$"*".0"! &*0".*((5
*+0%". #"01." +# 0%" )+*&0+. &/ &0/ '(&$%0
/2". *! .",( "(" '(&$%0 //")(5 &* " 0%"&. 0.*/7
)&//&2&0&"/ ." ."(0&2"(5 (+3 +(+. / ."-1&." 2".5
.&$%0 '(&$%0 )(( .&$%0 '(&$%0/ 0"*! 0+ %2" ."(7
0&2"(5 /%+.0 +,".0&*$ (&#"0&)"/ +),."! 0+ / + )&*&7
)&6" 0%" ,.+(")/ //+ &0"! 3&0% 0%"/" /%+.0 (&#"0&)"/ 3"
%+/" ,*"( 3&0% .",( "(" '(&$%0 //")(5 +
)&*&)&6" 0%" *""! #+. .",( ")"*0 3" !"/&$*"! &. 1&0
0%0 * 1/" 0%" / .""* /2". #"01." +# 3&*!+3&*$ /+#03."
0+ !"0" 0 3%"* 0%" !&/,(5 &/ *+0 &* 1/" *! "40&*$1&/% 0%"
'(&$%0 %" / .""* /2". /%+1(! " /"0 1, 0+ !&/,(5 *
((7( ' &)$" 3%"* 0%"." &/ *+ 1/". &*,10 #+. /+)" ,".&+!
+# 0&)" + 2+&! 5 (&*$ 0%" '(&$%0 1**" "//.&(5 #+.
"4),(" 3%"* 0%" 1/". 0,/ 0%" )+1/" / /++* / 0%"
%" #(0 ,*"(
!&/,(5 )+*&0+. 3"&$%/ ( &*7
(1!&*$ 0%" /0*! *! )"/1."/
&* )) 3&!" &*
)) %&$% *! &*
)) !"",
1$1/0 "3("007 '.! +1.*(

7'6))2 7%:)6 89627 32 8,) &%'/0-+,8 320= 89627 3** %*8)6 8,)
&0%'/ -1%+) ,%7 &))2 46)7)28 *36 %&398 7)'32(7
$) -2'36436%8)( % 291&)6 3* (-%+2378-' *)%896)7 -2 8,)
" 132-836 * 23 :-()3 -7 46)7)28 36 8,) 8-1-2+ -7 -2?
'366)'8 %2( 8,) (-740%= '%2238 03'/ 3283 8,) :-()3 7-+2%0
8,) (-740%= 7,3;7 7-< ,36->328%0 '3036 &%67 %2= '31498)6
7=78)1 463&0)17 %6) ,%6( 83 (-78-2+9-7, *631 132-836 463&?
0)17 7-2') -2 )-8,)6 '%7) 8,)6) -7 238,-2+ 32 8,) (-740%=
#,) 46)7)2') 3* 8,) '3036 &%67 8)007 97)67 36 7)6:-') 4)6732?
2)0 8,%8 8,) (-740%= -7 *92'8-32%0 &98 8,%8 8,)6) -7 1378 0-/)0=
% 463&0)1 ;-8, 8,) -2498 :-()3 *631 8,) ;36/78%8-32
#,) " 132-836 ,%7 8,6)) 7 8,%8 %6) :-7-&0) *631
8,) 6)%6 3* 8,) (-740%= 2) -2(-'%8)7 ;,)8,)6 43;)6 -7 46)7?
)28 %238,)6 -2(-'%8)7 8,%8 8,) &%'/0-+,8 -7 8962)( 32 %2( 8,)
8,-6( -2(-'%8)7 8,%8 8,) (-740%= -7 4634)60= 03'/)( 32 8,)
-2498 :-()3 7-+2%0 #,) 7 '%2 &) 97)( 83 ()8)61-2)
59-'/0= ;,)8,)6 8,)6) -7 % 463&0)1 ;-8, 8,) 43;)6 79440=
8,) &%'/0-+,8 36 8,) :-()3
63:-(-2+ 8,) '%4%&-0-8= 83 409+ 8,) " -283 % 8=4-'%0
;36/78%8-32 ;-8,398 %2= 13(-*-'%8-32 83 8,) ;36/78%8-32
1)%28 8,%8 ;) ,%( 83 ()7-+2 8,) '-6'9-87 -2 8,) " 7
(-740%= -28)6*%') &3%6( 83 ,%2(0) 8,) 7%1) %2%03+ ! '31?
437-8) 7-+2%07 7)28 83 % !# (-740%= 77)28-%00= ;) ,%( 83
()7-+2 '-6'9-87 8,%8 %6) %&0) 83 8%/) %2%03+ 7-+2%07 %2( 8,)-6
%773'-%8)( 8-1-2+ %2( '32:)68 8,)1 83 (-+-8%0 7-+2%07 *36 (6-:?
-2+ '3928)67 %2( ')007 -2 %2 1%86-<
'32:)28-32%0 !# &9-0(7 %2 -1%+) &= 7;))4-2+ 32) 36
136) 13(90%8)( )0)'8632 &)%17 %'6377 8,) 4,374,367 32
8,) *%') 3* 8,) 89&) *631 0)*8 83 6-+,8 %2( 834 83 &38831 #,)
7-+2%07 8,%8 '328630 8,) 7;))4 3* 8,) &)%1 %6) 8,) ,36->328%0
%2( :)68-'%0 7=2' 7-+2%07
HSYNC
%2(
VSYNC
6)74)'8-:)0= 7))
-+ 7 8,) &)%1 7;))47 %'6377 8,) *%') 3* 8,) 89&) -8
'6)%8)7 8,) -1%+) *36 % 7-2+0) ,36->328%0 0-2) 8 8,) )2( 3*
8,) 0-2) 8,) &)%1 -7 &0%2/)( 73 8,%8 8,) 6)86%') ;328 &)
:-7-&0) %2( 8,)
HSYNC
7-+2%0 '%97)7 8,) &)%1 83 7;))4 &%'/
83 8,) 78%68 3* 8,) 2)<8 0-2) #,) *6328 436', 463:-()7 731)
8-1) *36 8,) &)%1 83 7,98 3** &)*36) 8,)
HSYNC
7-+2%0 '%97)7
8,) 6)86%') 83 &)+-2 #,) &%'/ 436', 463:-()7 731) 8-1) *36
8,) 7;))4 '-6'9-87 83 78%&-0->) &)*36) 8,) &)%1 -7 92&0%2/)(
Picture
Information
Horizontal Blanking and
Sync Signals
Vertical Blanking and
Sync Signals 15.888 s
White Level (1V)
Black Level (340 mV)
Active
Video
(Pictures)
Front
Porch
Back
Porch
Black Level (286 mV)
Sync Level (0 mV)
31437-8) %2%03+ :-()3 7-+2%07
83 78%68 8,) 2)<8 0-2) 8 8,) &38831 3* 8,) *6%1) 8,) 7%1)
8,-2+ ,%44)27 (96-2+ :)68-'%0 6)86%') 83 +)8 8,) &)%1 &%'/
83 8,) 834
#%&0) 7,3;7 8,) 8-1-2+ *36 8,) '31437-8) :-()3 7-+2%07
'31-2+ *631 %2 ;36/78%8-32 %2( +3-2+ 83 8,)
" #3 /))4 ):)6=8,-2+ 4634)60= 7=2',632->)( 8,) :)6?
8-'%0 8-1-2+ -7 %00 -2 )<%'8 -28)+)6 1908-40)7 3* 8,) ,36->328%0
0-2) 8-1) *36 8,) 232-28)60%')( 132-8367 97)( -2 ;36/?
78%8-327 36->328%0 8-1-2+ -7 -2 4-<)0 4)6-3(7 ;,-', -7 8,)
8-1) 6)59-6)( 83 7)8 94 %2( (-740%= 32) 4-<)0
)6-3( '8-:) 0%2/-2+
'8-:)
0%2/-2+ 36',)7 "=2'
6328 36',
"=2'
%'/ 36',
* ;) 8,-2/ 3* %2 %'8-:) 1%86-< %7 % &-+ ! 8,) (-7?
40%= 94(%8) 463')77 '327-787 3* ;6-8-2+ 83 %00 3* 8,) ')007 *
;) %0;%=7 94(%8) 8,) ')007 8,) 7%1) ;%= %00 3* 8,) %((6)77?
-2+ *92'8-327 '%2 &) (32) &= ,36->328%0 %2( :)68-'%0 %((6)77
6)+-78)67 -27-() 8,) (-740%= 378 7 %'')48 1908-40) 4-<)07
32 )%', '03'/ 83 /))4 8,) '03'/ 6%8)7 (3;2 "31) %'89%00=
94(%8) (-**)6)28 4%687 3* 8,) (-740%= %8 8,) 7%1) 8-1) #,)
" 7 8%/)7 8;3 '327)'98-:) 4-<)07 32 )%',
'03'/ %7 -8 7'%27 %'6377 8,) ,36->328%0 0-2)7 %2( (3;2 8,)
*6%1) *8)6 )%', '03'/ 8,) -28)62%0 ,36->328%0 %((6)77
'3928)6 -2'6)1)287 83 43-28 83 8,) 2)<8 4%-6 3* 4-<)07 8 8,)
)2( 3* 8,) 0-2) 8,)6) %6) 8;3 8,-2+7 8,%8 2))( 83 ,%44)2
8,) ,36->328%0 '3928)6 2))(7 83 &) 6)7)8 %2( 8,) :)68-'%0
'3928)6 2))(7 83 &) -2'6)1)28)( #,) 7-+2%0 8,%8 4)6*3617
8,-7 *92'8-32 -7 :)6= 7-1-0%6 83 8,) ,36->328%0 7=2' 7-+2%0 -2 %
!# 73 ;) '%00 -8
HSYNC
*8)6 8,) 0%78 0-2) %8 8,) &38831 3*
8,) *6%1) ;) 2))( 83 6)7)8 8,) :)68-'%0 %((6)77 '3928)6 83
78%68 3:)6 %8 8,) 834 3* 8,) 2)<8 *6%1) "-2') 8,) 7-+2%0 83 (3
8,-7 &),%:)7 :)6= 19', 0-/) 8,) :)68-'%0 7=2' -2 % !# ;)
'%00 -8
VSYNC
2) -14368%28 8,-2+ 83 238) %&398 8,) 8-1-2+ 3* !#7 %2(
7 -7 8,%8 8,) ,%7 19', 136) *0)<-&-0-8= #,) !#
7;))4 '-6'9-87 1978 (6-:) 8,) 0%6+) -2(9'8-:) 03%( 3* 8,)
()*0)'8-32 '3-07 73 -8 -7 238 46%'8-'%0 83 %(.978 8,) 8-1-2+ (=?
2%1-'%00= $-8,-2 0-1-87 8,) 7 8-1-2+ '%2 &) :%6-)( $)
833/ %(:%28%+) 3* 8,-7 ',%6%'8)6-78-' -2 8,) ()7-+2 3* 8,)
"00
-+ 7,3;7 % &03'/ (-%+6%1 3* 8,) 1%-2 '31432)287 3* 8,)
" *0%8 4%2)0 (-740%= 132-836 #,) %2%03+ :-()3
*631 8,) ;36/78%8-32 '31)7 -283 8,) 8)61-2%8-32 2)8;36/
;,-', 1%8',)7 8,) -14)(%2') 3* 8,) :-()3 '%&0) #,) :-()3
8,)2 +3)7 83 8,) %2%03+?83?(-+-8%0 '32:)68)67 7 #,)
(-+-8%0 398498 -7 7%140)( %2( 97)( 83 '328630 8,) 0):)0 %(.978
9+978 );0)88? %'/%6( 3962%0

75-Hz
Frame Rate
Video Input from
Workstation
Level
Adjust
ADC*
4
Frame
Buffer
66-Hz
Frame Rate
Flat Panel
Display
Sync
Clocks
Dot Clock
Regeneration
Frame
Buffer
Control
Logic
Input Video
Pixel Clock
*There is one ADC each for red, green, and blue analog signals.
Control
Flat Panel
Control
Flat Panel
Clock
",/#+ $)!'2!- /& 4(% #/-0/.%.43 ). 4(% ).4%2&!#% "/!2$
&/2 4(% &,!4 0!.%, $)30,!9 -/.)4/2
#)2#5)43 7()#( 3%4 4(% $# ,%6%, /& 4(% ).0543 !.$ 4(%
2%&%2%.#% 6/,4!'% 3/ 4(!4 4(% %.4)2% $9.!-)# 2!.'% /&
4(% 3 )3 53%$ (% 6)$%/ 39.# 3)'.!, )3 %842!#4%$ &2/-
4(% ).054 6)$%/ !.$ 3%.4 4/ 4(% $/4 #,/#+ 2%'%.%2!4)/. #)2#5)4
7()#( '%.%2!4%3 4(% #,/#+ 3)'.!,3 53%$ "9 4(% 3 4/ 3!-;
0,% 4(% 6)$%/ 3)'.!, (% $)')4!, /540543 /& 4(% 3 !2% 3%.4
4/ 4(% &2!-% "5&&%2 7()#( 39.#(2/.):%3 4(% ).054 3)'.!, 4/
4(% &,!4 0!.%, 4)-).' !.$ 3%.$3 )4 4/ 4(% 0!.%,
(% #)2#5)429 #/.6%243 4(% ).#/-).' 6)$%/ !.!,/'
342%!- ).4/ 4(% $)')4!, $!4! 4(!4 4(% &,!4 0!.%, $)30,!9 #!.
!##%04 . 4(% #!3% /& 4(% -/.)4/2 0)8%,33
!2% #/.6%24%$ 3/ 4(!4 4(% &/52 -/34;3)'.)&)#!.4 ")43 /& %!#(
#/,/23 $)')4!, 2%02%3%.4!4)/. $/ ./4 6!29 &2/- /.% &2!-% 4/
4(% .%84 "%#!53% /& $)')4!, ./)3% .% /& 4(%3% &/52 ")43 )3
53%$ &/2 #/.42/, !.$ 4(% /4(%2 4(2%% ")43 $%&).% 4(% 4(2%%;")4
#/,/2 4(!4 4(% &,!4 0!.%, 53%3 4/ '%.%2!4% %)'(4 ).4%.3)49 ,%6;
%,3 &/2 2%$ '2%%. !.$ ",5% 02/6)$).' ! 4/4!, /& $)30,!9;
!",% #/,/23 (% /.%;6/,4 37).' /& 4(% ).054 !.!,/' 6)$%/ )3
$)6)$%$ ).4/ 4(2%% -!). 2%')/.3 4(% 39.# ,%6%, 4(% ",!.+
,%6%, 490)#!,,9 - !"/6% 4(% 39.# 6/,4!'% !.$ 4(%
6)$%/ ,%6%, 2!.'%3 &2/- - !"/6% ",!.+ 3)'.)&9).' ",!#+
4/ - !"/6% ",!.+ 3)'.)&9).' 7()4% (%3% 6/,4!'% ,%6;
%,3 !2% 3(/7. ). )' (% 0%2)/$ /& 4(% 39.# 3)'.!, /. 4(%
!.!,/' ).054 )3 4(% 4)-% 2%15)2%$ 4/ 02/6)$% $!4! &/2 /.%
(/2):/.4!, ,).% /& 0)8%,3 . 4(% -/.)4/2 4()3
4)-% )3 3
)' 3(/73 4(!4 4(% #)2#5)429 )3 #,%!.,9 $)6)$%$ "%;
47%%. 4(% $/4 #,/#+ 2%'%.%2!4)/. #)2#5)4 !.$ 4(% 3500/24
#)2#5)429 &/2 4(% (% $/4 #,/#+ 2%'%.%2!4)/. #)2#5)4 53%3
4(% (/2):/.4!, 39.# 3)'.!, &2/- 4(% '2%%. !.!,/' ).054 ,).%
4/ #2%!4% ! #,/#+ 7()#( )3 53%$ "9 4(% 4/ 3!-0,% 4(%
!.!,/' 6)$%/ 3)'.!, (% 3500/24 #)2#5)4 )3 02)-!2),9
#/.#%2.%$ 7)4( #/.42/,,).' 4(% /&&3%4 /& 4(% ).054 !.!,/'
3)'.!, !.$ 4(% 2%&%2%.#% 6/,4!'% 4/ %.352% 4(!4 4(% /54;
0543 (!6% 4(% $%3)2%$ $)')4!, 2!.'%
Liquid crystal displays, or LCDs, are divided into two main classes: active and passive matrix LCDs. Passive matrix displays scan each of the cells, or pixels, sequentially. They are less complex and less expensive than active matrix devices, but the addressing technique they use means that each cell is only driven for a small fraction of the time. To maintain the image, the cells must hold their state for a long time (analogous to long decay phosphors in a slow-scan CRT).
The disadvantage is that the response time of the display is slowed, which leads to ghosting on rapidly changing images, such as when the cursor is moved.
Active matrix displays have circuitry associated with each cell. The usual technique for building active matrix LCD circuits is to use a thin film of silicon grown on the display glass. This technique is known as thin-film transistor, or TFT. This type of LCD can be thought of as a big dynamic RAM, with one cell for each pixel. The
RAM drives each liquid crystal cell continuously, and the RAM cells are refreshed by scanning the display. This enables the liquid crystal cell to be faster, improving response time dramatically. It also allows the display to have much higher resolution, since the drive time of each cell is not reduced by adding more cells. The increased resolution makes it more practical to build a color display since a color display has at least three times as many effective pixels as a monochrome display
(one red, one green, and one blue subpixel for each pixel).
LCDs offer a number of advantages over CRTs. Because they are fabricated with a lithographic process, they offer excellent linearity, convergence, and purity. LCDs have no electron beam, making them unsusceptible to magnetic fields. They have lower power requirements (about 55W versus 100W for a comparable-size CRT).
Because conventional CRTs need to deflect an electron beam, they must have a greater depth, and thus a larger footprint, than an LCD monitor. CRTs need to accelerate the electron beam, which requires high voltages that are not necessary for LCD monitors. S ide effects of the high voltages include x-ray emissions and potential electrostatic problems in some environments. Finally, LCD monitors don’t need a heavy glass bottle to maintain a vacuum, so they weigh much less than
CRTs.
/ #2%!4% ! 0,%!3).' 6)35!, )-!'% 7)4(/54 0)8%,3 *)44%2).'
!2/5.$ )4 )3 #2)4)#!, 4/ 0/3)4)/. 4(% 3!-0,).' #,/#+ %$'%3
02%#)3%,9 !.$ 2%0%!4!",9 & ! 0)8%, )3 3!-0,%$ !4 (/2):/.4!,
0/3)4)/. 8 ). /.% &2!-% "54 !4 0/3)4)/. 8 ). 4(% .%84
&2!-% 4(% 53%2 7),, %!3),9 3%% 4(% $)&&%2%.#% !3 ./)3% /. 4(%
-/.)4/2 524(%2-/2% 4(% 3!-0,% -534 "% 4!+%. 7(%. 4(%
3)'.!, )3 34!",% !.$ ./4 42!.3)4)/.).' "%47%%. 0)8%,3 ()3
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4(!. ! 3).',% 0)8%, 4)-% (% )3 !",% 4/ 2%#/6%2
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).054 &2/- /.% ,%6%, 4/ 4(% .%84 )3 .3 7/234 #!3% ,%!6).'
/.,9 .3 &/2 3%450 !.$ 5.#%24!).4)%3 /6%2 !,, 4%-0%2!452%
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5'534 %7,%44;!#+!2$ /52.!,

Dot Clock Regeneration Circuit
Analog
Video
Controllable
Current
Source
+5V
Line Receivers
ECL
IN
IN
ECL
IN
IN
V
BB
D
ECL
Q
Q
ECL
IN
IN
PLL_HSYNC
Delay Line
D
ECL
Q
Q
Phase-Locked Loop
Phase
Detector
R U
Loop
Filter
V
ECL
D
VCO
Voltage
Voltage-
Controlled
Oscillator
ECL42base
ECL
+5V
1 D
ECL
Q
R Q
ECL_nCSYNC
+5V
CLK42rgb nCLK42rgb
ECL-to-
TTL
+5V
CNTCLK42
HSYNC
Five Most-
Significant Bits
10-Bit
Counter
ADC Support Circuit
Controllable
Current
Source
Level
Adjust
Feedback
Path
Controllable
Voltage
Reference
Ain
VREF+
VREF–
Sync_ctl PAL
GRN Level Adjust
VREF + Adjust
8 Bits
8 Bits
Digital Color Data
Buffered and Loaded into Frame Buffer
To Other
Half of ADC
&# ,*-%71-7"'%'1* !-,3#/0'-, !'/!2'1/6 ', 1&# ',1#/$!# -/"
)#4 !, # ',1/-"2!#" ', 1&# 1&/## +(-/ /#0 06,! 0#.7
/1'-, #51/!1',% 1&# 06,! 0'%,* $/-+ 1&# ,*-% ',.21 1- #
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!-,1/-* #14##, 1&# #"%# -$ 1&# ',1#/,* 06,! 0'%,* ," 1&#
!*-!) 0#,1 1- 1&# $-/ 0+.*',% 1&# "1 ," .&0#
*-!)',% "#%/## 1- 4&'!& 1&# ',1#/,* 06,! 0'%,* !, #
+1!&#" 4'1& 1&# ,*-% ',.21 06,! 0'%,*
'% 0&-40 &-4 1&# 0'%,*0 20#" ', 1&# +-,'1-/
*',# 2. *1'+1#*6 4# /# 1/6',% 1- %#1 1&# /'0',% #"%#0 -$
CLK42rgb
," nCLK42rgb
1- # ./#!'0#*6 .-0'1'-,#" 4'1& /#0.#!1
1- 1&# ,*-% ',.21 &'0 '0 #!20# 1&#0# 0'%,*0 /# 20#" 1-
!*-!) 1&# 1&1 ./-"2!#0 1&# "'%'1* .'5#* "1
&#
ECL_nCSYNC
0'%,* '0 %#,#/1#" $/-+ 1&# ,*-% 3'"#-
0'%,* $1#/ 1&# ,*-% 3'"#- 0'%,* &0 ##, 1#/+',1#" ,"
3-*1%# 0&'$1#" 1&/-2%& 6.00 !.!'1-/0 #./1',% 1&#
06,! 0'%,* $/-+ 1&# ,*-% 3'"#- 0'%,* '0 10) 1&1 **
"'0.*6 +-,'1-/0 +201 "- ," 1&#/# /# +,6 ./10 !-++#/7
!'**6 3'* *# $-/ 1&'0 .2/.-0# -4#3#/ ,-,# -$ 1&#0#
./10 4#/# !!#.1 *# $-/ 20# ', 1&# +-,'1-/ #7
!20# -$ 1&# %/#1 2,!#/1',16 -21 1&# ./-.%1'-, "#*6 -$
1&#0# ./10 &#/#$-/# 4# 20#" !/#$2**6 '0#" "'$$#/7
#,1'* *',# /#!#'3#/ //,%#" ', !&+'1171/'%%#/
!-,$'%2/1'-, &# '0 0#,0'1'3# #,-2%& 1- "'01',7
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CLK42rgb nCLK42rgb
CNTCLK42
HSYNC
PLL_HSYNC (ECL)
Blank Level
Analog Input
Sync Level
ECL_nCSYNC
23.64 ns
Signal
The phase-locked loop locks the rising edges of PLL_HSYNC and ECL_nCSYNC .
Source or Purpose
ECL42base
CLK42rgb nCLK42rgb
CNTCLK42
Output of the Voltage-Controlled Oscillator
TTL Clock Used by the ADC to Sample Data
Inverse of CLK42rgb also Used to Sample Data
Clock Used to Count Pixels
Regenerated Horizontal Sync from Pixel Counts HSYNC
(TTL Version)
PLL_HSYNC ECL Version of HSYNC , Precisely Linked with nCLK42rgb for Locking onto the Input Sync
ECL_nCSYNC Input Composite Sync Used for Locking to Internally
Generated HSYNC
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0
Pixel n
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7
Random Port
Data from ADCs
8
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Red
(Two
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Green
(Two
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(Two
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Serial Port Data to LCD
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(continued on page 58)
:,:89 *<1*99@ &(0&7) 4:73&1

Simplicity and elegance were the two main underlying objectives for the product design of HP’s first standalone flat panel display monitor. Because of the high cost and resolution of the display technology, the product design needed to radiate innovation and quality. The use of many subtle curves gave the product a very soft and sophisticated look and feel.
Other mechanical objectives were to design a small-footprint, yet stable package with a wide tilt range and swivel, require no fan, be desktop or wall mountable, and have built-in security and cable management features.
adjustment mechanisms would have taken more time and resources and potentially resulted in a bulkier design. For simplicity, a fixed height with a wider tilt range was decided upon that would meet most users’ needs. As for swivel, the simple answer was: just slide it around. With the appropriate feet material, the monitor is light enough to be easily swiveled and slid anywhere on the desk. For thermal, size, and simplicity reasons, it was decided not to incorporate the power supply and instead use an external power module (off the desk, out of sight).
Simplicity
The design is made up of two assemblies: the chassis/display assembly which houses the display module and control electronics, and the stand assembly which provides structure and dynamic movements (see Fig. 1). The stand has no electronics and is detachable. The overall structure is C-shaped which helped to reduce the footprint by balancing the display over the stand and provided a wider tilt range (Fig. 2). It also gave it an elegant, floating display look. An added benefit to the C shape is that a keyboard can fit under the display portion to free up even more desk space.
Because of the schedule and available engineering resources, simplicity was taken seriously. A human factors study was completed giving the desired height, tilt, and swivel ranges. However, designing individual height, tilt, and swivel
Chassis/Display Assembly
This chassis/display assembly shown in Fig. 1a consists of the LCD module, the interface printed circuit board, the power and brightness switch board, an aluminum chassis, a protective and conductive glass over the display, and cosmetic plastic covers. An aluminum chassis (as opposed to steel) was chosen to reduce weight and for EMI containment. The chassis contains a stainless-steel gasket to provide EMI contacts around the video and power connectors. A steel bracket is attached to the rear to provide a more rigid mounting location for the hinge and stand assembly. The plastic middle and back covers are heatstaked to the metal chassis. The printed circuit boards are snapped and then screwed into place. A protective glass, which is conductive and provides EMI containment, is taped to the display module metal housing. The display module is connected via cables to the control board and then screwed to the chassis. The plastic front cover hooks at the top on the middle cover and is then screwed underneath into the chassis. The
Plastic
Front
Cover Protective EMI
Glass Shield
LCD Module
Interface
Printed
Circuit
Board
Aluminum
Chassis
Plastic Middle
Cover
Plastic Back
Cover
Switch Printed
Circuit Board
(a)
Plastic Hinge
Covers
Steel Friction
Hinge
(b)
Plastic
Front Cover
Steel Stand
Plastic
Back
Cover
Steel
Security
Loop
Plastic Feet
Fig. 1. The two assemblies that make up the product design for the HP S1010A flat panel display. (a) The chassis/display assembly. (b)The stand assembly.

Final Assembly
The stand assembly is mounted to the display assembly via two screws. To expose the mounting holes, the back stand cover is snapped off and the hinge shaft is aligned with the chassis mounting bracket and secured with two screws. Fig. 3 shows different views of the final assembly of the display.
Conclusion
As a testimony to our adherence to the original design goals of simplicity and elegance, the product has won two major design awards: Design Zentrum Red Dot for High Design Quality (Germany 1994) and The Industrial Design Excellence
Award-Gold 1994 (United States), featured in the June 6, 1994 issue of Business
Week.
(a)
Fig. 2. The tilt range of the flat panel display.
(b) assembly weighs approximately 6 lb (2.7 kg) with the LCD module weighing approximately 3 lb (1.4 kg).
The Stand Assembly
To provide a stable base for the display assembly, the stand was designed out of heavy sheet steel with a counterbalancing shape (Fig. 1b). The stand assembly includes a custom steel friction hinge, a stainless-steel security loop, and cosmetic plastic covers. The security loop snaps into the metal stand. The plastic front cover is heatstaked to the metal stand. The plastic hinge covers are screwed to the hinge shaft. The hinge assembly is screwed to the stand. The plastic back cover, which incorporates a cable management recess, is hooked at the bottom into the front cover and rotates and snaps at the top into the front cover.
Fig. 3. Different views of the HP S1010A flat panel display.
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Horizontal
Sync qsf
A
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B
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≠
8
Video RAMs, or VRAMs, are a variety of two-port dynamic RAM. They are designed to work well in graphics and video applications. The main port allows random access to any cell of the RAM. The other port consists of shift registers that are controlled by an independent clock. In the HP S1010A, the random port runs in the video input clock domain, and the serial port runs in the flat panel clock domain.
A data transfer operation loads the shift registers with data from the RAM array.
The shift registers can be treated as two semi-independent halves, so that one half can be loaded without interfering with the data being shifted out of the other half.
This provides more flexibility, since a data transfer operation (called a split data transfer in this case) can happen at any time while the other half is active, and transfers can be arranged so that there will be no interruption in the data flow out of the shift registers. The VRAM provides a signal called qsf to indicate which half of the shift register is active. When the data in the active half of the shift register is exhausted, qsf toggles, and the other half becomes active. This signals the HP
S1010A’s control logic that it’s time to get ready for another split data transfer.
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