International Journal of Engineering Trends and Technology (IJETT) – Volume 14 Number 6 – Aug 2014
Student, Department of Electronics and Communication, Sree Buddha College of Engineering, University of Kerala,
Kerala, India
Abstract
In this paper design and implementation of a graphics controller, which can support multiple resolutions is presented. It receives data to be displayed on the screen either from some external sources or an internal program and drives RGB and control signals onto the screen. It can display text as well as graphics on the screen. We have included a useful software library to enable text mode. This controller can be reconfigured according to the requirements of the target application. It is based on FPGA hence the end use of this controller is in embedded systems and FPGA based computers. Here we have integrated our controller with some other modules (UART, PS/2 interface and Memory Controller) for demonstration. The architecture is coded in VHDL, simulated in Xilinx ISE 13.2 and implemented on Spartan 3 board.
Keywords— Graphics controller, FPGA
I.
I NTRODUCTION
VGA (Video Graphics Array)[1] is used as an interfacing standard in many embedded systems. It is used to interface a system with a monitor to display data. Users can interact with the system through monitor. VGA is an analog display standard. Most of the current PCs support some higher resolution standards along with VGA standard. Different systems need different display quality. industrial production machines of today must be highly flexible in order to competitively account for dynamic and unforeseen changes in the product demand. FPGAs are very powerful, relatively inexpensive and adaptable. Hence we can say that Fieldprogrammable gate arrays meet requirements of targeted applications. Thus, a graphics controller, which is a logic circuit to control the monitor interface, can be easily realized by FPGA technology with low cost and high flexibility.
A graphics controller is a circuit which generates the output images to be fed into a display. Graphics controller is also known a Graphics Coprocessor[2]. There are two kinds of interface signals to display. One is data signal, and the other is control signal. The three data signals are red, green and blue and two control signals are horizontal synchronization and vertical synchronization signals. There are different frequencies of the horizontal and vertical synchronization signal for the changeable output resolution. The graphics controller processes the received data and output the data along with control signals onto the screen[3]. I have developed an efficient architecture for a multi resolution graphics controller, which is suitable for commercial, industrial and specialist display system applications. FPGA’s parallel computation is utilized in this paper. Where timing signals for various screen resolutions can be synced using a single clock and display data are loaded simultaneously. It is capable of displaying data under resolutions ranging from
QVGA to HD. This system can work in two modes, graphics mode and text mode. Here we have integrated our controller into a system with some other modules for demonstration.
This system consists of UART Module, PS/2 Module,
Memory Controller Module and Monitor Controller Unit. The system can display text, animated object and images on the monitor. In this design, the memory used is the internal Block
RAM of Xilinx FPGA. It is a static RAM. An external static ram or SD RAM can also be used. It will require additional memory interfacing circuits. A Memory Controller is used for accessing data from memory. UART is an integrated circuit which plays a key role in serial communication. It handles the conversion between serial and parallel data. In actual applications, only a few key features of UART are needed.
Specific interface chip will cause waste of resources and increased cost. So we have integrated a UART module in our system. The keyboard has always been the most favourite device for data input to a system. Hence a PS/2 keyboard interface is also included in our system. We can use this proposed system for different applications by simple program level reconfiguration. Whole design has been synthesized and implemented on a Xilinx Spartan-3 FPGA using Xilinx ISE
Design Suit 13.2. Here Hardware Description Language used is VHDL. Since VGA port in Spartan-3 board supports 8-bit output, we can use DAC to increase output colour depth.
A.
Basic Ideas
II.
A RCHITECTURE D ESIGN
Fig.1 Screen of a PC monitor
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International Journal of Engineering Trends and Technology (IJETT) – Volume 14 Number 6 – Aug 2014
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VGA (video graphics array) is a video display standard introduced in the 1980s in IBM PCs and is widely supported by PC graphics hardware and monitors. VGA system can be given as a combination of five signals which is required to show an image on screen. These signals are Horizontal synchronization signal, Vertical synchronization signal and the three colour signals Red, Green and Blue respectively. The screen of a PC monitor usually includes a small black border and a middle rectangle visible portion as shown in Fig.1.
 Display: Region where the pixels are actually displayed on the screen.
 Right border: Region that forms the right border of the display region. It is also known as the front porch
(i.e., porch before retrace). The video signal should be disabled in this region.
 Left border: Region that forms the left border of the display region. It is also known as the back porch
(i.e., porch after retrace). The video signal should be disabled.
 Bottom border: Region that forms the bottom border of the display region. It is also known as the front porch (i.e., porch before retrace). The video signal should be disabled in this region.
 Top border: Region that forms the top border of the display region. It is also known as the back porch
(i.e., porch after retrace). The video signal should be disabled in this region.
The timing signals have utmost importance in a VGA system. If the timing signals are not meeting the timing constraints, then most displays will enter sleep mode or will turn off. Hence a graphics controller has to meet the required timing specifications correctly. There are separate fixed timing specifications for each display standards. So a Multi resolution graphics controller has to satisfy all these timing constraints. The pixel rate (clock frequencies) of each resolution standard can be calculated using three parameters p, l and s .
Pixel rate = p*l*s
Where, p is the number of pixels in a horizontal scans line, l is the number of lines in a screen and s is the number of screens per second. Table I shows clock frequencies required for some resolutions.
TABLE I
C LOCK F REQUENCIES OF R ESOLUTIONS
Resolution
640X480
320X240
800X600
1024X768
1440X900
1280X720
1980X1200
Clock Frequency (MHz)
25.175
62.4
40
65
85
74.16
154.12
B.
Multi resolution graphics controller architecture
Fig. 2 Graphics controller block diagram
A simplified block diagram of a Multi Resolution
Graphics Controller is shown in Fig.2. It contains a control circuit, a pixel generation circuit, a DCM and a FIFO module.
Here in this design, we have used only the memory resources available on Spartan 3 FPGA board. But if the size of an image is larger than memory resources available on FPGA devices, the image cannot be stored totally inside the design of graphics controller. It should be held on an off-chip memory
(e.g. SRAM) and transferred into this controller unit by small data blocks during the display time. For that reason, most of graphics controllers have an internal FIFO memory to temporarily store these data blocks. To select a required FIFO, we have to consider some factors, including pixel clock, operating system clock, data bus width, and the bus occupation of the system which contains controller unit. A
FIFO (first-in-first-out) buffer is an elastic storage between two subsystems. It has two control signals, wr and rd, for write and read operations. When wr is asserted, the input data is written into the buffer. The rd signal actually acts like a remove signal. When it is asserted, the first item of the FIFO buffer is removed and the next item becomes available. The
FIFO buffer provides more buffering space and further reduces the chance of data overrun. The desired number of words in FIFO to accommodate the processing need of the main system can be adjusted.
The read and write of FIFO is controlled by Controller module. In addition to this, Control circuit generates the synchronization signals and some other control signals.
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International Journal of Engineering Trends and Technology (IJETT) – Volume 14 Number 6 – Aug 2014
Synchronisation (timing) signals include horizontal and vertical synchronisation signals. These signals are connected to the monitor to control the horizontal and vertical scans of the monitor. The Controller module essentially specifies the current scan location and also generates the video_on signal to indicate whether to enable or disable the display. Address to access memory is calculated by this controller module.
Composition of Controller module is shown in Fig. 3, which consists of FIFO Read/Write Controller, Pixel Generator
Controller and Timing Signals Generator. These modules are controller by a finite state machine (FSM). generate objects on the screen. This method is known as object mapped scheme.
Fig.4 Representation of character ‘A’
Representation of character A in ROM is given in
Fig.4.Tile-mapped pixel generation scheme can be used for displaying text[8][10]. For the text display, we use the 7-bit
ASCII code for the character tiles. The patterns of the tiles constitute the font of the character set. The character patterns are stored in a ROM. The pattern memory is known as font
ROM.
C.
FPGA based system for demonstration
Here, I have implemented an FPGA based system to demonstrate the working of the proposed controller. An FPGA based system using Multi Resolution Graphics Controller
(labelled as VGA unit) is given in Fig.5.
Fig.1 Composition of controller module.
The pixel generation circuit generates the three video signals, which are collectively referred to as the rgb signal. A colour value is obtained according to the current coordinates of the pixel (the pixel_x and pixel_y signals) and the external control and data signals. If we are using an external memory to store data, then pixel generation module can act as a data aligner which aligns data between the output of the FIFO module and the input of the VGA Interface module. Pixel generation module can generate pixel values by object mapped scheme or tile mapped scheme or bit mapped scheme.
In a bit mapped scheme, a video memory is used to store the data to be displayed on the screen. Each pixel of the screen is mapped directly to a memory word, and the pixel_x and pixel_y signals form the address. A graphics processing circuit continuously updates the screen and writes relevant data to the video memory. A retrieval circuit continuously reads the video memory and routes the data to the rgb signal.
We can use a tile mapped scheme to reduce memory requirements. In this scheme, we can group a collection of bits to form a tile and use each tile as a display unit. In some applications we can use simple object generation circuits to
Fig.5 FPGA based system.
It is composed of a memory controller unit, to interface with an external memory; PS/2 unit to interface with a PS/2 keyboard; VGA unit to interface with monitor and UART unit for serial communication. The system uses a channel of
PLBv4.6 bus to interconnect these components.
The UART[12] terminal receives input from the UART port and displays the received characters on a monitor. The
UART core consists of 3 main modules transmitter, receiver and baud rate generator. The UART transmitter module converts the bytes into serial bits according to the basic frame format and transmits those bits. The UART receiver module is
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International Journal of Engineering Trends and Technology (IJETT) – Volume 14 Number 6 – Aug 2014 used to receive the serial signals and convert them into parallel data. Baud rate is the rate at which data is transmitted.
Fig.6
shows the block diagram of complete UART. UART receiver obtains the data word via oversampling. Baud rate generator is designed as a mod-m counter, which counts from
0 to m-1 and wraps around. Interfacing circuit is used to provide buffer and status between the UART receiver and the system that uses the UART. FIFO can be used as interfacing circuit.
Fig.7 Conceptual diagram of PS/2 receiver
If we want to display images, we need some memory to store it. Random Access Memory (RAM) is used for massive storage in a digital system since a RAM cell is much simpler than an FF cell[13]. A commonly used type of RAM is the asynchronous static RAM (SRAM). data from an asynchronous SRAM is more complicated, hence we need a memory controller module for that. Block diagram of memory controller is shown in Fig.8.
Its data path contains one address register, which stores the address, and two data registers, which store the data from each direction. Since the data bus, dio, is a bidirectional signal, a tri-state buffer is needed. The control path is an FSM, which follows some timing specifications.
Fig.6 Complete UART bock diagram
PS/2 keyboard interface[11] is used to connect a keyboard with our system. The communication of the PS/2 port is bidirectional and the host can send a command to the keyboard or mouse to set certain parameters. For our purposes, the bidirectional communication is hardly required and thus our discussion is limited to one direction, from the keyboard to the prototyping board. The design of the PS/2 port receiving subsystem is somewhat similar to that of a
UART receiver. The subsystem includes a falling edge detection circuit, which generates a one-clock-cycle tick at the falling edge of the keyboard clock signal, and the receiver, which shifts in and assembles the serial bits.
Fig. 7 shows conceptual top-level diagram of PS/2 receiver. The basic idea is to use the FSM to keep track of the
F0 packet of the break code. After it is received, the next packet should be the make code of this key and is written into the FIFO buffer.
Fig.8 Memory controller block diagram
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International Journal of Engineering Trends and Technology (IJETT) – Volume 14 Number 6 – Aug 2014
III.
R ESULTS AND D ISCUSSION
Simulation result of the controller for WXGA resolution is given in Fig.9.
Fig.9 Simulation result for WXGA resolution
Hardware results of Multi resolution graphics controller for text and graphics mode is shown in Fig.10, Fig.11, Fig.12.
Fig.11 Test output – graphics mode (animated objects)
Fig.10 Test output – text mode
Fig.12 Test output – graphics mode (image)
Table II shows comparison of supported display standards and bus technologies of different designs.
TABLE III
COMPARISON OF SUPPORTED DISPLAY STANDARDS AND BUS TECHNOLOGY (Y: YES, N: NO)
Design
CAST[4]
Oc_vga[7]
Xl_tft[6]
Van[2]
Proposed
IV.
C
Display Standards Bus Technology
QVGA VGA SVGA XGA WXGA+ HD FHD PLB AHB WISHBONE
Y
Y
Y
Y
Y
Y
Y
N
Y
N
Y
N
Y
N
Y
Y
N
Y
Y
Y
N
Y
N
Y
N
N
N
N
N
N
Y
Y
Y Y Y Y Y Y N Y
ONCLUSIONS
In conclusion, I have presented design of hardware architecture for a multi resolution graphics controller which has high potential to be used in FPGA-based systems. This controller can support QVGA, VGA, SVGA, XGA,
WXGA, WXGA+ and HD resolutions. It can work in two modes, graphics mode and text mode. The highlighted features such as multiple display resolutions supporting capability, customizable internal FIFO memory, independence to system clock and pixel clock etc., makes this system suitable for FPGAs and able to meet different requirements of targeted applications. Timing constraints of each resolution are met as per requirement. In addition, a
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International Journal of Engineering Trends and Technology (IJETT) – Volume 14 Number 6 – Aug 2014 software library to enable text mode is also introduced. In order to demonstrate working of this controller a system is developed which includes UART, PS/2 and a memory controller module. Thus, FPGA-based graphics controller is a good choice as it is easy to be designed and tiny.
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