International Journal of Engineering Trends and Technology (IJETT) – Volume 11 Number 9 - May 2014
A High-Precision Wide Range On-Chip Path Delay
Measurement
Neelufar Naheed Saudagar#1, Seema Deshmukh*2
#
PG Student, VLSI Design And Embedded Systems, Dept. Of PG Studies, VTU, Gulbarga, India.
*
Assistant Professor, Dept. OF E and CE, PDA College Of Engineering, Gulbarga, India.
Abstract— On- chip delay measurement is one of the important
procedures while the testing of the integrated circuits(IC) circuits
is taken into consideration. Occurrence of the on chip delay is
due to some defect in the IC at electrical level. Due to that defect
there will be a delay in the movement of the signal to the
destination. In order to improve the quality of shippable
products, there is an urgent need to conduct effective delay
testing for ascertaining the operation of chips at the rated
frequency. In this paper, we present a on-chip path delay
measurement architecture for efficiently detecting and
debugging of delay faults in the fabricated integrated circuits. In
the proposed on-chip path delay measurement(OCDM) circuit,
several delay stages are employed, whose delay range is increased
by a factor of two from the last to first delay stage. A calibration
circuit is included to calibrate the delay range of the delay stage.
Xilinx ISE based implementation was carried out. Simulation
results shows precise measurement of path delays.
Keywords— calibration, delay measurement, delay range, vernier
delay line(VDL).
I.
INTRODUCTION
Scaling improves the performance of modern VLSI chips
considerably. We have seen operating frequencies are
reaching multi-gigahertz for integrated circuits, resulting in
more rigorous timing requirements [1]. Timing related defects
originated from manufacturing process-related problems, such
as resistive opens and shorts, metal mouse bites, via voids,
etc., will become more common [2]. Consequently, delay
faults caused by these physical defects, which prevent the
circuit from meeting the timing requirements, are of growing
concern in nanometer technologies [3]. As a result, the delay
of gates and timing-critical paths will have large variations
and can hardly be predicted during the design stage due to the
imprecision of verification models [4]. Furthermore, the
circuit timing would also be impacted by the application
environment conditions such as temperature, supply voltage
noise, etc. In order to improve the quality of shippable
products, there is an urgent need to conduct effective delay
testing for ascertaining the correct operation of chips at the
rated frequency [5].
Traditionally at-speed delay testing was carried out to
check the satisfiability of the circuit timing by considering
whether the circuit under test(CUT) passes delay testing under
the applied test vector pairs or not. However with this the
small delay defect(SDD), which introduces small extra delay
over its normal value may not be detected due to observability
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limitation for large timing slack. However detection of SDD is
very important to ensure the chip’s quality and reliability. In
addition to imperative requirement of SDD detection it is also
necessary to identify and rectify design related failures and
performance limiters as early as possible during first silicon
debug. However its very expensive to use external high speed
automatic test equipment(ATE) for post silicon debug for
modern high performance chips.
Several on-chip architectures have already been proposed
for delay testing and silicon debug in literatures. An on-chip
timing characterization scheme based on skewed inverter
delay line is proposed by Datta et al[6], where pulse is first
generated by the triggered transitions of the start and end
points of path under measurement(PUM) using test vector,
and then the width of pulse is recorded using pulse shaping
technique. Another technique for path delay measurement was
proposed by Datta et al[7] based on modified VDL, a highresolution capability for delay measurement is provided using
a balanced delay line. Using the same principle of VDL Tsai
et al.[8] proposed a built-in delay measurement circuit
consisting of coarse and fine blocks, which is an extension of
modified VDL technique.
Although VDL based techniques can provide high delay
measurement resolution, it need lots of stages to achieve a
large measurement range, thus the whole delay measurement
process is time consuming.
The on-chip path delay measurement techniques have been
gained many attentions for researchers in recent years, for it
can provide a cost-effective alternative way to perform delay
defect detection and silicon debug in modern VLSI chips[9].
Rather than testing the chip with all possible worst-case test
vectors and process corners, it is better to measure the delays
of paths and to check if the slacks are large enough to tolerate
all the possible delay variations. A novel on-chip path delay
measurement technique based on timing characterization and
silicon debug is proposed in[10],[11] with six delay stages.
In this paper we present an OCDM circuit, with seven delay
stages in which the delay range of delay stages are increased
by a factor of two from the last to first stage. The time
difference of two input signals in the next stage depends on
the stored value of the current delay stage.
II. OCDM BLOCK DIAGRAM
In this section, OCDM circuit design has been presented for
path delay measurement and silicon debug. Fig. 1. Shows the
proposed OCDM circuit design, which converts the delay of
path under measurement into series of digital values that can
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International Journal of Engineering Trends and Technology (IJETT) – Volume 11 Number 9 - May 2014
be stored flip-flops of the VDL chain. Here, inputs x is fed by
the output of PUM while, input y is fed by the input of PUM.
So y always switches earlier than x does during delay
measurement period. All flip flops of the OCDM are
initialized to logic ZERO values by asserting the reset signal.
Delay measurement mode is activated by asserting the mode
signal. The values stored in the delay line are shifted out
serially using the clock signal shiftclk in the shift mode by deasserting the mode signal. The delay of PUM can be obtained.
Fig. 1 Proposed OCDM block diagram.
A. Delay Stage
Each delay stage consisted in the VDL chain is constructed
by a positive edge triggered D-type flip-flop, four
multiplexers and several buffers. Fig. 2 Shows the structure of
delay stage.
stage to first stage of the OCDM circuit, the delay range of
each stage is increased by a factor of two.
The delay of BUF B is designed large enough to make sure
that a stable logic value can be stored in the flip-flop before the
two transition signals arrive at the inputs of multiplexers whose
outputs are connected to the inputs of the next delay stage. The
delay value of the buffer named BUF A in each delay stage is
larger than the collective delay of the path that contains LDU
and BUF B of the same delay stage.
The principle of OCDM is, that a logic ONE will be stored
in the flip-flop of delay stage, if the time difference between
the two inputs of each delay stage is larger than the delay range
of the same stage. The time difference between the output
signals is reduced by an amount which is equal to the delay
range of the same delay stage. Otherwise, the flip-flop of the
delay stage will hold a logic ZERO value, and the time
difference between the output signals will remain the same as
that between the input signals of the delay stage. There exist a
set up time in D flip-flop of each delay stage.
B. Calibration Circuit
Before using the OCDM circuit, to assure the precision of
the result of path delay measurement it is necessary to
calibrate the delay ranges. Fig. 3 shows the basic structure of
calibration circuit.
Fig. 3 Calibration circuit.
Fig. 2 Structure of delay stage
.
There are two delay units one is upper delay unit(UDU) and
other is lower delay unit(LDU.)The UDU refers to buffer chain
which starts at the input of the delay stage and ends at the input
if the multiplexer whose output is connected to data input of
the flip-flop in each delay stage. The LDU is similar UDU,
except it starts at the input of the delay stage and ends at the
input of another multiplexer whose output is connected to the
clock input of the flip-flop in each delay stage.
Delay range is defined as the delay difference between the
two delay units in each stage of the OCDM circuit. The delay
of UDU is designed larger than that of the LDU. From the last
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The output of the calibration circuit is directly connected to
inputs of the OCDM circuit. Pin and Pout are input and output
of PUM respectively. When CS is set to 1, generated
transitions at Pin and Pout are sent to the OCDM circuit for
delay measurement. When CS is set to 0, the delay range
calibration process is conducted. The simplified timing
diagram for calibration circuit is shown in fig. 4. The FF1 is
positive edge triggered whereas FF2 is negative edge triggered.
Both the flip-flops are initialized to logic ZERO state by
asserting the reset signal. The time difference between y and x
is equal to the width of the positive half cycle of the clock
period.
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International Journal of Engineering Trends and Technology (IJETT) – Volume 11 Number 9 - May 2014
Fig. 6 TC.
Fig. 4 Timing diagram for calibration circuit.
III.
PATH DELAY MEASUREMENT ARCHITECTURE
Fig. 5 shows the architecture for proposed path delay
measurement scheme using OCDM circuit. Timing critical
paths that have delay exceeding specified timing threshold
under static timing analysis are the ones that are selected for
delay measurement. The main focus in this paper is on the
design of path delay measurement architecture. To select the
particular path into the OCDM circuit for delay measurement
we include two M-to-1 multiplexers.
Fig. 7 Simplified timing diagram for TC.
B. Path Delay Measurement
The proposed on-chip delay measurement can be divided
into following steps:
 Select the path for delay measurement using the mux;
 For the selected PUM the first vector of the test vector
pair is applied to initialize the internal logic of the
circuit to stable state;
 Reset signal is asserted to initialize all flip-flops of the
OCDM circuit to logic ZERO state;
 Mode signal is asserted
measurement mode;
for
activating
delay
 The second vector is applied, and hence the transition
signal is launched at the input and propagated to the
output of PUM, thus the delay difference of the to
transitions is measured by the OCDM and recorded into
the delay line;
Fig. 5 Path delay measurement architecture.
A. Triggering Circuit(TC)
The OCDM circuit works well only when the input and
output of the PUM are rising transitions. The TC thus transfers
the signal into the signal with rising transition regardless of the
transition direction of the original signal for facilitating path
delay measurement.
Block of TC is shown in fig. 5 is used to handle this
problem. Rising transitions taken from the start and end of
PUM are fed into the inputs y and x of the OCDM circuit,
respectively. The basic structure for the TC block is shown in
fig. 6. Simplified timing waveform for TC is shown in fig. 7.
The D signal is always high, whenever a rising or falling
transition is generated at the IN signal, this block transfers to a
rising transition which is generated at the OUT signal.
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 The OCDM circuit is configured into shift mode by deasserting the mode signal after delay measurement. The
values stored in the delay line are shifted out serially
using the shiftclk, the delay of PUM can calculated
using the read out values.
The above steps can be repeated for delay measurement of
all paths.
C. Delay Calculation Of Import Lines
To obtain the delay with high-precision for PUM we
consider the delay for the import lines. The architecture for
path delay measurement scheme shown in fig. 5 is redrawn in
fig. 8, to calibrate the delay difference of the import lines, a 2to-1 multiplexer with data inputs, respectively, connected to
the data input and data output of the flip flop at the end point of
the PUM is included. The path delay measurement is
configured into the delay measurement mode, when MS signal
is set to 1.
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International Journal of Engineering Trends and Technology (IJETT) – Volume 11 Number 9 - May 2014
Fig. 8 Delay calculation of import lines.
The delay measurement result of the PUM without
considering the delay difference of the import lines can be
given as follows:
Delay measurement result=D1-D2+D3
where D1, D2 and D3 are the delays of PUM, import line P2
and P3 respectively. The import line’s delay difference
calibration mode is configured, when MS signal is set to 0.
Fig. 9 Path delay measurement.
IV. SIMULATION RESULTS
In this section, on-chip path delay will be simulated and
measured. During the simulation the delay is measured for
each path under measurement.
A. OCDM Circuit
Seven delay stages are designed in the proposed OCDM
scheme which achieves a maximum path delay measurement
range of 157.75ns, while the last stage has a delay range of
1.25ns. Table I shows delay range of each delay stage.
Fig. 10 Delay calculation of PUM with delay of import lines.
TABLE I
DELAY RANGE OF EACH DELAY STAGE
Delay stage
1st
2nd
3rd
4th
5th
6th
7th
Delay range(ns)
80
40
20
10
5
2.5
1.25
Fig. 11 shows the delay of the import lines with MS set to
0. In this case the OCDM calculates the delay of import lines
P2 and P3. Due to addition of extra multiplexer the delay of
import line P3 will be more than that of P2.
B. Path Delay Measurement
Fig. 9 shows the simulation result for the selected PUM
using the on-chip delay measurement technique. A two test
vector pair is applied to the PUM1 a transition signal is
launched which is fed to the OCDM for delay measurement.
The delay of PUM1 is 130ns which can be calculated using
the values obtained serially at the output of OCDM.
C. Delay Calculation Of Import Lines
Fig. 10 shows the simulation result of the selected PUM
considering the delay of the import lines with MS set to 1.
Fig. 11 Delay calculation of import lines.
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International Journal of Engineering Trends and Technology (IJETT) – Volume 11 Number 9 - May 2014
V. CONCLUSIONS
In this paper, a novel on-chip delay measurement technique
has been presented. From the last to first delay stage, delay
range gradually increases by a factor of two for each delay
stage in the proposed OCDM circuit. Delay difference of the
import lines is also considered for feeding the PUM’s start and
end transitions into the OCDM circuit, which provides the
path delay with high-precision.
ACKNOWLEDGMENT
Authors would like to thank Dept., of PG Studies, VTU
Regional Office, Gulbarga, whose timely support and
suggestions went along in the completion of the project.
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