International Journal of Engineering Trends and Technology (IJETT) – Volume 33 Number 2- March 2016
Low Noise High Performance Wide OR
Domino Logic in DSM Technology
Anshul Namdev #1, Ashish Raghuwanshi #2,
#
PG Student [VLSI], Dept. of ECE, IES college of Engg. Bhopal, RGPV Bhopal, M.P. India
Abstract— Dynamic CMOS circuit exhibits high
performance, faster and more compact than static
CMOS circuit. Also, due to the absence of the PMOS
transistors, the input capacitance is lower. However,
dynamic logic style suffers from charge sharing,
higher power dissipation (due to high switching
activity), clock load and complexity. In this paper we
analyze and compare different topologies of domino
logic at circuit level for low power consumption, high
performance and batter noise immunity. We compare
power, delay, and unit noise gain (UNG) is calculated
by keeping Same W/L ratio of NMOS and PMOS
transistor for fair comparison of results . Simulation
is performed at Cadence virtuoso at 65 nm technology
with supply voltage is of 1 V at 100MHz frequency,
bottleneck operating temperature of 27 degrees
centigrade. Simulation results on 8, 16 and 32 inputs
OR gates with existing and proposed circuit showed
improvements noise immunity and decrease in delay
and power compared with other conventional
techniques.
By scaling down the technology the sensitivity of
the dynamic node to the noise sources has emerged as
a serious design challenge. For improving noise
immunity and reducing leakage the keeper transistor is
added.
However, power dissipation increases and
performance degrades by adding this pMOS keeper
transistor. Upsizing the keeper transistor improves
robustness at a cost of higher power dissipation and
delay. The severity increases many fold in wide
Domino circuits because of higher number of parallel
pull-down branches [2]. Fig. 1 illustrates [12] the
failure mechanism for a 32-in OR gate using FLDL
style at VDD=1 V for temperature 27OC.
Keywords— Wide fan in, CKD, HS, DFD, LCR, UNG.
I. INTRODUCTION
circuit has superior to the static logic circuit [1, 2].
It requires lesser area and reduces output load
capacitance hence enhance the speed [3, 4]. The high
speed domino logic circuit has become one of the
most crucial components of digital circuits. The
scaling of CMOS technology reduces both the
threshold and gate oxide thickness (T ox). The scaling
enhances the leakage current in the domino circuit.
Dynamic circuit typically uses a clock signal to
distinguish between the precharge and evaluation
phases. During the precharge clock (low) phase, the
precharge device is used to pull the output high,
assuming that there does not exist a low impedance
path from the output node to ground [5]. To ensure
that there is no active paths exist through the pull
down network or use evaluation device. An evaluation
device can be used to guarantee that the conducting
paths through the pull-up and pull down networks are
mutually exclusive. During the evaluation clock (high)
phase, the precharge device is turned OFF and pulldown network will either discharge the output node
making high (1) to low (0) transition or stay the same
depending on the input conditions.
ISSN: 2231-5381
Fig. 1 Failure mechanism for 32-in OR gate (FLDL)
Thus trade off exist between delay and power to
improve noise and leakage immunity [3]. Such tradeoff is not acceptable because it may increase the delay
or make the circuit too power hungry. There are
several techniques introduce in the paper to address
this issue.
The rest of the paper is arranged as follows. Section
II, studies five types of circuits that have been
proposed in related literatures, Standard Footless
Domino logic, Conditional Keeper Domino logic,
High Speed domino logic, Leakage Current Replica
diode and Diode Footed Domino logic.
In Section III we have briefly explain the proposed
modified circuit which improves power delay and
UNG. Section IV shows the simulation results and
finally conclusion is offered in Section V.
http://www.ijettjournal.org
Page 90
International Journal of Engineering Trends and Technology (IJETT) – Volume 33 Number 2- March 2016
II. RELATED WORK
In order to maintain the performance of the chip
along with high driving capability at lower supply
voltage, the VTH is reduced. However, the Threshold
Voltage (VTH) scaling results in the substantial
increase of the Subthreshold Leakage Current (I SUB) as
VTH is exponentially proportional to ISUB. In DSM
technology three domination leakage current occurred
in the CMOS device such as ISUB, IGATE, and IBTBT, as
shown in Figure 1.
keeper transistor MP2 turns ON to maintain the
voltage of the dynamic node. During the evaluation
mode, i.e. when the CLK goes HIGH, the dynamic
node is either discharged to ground or remains HIGH
depending on the inputs. Fig.1. Standard Footed
Domino circuit which have Lower Power
consumption by inserting a NMOS transistor Footed
Domino circuit come into existence [2]
VDD
VDD
PRECHARGE TRANSISTOR
CLK
KEEPER TRANSISTOR
MP1
MP2
VDD
G
MP3
DYNAMIC NODE
S
D
Gate Leakage
INn
Substrate
IN2
IN1
OUTPUT
MN1
Subthrehold
Leakage
Reverse Biased
Junction BTBT
Bulk
Fig.2. Standard Footerless Domino Logic Circuit
Fig. 1. Shows Various Leakage current in DSM
technology
2.1 Leakage power dissipation
Total Power dissipation is calculated as:PTotal = PDynamic + PSwatching + PShort-circuit + PStatic
Where PT is the dynamic or switching power
dissipation, occurs due to charging or discharging the
parasitic capacitances in node voltage transition. P ST is
the static or leakage power dissipation, combination of
the subthreshold leakage power due to the not ideal off
state. PShort-circuit is the short circuit power dissipation
occurs during switching operation when both the Pull
Up and Pull Down networks are in ON state. P Static is
the static DC power dissipated
The main power contribution is CMOS technology
is basically Sub-threshols Leakage and gate oxide
leakage current is the dominant in nanometer regime.
B. Conditional Keeper Domino Logic (CKD)
Conditional Keeper employs two keepers, small
keeper and large keeper [5]. In this technique, the
keeper device (PK) in conventional domino is divided
into two smaller ones, PK1 and PK2 as shown in Fig.3.
The keeper sizes are chosen such that PK=PK1+PK2
[6]. Such sizing insures the same level of leakage
tolerance as the conventional gate but yet improving
the speed. The circuit works as follows:
Precharge Phase: In pre-charge phase when clock
is low, the pull-up transistor is on, so the dynamic
node starts being charge up to VDD. Small keeper
transistor PK2 is ON which hold the voltage of
dynamic node to high level.
Evaluation Phase: A high clock pulse is applied. At
the beginning of evaluation phase when clock is high
pre-charge transistors and large keeper PK1 are off.
When all the inputs are at low logic level, i.e. in
standby mode, the dynamic node after the delays of
two inverters remains high, in this condition the output
node of NAND gate goes low, this causes the large
a) Sub-threshols Leakage
keeper PK1 to be turned on. The large keeper is
Sub-threshold leakage current is very significant deployed after a delay for two inverters, to prevent
component of the leakage power and this current erroneous discharge of the dynamic node when all
passes from drain to source through the channel [6-7 inputs remain LOW. The small keeper PK2; however
A. Standard Footless Domino Logic Circuit (SFLD) remain ON to compensate for charge leakage until
The footless scheme [4] is characterized by the PK1 is activated.
fact that discharge of dynamic node is faster. This
property is exploited by the high-performance circuits.
The circuit of the SFLD logic is shown in Fig. 1.
Operation of Footless-Domino is as follows: During
the pre-charge phase, i.e. when then clock (CLK) is
LOW, the dynamic node is charged to VDD and the
ISSN: 2231-5381
http://www.ijettjournal.org
Page 91
International Journal of Engineering Trends and Technology (IJETT) – Volume 33 Number 2- March 2016
VDD
CLK
Delay
PK1
VDD
VDD
PRECHARGE TRANSISTOR
CLK
MP1
PK2
DYNAMIC NODE
OUTPUT
IN2
INn
IN1
Fig.3 Conditional Keeper Domino Logic
C. High Speed Domino Logic (HS)
The circuit of the HS Domino logic is shown in
Fig.4 [7]. In HS domino the keeper transistor is driven
by a combination of the output node and a delayed
clock. The circuit works as follows: At the start of the
evaluation phase, when clock is high, MP 3 turns on
and then the keeper transistor MP2 turns OFF. In this
way, the contention between evaluation network and
keeper transistor is reduced by turning off the keeper
transistor at the beginning of evaluation mode. After
the delay equals the delay of two inverters, transistor
MP3 turns off. At this moment, if the dynamic node
has been discharged to ground, i.e. if any input goes
high, the nMOS transistor MN1 remains OFF. Thus
the voltage at the gate of the keeper goes to VDD-Vth
and not VDD causing higher leakage current though the
keeper transistor [8].
terminals connected together. Fig.5 [9] shows the
Diode Footed Domino configuration. Stacking effect
[10] occur because this transistor M1 is connected in
series with the evaluation network. Thus subthreshold
leakage current reduces as a result of stacking effect.
DFD circuit works as follow:
Preacharge Phase: during this phase a low clock
pulse is applied. Thus during the precharge phase
transistor M3 is ON and it turns off the mirror
transistor M2 to prevent any possible short-circuit
current through M2 during this phase.
Evaluation phase: In this phase high clock pulse is
applied and any of the inputs are allowed to switch to
high level. Due to the leakage current of the
evaluation transistor some voltage drops across the
diode footer M1. Thus a negative voltage exists
between gate and source of the evaluation transistors
that is in OFF mode. This negative voltage
exponentially reduces subthreshold current. Moreover,
the voltage-drop across the diode increases the body
effect of the evaluation transistors, which also helps in
the subthreshold leakage reduction. Thus noise
immunity improves by the higher gate switching
voltage at the expense of speed degradation. Speed is
improved by adding a mirror transistor M 2 as shown in
Fig. 5. By increasing the mirror ratio, the performance
can be increased.
CLK
VDD
VDD
MPRE
MK
DYNAMIC NODE
OUTPUT
Evaluation
Network
VDD
VDD
VDD
N_FOOT
M1
M2
MP3
CLK
MP2
MP1
MN1
CLK
DYNAMIC NODE
OUTPUT
INn
IN2
M3
M4
Fig.5 Diode Footed Domino Logic
IN1
Fig.4 High Speed Domino Logic
D. Diode Footed Domino (DFD)
In diode footed domino we modify the conventional
domino circuit by adding an nMOS transistor M1 in
series with the
foot of the evaluation network. This nMOS
transistor is in diode configuration i.e. gate and drain
ISSN: 2231-5381
E. Leakage Current Replica (LCR)
In Leakage Current Replica Domino logic one extra
pMOS transistor MK1 is stacked above the keeper
transistor as shown in Fig. 6 [11]. Addition to this
pMOS transistor a replica current mirror is added with
MK1. The main function of the current mirror is to
track the leakage current and copies it into the
dynamic gate through the transistor MK1. Construction
of the current mirror is such that it draws current
sf.Ileak where sf is safety factor and Ileak is dynamic gate
leakage current. An extra nMOS transistor M2 is used
in the current mirror. Transistor M2 is in diode
connection and work as a replica of the worst case
leakage current hence its width is set equal to the sum
http://www.ijettjournal.org
Page 92
International Journal of Engineering Trends and Technology (IJETT) – Volume 33 Number 2- March 2016
of the widths of the nMOS transistor in the PDN times
the safety factor. Width of the transistor M1 is equal to
that of the MK1.
In an LCR current mirror, dynamic node must be
pulled close to VDD to avoid compromising the noise
immunity of the dynamic gate, so M1 operates in the
triode region In this mode MK1 exits in saturation
region and continuously rise until MK1’s triode region
current matches the actual leakage current. Rest of the
working is same as that of the conventional domino
logic.
Shared Replica
Current Mirror
VDD
MK1
CLK
MP1
KPR
M1
sf.Ileak
Ileak
MK2
DYNAMIC NODE
M2
OUTPUT
Evaluation
Network
Shared Replica
Current Mirror
VDD
VDD
VDD
VDD
VDD
MK1
CLK
MP1
KPR
M1
sf.Ileak
Ileak
MK2
DYNAMIC NODE
M2
OUTPUT
Evaluation
Network
Fig.6 Leakage Current Replica Domino Logic
III. PROPOSED CIRCUIT
In the previous work, the main focus was directed
towards the feedback loop associated in the domino
logic circuit, which is created by the keeper transistor
and the inverter. This approach was mainly
concentrated for the delay variation in the circuit,
which causes problem for the circuit especially in high
performance application. Therefore the variation in
delay was the centre of point in this circuit analysis. In
this paper we have Modified LCR by inserting NMOS
transistor below dynamic node. At the beginning of
the pre-charge mode the pre-charge device is in active
mode. Therefore the voltage at the dynamic node will
be at 0 V and hence that will pass through an inverter
so the output at the inverter will be VDD. In
consequence the extra added transistor will turn on
and at the beginning of the pre-charge phase there will
be contention of current between the two current
derived from the extra added transistor and the keeper
transistor because the pre-charge. During the
evaluation phase the pre-charge device gets OFF
because at this time the clock switches from logic 0 to
logic 1 as shown in Fig 7.
ISSN: 2231-5381
Fig.7. Modified Diode Current Replica
Despite of having various advantages in domino
logic circuit it suffers a lot by noise and charge
leakage trouble. Therefore in the proposed work the
main area of concentration is the noise immunity of
the circuit without affecting it’s delay performance.
To achieve such performances a new circuit is
proposed. This circuit gives approximately same delay
as the previous circuit with better noise better noise
immunity. The proposed circuit is having an extra
NMOS transistor added to the circuit. The main
function of this extra added transistor is to compensate
the leakage current associated in the circuit.
Considering domino CMOS-OR logic the leakage
current in the circuit is inversely proportional to the
unity noise gain of the circuit. In Fig.8. The proposed
circuit employs nMOS transistors to implement
logical function. The proposed circuit has four
additional transistors, MEval, MDis, MK1, MK2, and a
shared reference circuit compared to standard footless
domino (SFLD). In this topology, the nMOS
transistors MDis turn on conditionally. Gate of the MDis
is connected to the N-FOOT node.
The dynamic power consumption directly depends
on the capacitance, voltage swing, and contention
current on the switching node in the constant
condition for frequency, power supply, and
temperature. Although the proposed circuit has less
dynamic power consumption and low delay at the
expense of some area overhead compared to footless
domino. It should be noted that if the source and body
terminals are not at the same voltage level then body
effect will occurs, thus the leakage current will be
decreased further at the expense of higher deviation
due to process variations.
http://www.ijettjournal.org
Page 93
International Journal of Engineering Trends and Technology (IJETT) – Volume 33 Number 2- March 2016
VDD
Reference circuit for all gate
VDD
S.No.
CLK
MPre
M1
VDD
VDD
M5
M6
1.
SFLD
2.
FDL
M7
3.
CKD
M8
4.
HSD
5.
DFD
6.
LCR
VDD
CLK
Out
IN0
transistors INK
VDD
MK1
MK2
N-FOOT
CLK
M4
MDis
Evaluation
Domino
Circuits
M3
CLK
MEval
Fig.8. Modified Current-Comparison Based
Domino
7.
8.
IV. RESULTS AND DISCUSSION
Simulations are performed by using Spectre
Cadence tool in 65 nm technology at 1 GHz frequency
and VDD of 1 V. width of the keeper is set equal to
0.25µm. The fall/rise times of the waveforms were set
to 1pS. Delay power dissipation and UNG is
calculated for 8, 16 and 32 input OR gate in various
logic style. Delay is calculated by using Cadence
spectra calculator. For delay calculation high voltage
is applied at only one input and remaining all input are
kept at low level in evaluation phase. For calculation
of UNG [12], a pulse noise is applied to all inputs with
amplitude which is a fraction of supply voltage and a
pulse width equal to 30% of duty cycle. Then, the
amplitude of the input noise pulse is increased until
the amplitude of the resulting output noise voltage is
equal to that of the input noise signal. This noise
amplitude is defined as
UNG= Vin,Vnoise = Voutput
Proposed
Modified LCR
Proposed
Modified CCD
8
INPUT
2.31
1
3.76
1
5.76
1
6.34
1
2.52
1
3.12
6
2.01
7
1.89
1
16
INPUT
32
INPUT
5.521
8.346
6.356
9.671
7.447
11.276
9.262
12.34
3.891
5.945
6.103
10.981
5.143
7.892
4.725
7.312
Fig.10 Average Power Consumption
TABLE II.COMPARISION OF UNG (in Volt)
S.
No.
1.
2.
3.
4.
5.
6.
7.
8.
Domino
Circuits
SFLD
FDL
CKD
HSD
DFD
LCR
Proposed
Modified LCR
Proposed
Modified CCD
8
INPUT
16
INPUT
32
INPUT
0.256
0.261
0.286
0.279
0.291
0.281
0.221
0.234
0.231
0.228
0.252
0.241
0.201
0.205
0.210
0.203
0.211
0.204
0.298
0.258
0.221
0.310
0.561
0.224
Fig.9. Transient response of 2 input proposed
domino OR logic
TABLE
I.
COMPARISION
DESSIPATION (in µW)
ISSN: 2231-5381
OF
POWER
http://www.ijettjournal.org
Page 94
International Journal of Engineering Trends and Technology (IJETT) – Volume 33 Number 2- March 2016
threshold voltage improves the noise immunity. Thus
UNG of DFD logic is higher than the other domino
logic. Leakage Current Replica shows best result in
term of speed as compared to other logic. The reason
behind this high speed is that the current mirror tracks
the leakage current and copies it into the dynamic gate.
REFERENCES
[1] L. T. Clarke, G. F. Taylor, “High fan-in circuit design,” IEEE
Journal of Solid-State Circuits, vol. 31, Issue 1, January 1996,
pp.91-96.
Fig.11 UNG Comparison
TABLE III.COMPARISION OF DELAY (in ps)
S.
No.
Domino Logic
8 INPUT
16 INPUT
32 INPUT
1.
SFLD
14.20
19.53
28.59
2.
FLD
15.23
20.65
29.35
3.
CKD
17.10
22.13
31.23
4.
HSD
14.41
18.32
28.43
5.
DFD
17.56
24.21
33.12
6.
LCR
13.93
17.51
25.34
12.35
18.27
27.18
11.98
17.93
26.56
7.
8.
Proposed
Modified LCR
Proposed
Modified CCD
[2] Farshad Moradi, TuanVuCao, ElenaI.Vatajelu, AliPeiravi,
Hamid
Mahmoodi, DagT.Wisland, “Domino logic designs for
high-performance and leakage-tolerant applications,” Elsevier
INTEGRATION, the VLSI journal, Issue 24 April 2012.
[3] Farshad Moradi, AliPeiravi, HamidMahmoodi, “A New
Leakage Tolerant Design for High Fan-in Domino circuits, ” 2004
IEEE.
[4]
B.-Y. Tsui, L.-F. Chin, “A comprehensive study of the
FIBL of nanoscale MOSFETs,” IEEE Transactions on Electron
Devices 51 (10) (2004) 1733–1735.
[5] A. Alvandpour, R.K. Krishnamurthy, K. Soumyanath, S.Y.
Borkar, “A sub-130-nm conditional keeper technique,” IEEE
Journal of Solid-State Circuits 37 (2002) 633-638.
[6] A. Alvandpour, R. Krishnamurthy, K. Soumayanath, ands.
Borkar, “ A
Low-Leakage Dynamic Multi Ported
Register File in 0.13 µm CMOS,” in proceedings of international
Symposium on Low Power Electronics and Design, 2001, pp. 68-71.
[7]
M.W. Allam, M.H. Anis, M.I. Elmasry, “High speed
dynamic logic style for scaled- down CMOS and MTCMOS
technologies,” in: Proceedings of the International Symposium on
Low Power Electronics and Design, 2000, pp. 155–160.
[8] M. H. Anis, M. W. Allam, and M. I. Elmasry, “Energyefficient noisetolerant dynamic styles for scaled-down
CMOS and MTCMOS
technologies,” IEEE Trans. Very
Large Scale (VLSI) Syst., 2002.
[9] Hamid Mahmoodi and Kaushik Roy, “Diode-Footed Domino:
A Leakage-Tolerant High Fan-in Dynamic Circuit Design Style,”
IEEE Transactions on Circuits and Systems—i: Regular papers,
VOL. 51, NO. 3, MARCH 2004.
[10] K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand,
“Leakage current mechanisms and leakage reduction techniques in
deep-submicron CMOS circuits,” Proc. IEEE, vol. 91, pp. 305–327,
Feb. 2003.
Fig.12 Delay Comparison
[11] Yolin Lih, Nestoras Tzartzanis and William W. Walker, “A
Leakage Current Replica Keeper for Dynamic Circuits,” IEEE
JOURNAL OF SOLID-STATE CIRCUITS, VOL. 42, NO. 1,
JANUARY 2007.
V. CONCLUSION
In this paper, several domino logic circuit topologies
were proposed for high-speed and leakage-tolerant
design. From the simulation result we can conclude
that power dissipation of the Diode Footed Domino is
minimum due to the stacking effect and body biasing
of the nMOs transistor that reduces the subthreshold
leakage current exponentially while the speed is
degraded because of the increase in switching
threshold voltage. On the other hand this increased
ISSN: 2231-5381
http://www.ijettjournal.org
Page 95