International Journal of Engineering Trends and Technology (IJETT) – Volume 33 Number 1- March 2016
A New Leakage Reduction Technique at
Nanoscale circuit Design
Vikas Singhai #1, Saima Ayyub #2, Paresh Rawat#3
#
PG Student [VLSI], Dept. of ECE, Truba College of Science and Technology Bhopal
Bhopal, India
Abstract— The popularity and necessity of portable
electronic systems by users have strongly influenced
VLSI designers to make great effort for reduced
silicon area, improved speeds, long duration battery
life, and great reliability. The VLSI designers always
try to save power consumption while designing a
system. The performance of circuit is strongly
influenced by the choice of logic style to design the
digital circuit. In a few technology generations,
leakage power is supposed to become a main
contributor of total power consumption. Power
consumption has become primary design issue and
needs suitable power management in the design of
digital circuits where switching and standby mode
affects the performance of system. In this paper we
have calculate the leakage power consumption of
conventional gates and proposed leakage reduction
techniques over various gates at 32nm process
technology with supply voltage of 0.8V by using
HSPICE simulator at 100MHz frequency.
Keywords— Leakage Power, SCE, NAND gate, Sleep
transistor.
VLSI designers to make great effort for reduced
silicon area, improved speeds, long duration battery
life, and great reliability. The VLSI designers always
try to save power consumption while designing a
system. The performance of circuit is strongly
influenced by the choice of logic style to design the
digital circuit. Design optimization at circuit level is
very important to avoid any degradation in output
voltage level, to achieve less power consumption, to
have less propagation delay in critical path and to be
reliable at reduced supply voltage as we scale down
towards deep sub micron technology. Switching
activity of circuit affects the dynamic power
consumption but with the technology scaling, the
number of transistors is continuously reduced which
increases the static leakage power at lower supply
voltage. In a few technology generations, leakage
power is supposed to become a main contributor of
total power consumption. Power consumption has
become primary design issue and needs suitable power
management in the design of digital circuits where
switching and standby mode affects the performance
of system.
II. RELATED WORK
I. INTRODUCTION
It is time we explore the well-engineered deep
submicron CMOS technologies to address the
challenging criteria of these emerging low-power and
high-speed communication digital signal processing
chips. The performance of many applications as
digital signal processing depends upon the
performance of the arithmetic circuits to execute
complex algorithms such as convolution, correlation,
and digital filtering. Fast arithmetic computation cells
including adders and multipliers are the most
frequently and widely used circuits in very-large-scale
integration (VLSI) systems. The semiconductor
industry has witnessed an explosive growth of
integration of sophisticated multimedia-based
applications into mobile electronics gadgetry since the
last decade. However, the critical concern in this arena
is to reduce the increase in power consumption
beyond a certain range of operating frequency.
Moreover, with the explosive growth, the demand, and
the popularity of portable electronic products, the
designers are driven to strive for smaller silicon area,
higher speed, longer battery life, and enhanced
reliability. The popularity and necessity of portable
electronic systems by users have strongly influenced
ISSN: 2231-5381
In order to maintain the performance of the chip
along with high driving capability at lower supply
voltage, the VTH is reduced. However, the Threshold
Voltage (VTH) scaling results in the substantial
increase of the Subthreshold Leakage Current (I SUB) as
VTH is exponentially proportional to ISUB. In DSM
technology three domination leakage current occurred
in the CMOS device such as ISUB, IGATE, and IBTBT, as
shown in Figure 1.
G
S
D
Substrate
Gate Leakage
Subthrehold
Leakage
Reverse Biased
Junction BTBT
Bulk
Fig. 1. Shows Various Leakage current in DSM
technology
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International Journal of Engineering Trends and Technology (IJETT) – Volume 33 Number 1- March 2016
2.1 Leakage power dissipation
III. LEAKAGE CURRENT IN BASIC NAND
GATE
Total Power dissipation is calculated as:PTotal = PDynamic + PSwatching + PShort-circuit + PStatic
Where PT is the dynamic or switching power
dissipation, occurs due to charging or discharging the
parasitic capacitances in node voltage transition. PST is
the static or leakage power dissipation, combination of
the subthreshold leakage power due to the not ideal off
state. PShort-circuit is the short circuit power dissipation
occurs during switching operation when both the Pull
Up and Pull Down networks are in ON state. P Static is
the static DC power dissipated
The main power contribution is CMOS technology
is basically Sub-threshols Leakage and gate oxide
leakage current is the dominant in nanometer regime.
a) Sub-threshols Leakage
Sub-threshold leakage current is very significant
component of the leakage power and this current
passes from drain to source through the channel [6-7].
The sub-threshold leakage current is caused basically
due to carrier diffusion between the source and drain
region of the transistor in weak inversion. For a
particular MOS transistor whenever applied gate to
source voltage is less than the threshold voltage of the
transistor, there is no flow of current. Mathematically
When
Vgs < Vt
Ids =0
A graph is prepared by nodes and links, which
represented by transistors and their interconnection
respectively. Figure 2, shows the Graphical
representation of 2 input NAND gate. Here a, b are the
inputs and y is the output of the given circuit. VDD and
GND are the power supply and ground nodes. This
logic gate is used as a basic gate for implementation of
every other gate for simulation. It is used CMOS logic
design style. Here two input NAND logic gate is used
as a basic gate for each logic and combinational circuit.
Firstly NAND gate and its variants are created using
CMOS design style. Secondly all the test circuits are
implemented by NAND gate and analyzed by using
these variants. it. For Simulation HSPICE is taken as a
simulator tool. It requires a spice code (Transistor
level net-list) of the desired circuit for their parameters
calculation. All the circuits are mapped with 180nm,
130nm, 90nm, 65nm and 45nm BPTM technology file.
This file contains every physical design details of a
CMOS transistor, where 45nm is the effective length
of CMOS transistor. All kind of analysis with
mapping of this file is shown through the flow of
HSPICE design flow. Firstly the proposed NAND gate
circuit operation is explained. In sleep mode, the sleep
transistors are off, i.e. transistor M1, M2 and Y1,Y2
are off. We do so by making S=0 and hence S‟=1.
Now see that the working of the basic NAND gate the
output of the NAND gate is one either input is Zero
with different combination of the input vector.
VDD
b) Gate oxide tunnelling current
Tunnelling through gate oxide occurs because
thickness of gate oxide layer is gradually reduced as
technology is reducing[7]. The gate oxide tunnelling
current is caused because of tunnelling of electrons
through nMOS capacitor with a heavily doped n+
polysilicon gate and p type substrate.
The sleepy stack technique divides existing
transistors into two transistors each typically with the
same width half the size of the original single
transistor‟ s width. Then sleep transistors are added in
parallel to one of the transistors in each set of two
stacked transistors; the divided transistors reduce
leakage power using the stack effect while retaining
state. The most efficient approach for leakage power
reduction is sleepy keeper approach. As we know that
PMOS transistor is connected to Vdd & NMOS
transistor is connected to GND. A NMOS transistor
will not pass Vdd efficiently, so to overcome this
problem to maintain a value of “1” in sleep mode, the
sleepy keeper approach is used.
ISSN: 2231-5381
M1
M2
a
y
M3
b
M4
GND
Fig.2. Graphical representation of 2input NAND
gate
During operation of two input NAND gate (i.e.
input vector „00‟), then transistor M1 and M2 turn
ON and transistor M3 and M4 turns of in which take
part in leakage current. When input vector(i.e. is 01)
the transistor M2 and M4 turn off and take part in
leakage contribution, at input vector 10 M1 and M3
turns off and take part in leakage current contribution.
When input vector is 11 maximum leakage current
flows by the two M1 and M2 transistor. These
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International Journal of Engineering Trends and Technology (IJETT) – Volume 33 Number 1- March 2016
parameters are Leakage Current (I Leak), Static Power
dissipation (PST) and Dynamic Power dissipation (P D),
Total Power (PT), delay and PDP. Performance of
CMOS circuits is depends on these parameters. For
DSM circuits mainly ISUB is the dominating
component of power dissipation in CMOS IC.
III. PROPOSED METHODOLOGY
In this section, we discuss the structure and
operation of the proposed low-leakage-power design
stack with sleepy keeper. The proposed circuit is
compared with well-known previous approaches, i.e.,
Conventional Gates. In Proposed approach we have
taken two technique stack approach with sleepy
keeper approach to reduce the leakage power
consumption in the circuit. Here we use two NMOS
Sleep transistor in pull down network and two Sleep
transistor PMOS in pull up network, so as to provide
the stacking of the transistor for further leakage
reduction. To maintain the proper logic level “1” we
insert NMOS transistor parallel to PMOS stacked
transistor in pull up network, to connect sleep
transistor to Vdd to the pull up network. In sleep mode,
this NMOS transistor connects Vdd to the pull up
network when sleep transistor cut off.
Similar action also repeat in pull down network the
two Sleep NMOS transistor provide the stacking effect
(Fig.7.). To maintain the value “0” in sleep mode a
PMOS transistor connect parallel with two NMOS
transistor. To maintain an output value to “0” PMOS
transistor connected to GND in sleep mode. For
Proper Logic NMOS connect to Vdd and PMOS
connect to GND. The stacking of the transistor
reduces the leakage power in proposed approach and
enhances the performance of the circuit by
maintaining proper logic of the circuit.
Vdd
Fig.4. Output Wave form of Proposed Circuit
V. RESULTS AND DISCUSSION
Leakage current for Proposed circuit is calculated
by using Berkley Predictive Technology Module
(BPTM) in HSPICE simulator using 32nm process
technology with supply voltage of 0.8V at 10MHz
frequency and CL=1pf. Leakage power of
conventional gate is compared with Proposed
technique implemented in with all the input vector
combination at 250 C and 1000 C temperature
respectively. Transient analysis of proposed technique
with Nand gate is shown in Fig.4. It is observe that
output wave form provides proper logic.
Table I. Leakage Power Consumption of Basic
Gates at 32nm at 250 C
Gates
P3
S1
N3
P4
NOT
AND
P2
P1
Input1
NAN
Out
N1
Input2
D
NOR
N2
EXO
N4
R
S2
Leakage
32nm
00
10.14
8
21.34
6
3.921
1
20.26
7
49.28
0
Power Consumption at
01
24.8
10
11
48.6
30.0
59.9
0
31.2
2
12.5
7
24.9
49.7
3
24.3
3
43.7
42.9
0
43.7
0
49.2
8
P5
N5
Gnd
Fig.3. Proposed Circuit
ISSN: 2231-5381
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International Journal of Engineering Trends and Technology (IJETT) – Volume 33 Number 1- March 2016
Table II. Leakage Power Consumption at 32nm at
1000 C
Gates
NOT
AND
NAN
D
NOR
EXO
R
Leakage Power Consumption (nW)
00
01
10
11
73.
44.9
87
8
116
185.
163.9
164.
.1
1
4
28.
96.3
75.11
89.8
07
1
0
146
44.8
42.66
51.2
.8
8
4
87.
170.
170.9
87.4
44
9
8
4
Gate
NOT
AND
NAND
NOR
EXOR
Leakage Power Consumption at
32nm
00
01
10
11
2.580
11.3
8
12.77
43.0
15.3
54.4
9
8
3
2.340
7.70
5.30
3.94
0
8
4
3.117
11.4
11.4
13.8
4
1
8
14.19
10.5
10.5
14.1
9
9
9
Table IV. Leakage Power Consumption of
Proposed Technique at 32nm at 1000 C
Gate
s
NOT
AND
NAND
NOR
EXOR
Leakage
(nW)
00
18.8
3
9
88.5
3
4
14.6
0
7
22.0
7
0
46.0
1
6
ISSN: 2231-5381
Power
01
25.7
Consumption
10
85.3
11
96.5
3
28.0
90.9
4
22.6
4
25.8
44.1
2
25.7
8
33.7
43.2
1
33.7
6
46.0
1
In nanometer scale CMOS technology, subthreshold leakage power is compatible to dynamic
power consumption, and thus handling leakage power
is a great challenge. In this paper, we present a new
circuit structure named “stacking with sleepy keeper
Approach” to tackle the leakage problem. . It
proposes a technique for reducing the leakage current
during idle mode of circuit. The proposed technique
can be applied on high performance, low power
application, where leakage is major concern such as
microprocessor, memory units and other portable
devices. In future new approach of leakage reduction
technique at gate level and block level are expected to
give more power saving than the existing approach at
CMOS circuit level design.
REFERENCES
Table III. Leakage Power Consumption of
Proposed Technique at 32nm at 250C
s
IV. CONCLUSION
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