International Journal of Engineering Trends and Technology (IJETT) – Volume 29 Number 5 - November 2015
Design of a New Dual Dynamic Flip-Flop with Low Power and
Low Area
S. Shabeena#1, Dr. R. Ramana Reddy*2, Mrs. D. Rama Devi#3
Student, Professor, Associate Professor, Department of ECE,MVGR College of Engineering,
Vizianagaram, A.P.
Abstract: The fast growth of the power density in
integrated circuits has made area and power
dissipation as the vital design measures. Latches and
flip-flops are the basic elements for storing
information. From the open literature, Dual Dynamic
Flip-Flop is classic structure that dissipates less
power. In this paper a dual dynamic flip flop (DDFF)
is designed by using MTCMOS technique. The
DDFF-MTCMOS design reduces standby power but
it suffers from higher threshold voltages. The
drawback which is associated by using MTCMOS
technique can be solved by using Self Controllable
Voltage Level (SVL) circuit. The DDFF-SVL design
dissipates less power but it suffers from large area
penalty. In order to overcome the drawbacks as a
result of incorporating MTCMOS and SVL logic in
DDFF a new dual dynamic flip flop with low area
and low power is proposed. The proposed design
dissipates less power due to the large pre charge
node capacitance, with reduced number of
transistors. The comparative power analysis and
performance improvements indicate that the
proposed design is suitable for high-performance
digital designs where the area and power dissipation
is of major concern. The proposed flip-flop reduces
50% to 60% of power dissipation as compared to
conventional flip-flops and area up to 48% is also
reduced. Serial in Serial out (SISO) shift register is
designed with the proposed flip-flop which exhibit
low power dissipation. The simulations are done in
MENTOR GRAPHICS, Schematic editor, Generic
GDK, 130nm technology.
Index terms: DDFF, high speed, low power, power
dissipation, high-performance, SVL logic.
I INTRODUCTION
Over the past decade, power consumption of VLSI
chips has constantly been increasing. Moore’s Law
drives VLSI technology to continuous increases in
transistor densities and higher clock frequencies. The
trends in VLSI technology scaling in the last few
years show that the number of on-chip transistors
increased about 40% and operation frequency of
VLSI systems increased about 30% every year.
Although capacitances and supply voltages scale
down meanwhile, power consumption of the VLSI
chips is increasing continuously. On the other hand,
ISSN: 2231-5381
cooling systems are not improving as fast as the
power consumption is increasing. Most of the
portable devices are design by the combination of
sequential circuits. Sequential circuits are designed
by the combination of flip-flop circuits. A low power
dissipating and area efficient VLSI systems can be
designing by using low power dissipating and area
efficient flip-flops.
Flip-Flop which is a basic building block of
many electronic circuits stores a logical state of one
data in response to a clock pulse. Flip-Flops are often
used in computational circuits to operate in selected
sequences during recurring clock intervals to receive
and maintain data for a limited time period. At each
rising or falling edge of a clock signal, the data stored
in a flip-flop is readily available so that it can be
applied as inputs to other combinational or sequential
circuitry. To achieve low power dissipation and area
efficient, three new D flip-flop architectures are
proposed and compared with the conventional flipflops and the performance is analysed.
II POWER DISSIPATION
The total power dissipated in generic digital CMOS
gate is calculated by using equations (1 - 4)
Ptotal Pdynamic Pshort circuit Pstatic (1)
2
P.CL . f .VDD
Pdynamic
Pshort circuit
Pstatic
I peak .t SC .VDD . f
I static .VDD
(2)
(3)
(4)
Where p = Change state probability of gate.
f = frequency
CL = Load Capacitance
VDD = Supply Voltage
Ipeak = Maximum current during the status of
gate
tSC = sort circuit time
Istatic = static current
There are three major components of power
dissipation
in
complementary
metal–oxide–
semiconductor (CMOS) circuits. 1) Switching
Power,2) Short Circuit Power and 3) Static
Power.Dynamic power constitutes the majority of the
power dissipated in CMOS VLSI circuits. It is the
power dissipated during charging or discharging the
load capacitances of a given circuit. Power
http://www.ijettjournal.org
Page 232
International Journal of Engineering Trends and Technology (IJETT) – Volume 29 Number 5 - November 2015
consumption of the circuit is reduced by reducing any
of the component parameters. It is of equal
importance to increase the system-clock frequency
for faster operation.
III REVIEW ON EXISTING FLIP-FOPS
A. POWER PC 603 FLIP-FLOP:
Power PC means Performance Optimization with
Enhanced RISC Performance Computing. The power
dissipation is low and also having low clock-to
output (CLK-Q) delay. In synchronous systems, the
latching elements have the delay overhead which is
expressed by the data-to-output (D-Q) delay rather
than CLK-Q delay. Here, D-Q delay is the
combination of CLK-Q delay and the setup-time of
the Flip-Flop. But the static designs lack the low D-Q
delay due to their large positive setup-time, and also
most of them are susceptible to flow through
resulting from CLK overlap.
The PowerPC 603 master-slave latch [1] is shown in
Fig 1. It has the advantages ofhaving a low-power
keeper structure and a low latency direct path. It is
one of the fastest classical structures and itsmain
advantage is the short direct path and low power
feedback. The large load on the clock will greatly
affect thetotal power consumption of the flip-flop.
This flip-flop is the transmission gate flip-flop, it has
a fully static master–slave structure, which is
constructed by cascading two identical pass gate
latches and provides a short clock to output latency.
It does have a worse data-to-output latency because
of the positive setup time and its sensitivity toclock
signal slopes and data feed through is another
concern when using it. The large D-Q delay resulting
fromthe positive setup time is one of the
disadvantages of this design. Also, the large data and
CLK node capacitancesmake the design inferior in
performance. Despite all these shortcomings, static
designs still remain as the low powersolution when
the speed is not a primary concern.
Fig 1: PowerPC 603 flip-flop.
B.HYBRID LATCH FLIP-FLOP (HLFF):
The hybrid latch flip-flop (HLFF)is one of the fastest
flip-flop structure. It is robust to clock signal slopes,
but it does have a positive hold time. This design is
very suitable for high performance system as shown
in fig 2. This structure is basically a level sensitive
latch which is clocked with an internally generated
sharp pulse. This sharp pulse is generated at the
positive edge of the clock and delayed version of the
clock [2]. Due to this large hold time requirement the
integration of HLFF to design complex circuits is a
difficult process.
Fig 2: Hybrid Latch Flip Flop(HLFF).
ISSN: 2231-5381
http://www.ijettjournal.org
Page 233
International Journal of Engineering Trends and Technology (IJETT) – Volume 29 Number 5 - November 2015
C.CONDITIONAL DATA MAPPING FLIP-FLOP:
Fig 3 is Conditional Data Mapping Flip-Flop
(CDMFF), it is the most efficient attempt to reduce
the redundant data transitions in the flip-flop.
CDMFF uses an output feedback structure to
conditionally feed the data to the flip-flop which
reduces overall power dissipation by eliminating
unwanted transitions when a redundant event is
predicted. Since there are no added transistors in the
pull down NMOS stack, the speed of the performance
is not greatly affected. But the presence of three
stacked NMOS transistors at the output node, similar
to HLFF, and the presence of conditional structures
in critical path increase the hold time requirement
and D-Q delay of the flip-flop [3]. Also, the
additional transistors added for the conditional
circuitry make the flip-flop bulky and cause an
increase in power dissipation at higher data activities.
Fig 3: Conditional Data Mapping Flip-Flop (CDMFF).
Fig 4: Cross Charge Control Flip Flop (XCFF).
E. DUAL DYNAMIC FLIP-FLOP (DDFF):
The dual dynamic flip-flop (DDFF) acts like static
and dynamic circuit and the schematic is shown in
below fig 5. The operation of DDFF is based on the
dynamic logic principles. This flip-flop requires two
phases to operate based on the clock input to the
circuit. The architecture exhibits negative setup time,
since the short transparency period defined by the 11overlap of CLK and CLKB allows the data to be
sampled even after the rising edge of the CLK before
CLKB falls low. Node X1 undergoes charge sharing
when the CLK makes a low to high transition while
D is held low [1,6]. This results in a momentary fall
in voltage at node X1.At the end of evaluation phase,
as the CLK falls low, node X1 remains high and node
X2 stores the charge dynamically.In DDFF, due to
feedback structure at the output node, the switching
for more data patterns is inefficient [7, 8].
D.CROSS
CHARGE
CONTROL
FLIPFLOP(XCFF):
The cross charge control flip-flop (XCFF) reduces
the power dissipation by splitting the dynamic node
into two, each one separately driving the output pullup and pull-down transistors as shown in fig 4. The
total power consumption is almost reduced without
any degradation in speed because; only one of the
two dynamic nodes is switched during one clock
cycle [4]. XCFF has a comparatively lower CLK
driving load. The major drawback of this design is
that, the redundant precharge at node X2 and X1 for
data patterns containing more 0s and 1s respectively.
Due to the conditional shutoff mechanism, the large
hold time requirement appears, and a low to high
transition in the CLK when the data is low, causes
charge sharing at node X1. The problem of charge
sharing becomes very high when complex functions
are incorporated into the design [5].
ISSN: 2231-5381
http://www.ijettjournal.org
Fig 5: Dual Dynamic Flip Flop (DDFF).
Page 234
International Journal of Engineering Trends and Technology (IJETT) – Volume 29 Number 5 - November 2015
IV PROPOSED FLIP-FLOP ARCHITECTURES
A. INCORPORATING MTCMOS TECHNIQUE IN
DDFF DESIGN.
In order to reduce the standby power the DDFF is
implemented by using MTCMOS logic. Multi
threshold voltage CMOS (MTCMOS) reduces the
leakage by inserting high threshold device in series
with low threshold circuitry. Fig 6 shows the
schematic of DDFF with MTCMOS logic. In the
active mode the sleep control transistors (MP and
MN) are turned on. Since their on-resistances are
small, the virtual supply voltages (VDDV and VSSV)
almost function as real power lines. In the standby
mode, MP and MN are turned off, and the leakage
current is low. MTCMOS reduces Pst (standby
power) by disconnecting the power supply through
the use of P-MOSFET switches with higher threshold
voltage. It has severe drawbacks such as need for
additional fabrication process for higher Vth and the
fact storage circuits based on the MTCMOS
technique can’t retain data [1,10].
(n-SW), and the lower SVL circuits consist of single
n-MOSFET switch (n-SW) and m p-MOSFET
switches connected into series. The ―on p-SW‖
connects power supply Vdd and load circuit in active
mode and ―on n-SW‖ connects VDD and load circuit
in standby mode. Same as the lower SVL circuit
consists of single n-MOSFET switch (n-SW) and m
p-MOSFET switch connected in series it is located
between the ground level and load circuit. The lower
SVL not only supply Vss to achieve load circuits use
of ―on n-SW‖ but also it supply’s Vss to standby load
circuit use of on pSW. where the load circuit is active
both the p-SW and n-SW are turned into on, but the
nRSI&pRSI are turned into off, then the upper SVL
and lower SVL circuits are supply maximum supply
voltage (VD=VDD) and minimum ground level
voltage (VS=VSS=0) to the active load circuit then
the operating speed of the load circuit can be
maximized.
Fig 7: DDFF with SVL logic (proposed flip-flop-2)
Fig 6: DDFF with MTCMOS logic (proposed flip-flop-1)
B. INCORPORATING SVL TECHNIQUE IN
DDFF DESIGN.
Self-Controllable-Voltage-Level (SVL) technique
overcomes the drawbacks occurred by the MTCMOS
technique. Fig 7 shows the schematic of DDFF with
SVL logic. This circuit significantly decreases Pst
(standby power) while maintaining high speed
performance. The SVL circuit consists of an upper
SVL (U-SVL) and lower SVL (L-SVL) circuit. In
dual dynamic node hybrid flip-flop has been used as
the load circuit. The upper SVL consist of single PMOSFET switch (P-SW) and m n-MOSFET switches
ISSN: 2231-5381
C. A NEW DUAL DYNAMIC FLIP-FLOP BASED
ON DDFF DESIGN.
The standby power is reduced by using SVL logic but
the area is increased. In order to reduce both area and
power a new dual dynamic flip flop is proposed. The
proposed flip flop is designed in such a way that it
comes with the reduced area due to minimum number
of transistors used for the design. The basic concept
behind this structure comes from the overlap based
cell and the DDFF design mentioned above. The
power dissipation of this flip-flop design is lower
than the existing flip-flop designs as shown in Fig 8.
http://www.ijettjournal.org
Page 235
International Journal of Engineering Trends and Technology (IJETT) – Volume 29 Number 5 - November 2015
Fig 8: A new dual dynamic flip flop (Proposed Flip-Flop-3)
Fig 9: Waveform of proposed flip-flop-3
V DESIGN OF SERIAL-IN SERIAL-OUT (SISO)
SHIFT REGISTER
Shift registers are high speed circuits. In SISO The
data string is presented at 'Data In', and is shifted
right one stage each time 'Data Advance' is
brought high. At each advance, the bit on the far left
(i.e. 'Data In') is shifted into the first flip-flop's
output. The bit on the far right (i.e. 'Data Out') is
shifted out and lost. The data are stored after
each flip-flop on the 'Q' output, so there are four
storage 'slots' available in this arrangement; hence it
is a 4-bit Register. To give an idea of the shifting
pattern, imagine that the register holds 0000 (so all
storage slots are empty). As 'Data In' presents 1,
0,1,1,0,0,0,0 (in that order, with a pulse at 'Data
Advance' each time—this is called clocking or
strobing) to the register. The left hand column
corresponds to the left-most flip-flop's output pin,
and so on. So the serial output of the entire register is
10110000. It can be seen that if data were to be
continued to input, it would get exactly what was put
in, but offset by four 'Data Advance' cycles. This
arrangement is the hardware equivalent of a queue.
Also, at any time, the whole register can be set to
zero by bringing the reset (R) pins high.This
arrangement performs destructive readout - each data
is lost once it has been shifted out of the right-most
bit.
Fig 10 shows the implementation of SISO shift
register with Cross Charge Control Flip-Flop
(XCFF). Fig 11 shows the implementation of SISO
shift register with Dual Dynamic Flip-Flop (DDFF).
Fig 12 shows the implementation of SISO shift
register with proposed flip-flop-3.
VI SIMULATION RESULTS
In order to compare the performance of proposed
flip-flop with existing flip-flop designs, all the
circuits are simulated in 130nm CMOS technology of
mentor graphics tools with a supply voltage of 1.2V.
Table I illustrates the performance comparison of
various flip-flops and table II summarizes
comparisons of SISO shift registers.
Fig 10: Implementation of SISO shift register with Cross Charge Control Flip-Flop (XCFF).
ISSN: 2231-5381
http://www.ijettjournal.org
Page 236
International Journal of Engineering Trends and Technology (IJETT) – Volume 29 Number 5 - November 2015
Fig 11: Implementation of SISO shift register with Dual Dynamic Flip-Flop (DDFF).
Fig 12: Implementation of SISO shift register with proposed flip-flop-3
TABLE 1: PERFORMANCE COMPARISON OF VARIOUS FLIP-FLOPS
Flip-Flop
Number of
transistors
22
Total layout
area (μm2)
5129.685
D-Q
DELAY
21.592ns
CLK-Q
DELAY
21.092ps
RISETIME
FALLTIME
52.535ps.
120.16ps
POWER
DISSIPATION
16.2621NW
HLFF
20
1480.828
29.270ns
693.93ps
90.627ps
40.008ps
11.133NW
CDMFF
22
1231.798
131.50ps
631.50ps
151.53ps
231.42ps
10.531NW
XCFF
21
1055.598
50.818ps
29.237ps
34.704ps
26.80ps
15.2337NW
DDFF
18
800.565
274.17ps
660.31ps
155.06ps
231.45ps
14.77NW
DDFFMTCMOS
DDFF-SVL
Proposed
Flip-Flop
20
1015.657
330.31ps
274.17ps
145.06ps.
235.25ps.
6.509NW
26
10
1256.578
383.578
637.42ps
238.43ps
179.47ps
350.21ps
35.138ps.
113.46ps
37.892ps.
144.46ps
6.081NW
6.4889NW
POWERPC
603
ISSN: 2231-5381
http://www.ijettjournal.org
Page 237
International Journal of Engineering Trends and Technology (IJETT) – Volume 29 Number 5 - November 2015
Fig 12: Wave form of SISO shift register by using proposed flip-flop-3
TABLE II: COMPARISION RESULTS OF SISO SHIFT REGISTERS
SISO(XCFF)
SISO(DDFF)
SISO(proposed
flip-flop-3)
CLK-Q
DELAY
29.235ns
255.89ps
735.73ps
RISETIME
FALLTIME
25.370ps
33.442ps
103.47ps
26.536ps.
30.442PS
34.099ps
VII CONCLUSION
In this paper a new dual dynamic flip-flop is
proposed. The proposed flip-flop architecture
exhibits reduction in the power dissipation up to 5060% and delay up to 86% than the conventional flipflops. A SISO shift register is designed using
conventional and proposed flip-flop. The SISO shift
register designed with proposed flip-flop exhibits
83% of reduction in the power dissipation.
As a future work, complex logic functions
can be incorporated into the proposed flip-flop-3.
REFERENCES
[1]. KalarikkalAbsel, Lijo Manuel, and R. K. Kavitha, ―LowPower Dual Dynamic Node Pulsed Hybrid Flip-Flop
Featuring Efficient EmbeddedLogic’’, IEEE Tans. VLSI,
Syst., vol.21, no.9, pp. 12-29, Sep. 2013.
[2]. N. Nedovic and V. G. Oklobdzija, ―Hybrid latch flip-flop
withimproved power efficiency,‖ in Proc. Symp. Integr.
CircuitsSyst. Design ,2000, pp. 211–215.
ISSN: 2231-5381
POWER
DISSIPATION
59.615NW
36.965NW
30.147NW
[3]. B.-S. Kong, S.-S. Kim, and Y.-H. Jun, ―Conditional-capture
flip-flop for statistical power reduction,‖ IEEE J. Solid-State
Circuits , vol. 36,no. 8, pp. 1263–1271, Aug. 2001.
[4]. J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital
Integrated Circuits: A Design Perspective , 2nd ed.
Englewood Cliffs, NJ: Prentice-Hall, 2003
[5]. P. Zhao, T. K. Darwish, and M. A. Bayoumi, ―Highperformance and low-power conditional discharge flip-flop,‖
IEEE Trans. Very LargeScaleIntegr. (VLSI) Syst. , vol. 12,
no. 5, pp. 477–484, May 2004.
[6]. Hirata, K. Nakanishi, M. Nozoe, and A. Miyoshi, ―The cross
charge-control flip-flop: A low-power and high-speed flipflop suitable formobile application SoCs,‖ in Proc. Symp.
VLSI Circuits Dig. Tech. Papers, Jun. 2005, pp. 306–307.
[7]. C. K. Teh, M. Hamada, T. Fujita, H. Hara, N. Ikumi, and
Y.Oowaki, ―Conditional data mapping flip-flops for lowpower and highperformancesystems,‖ IEEE Trans. Very
Large Scale Integr. (VLSI) Syst.,vol. 14, no. 12, pp. 1379–
1383, Dec. 2006.
[8]. O. Sarbishei and M. Maymandi-Nejad, ―Power-delay
efficient overlap-based charge-sharing free pseudo-dynamic
flip-flops,‖ in Proc.IEEE Int. Symp. Circuits Syst., May
2007, pp. 637–640
http://www.ijettjournal.org
Page 238
International Journal of Engineering Trends and Technology (IJETT) – Volume 29 Number 5 - November 2015
[9]. H. Mahmoodi, V. Tirumalashetty, M. Cooke, and K. Roy,
―Ultra low-power clocking scheme using energy recovery
and clock gating,‖IEEE Trans. Very Large Scale Integr.
(VLSI) Syst., vol. 17, no. 1, pp. 33–44, Jan. 2009.
[10]. O. Sarbishei and M. Maymandi-Nejad, ―A novel overlapbased logic cell: An efficient implementation of flip–flops
with embedded logic,‖IEEE Trans. Very Large Scale Integr.
(VLSI) Syst. vol. 18, no. 2, pp. 222–231, Feb. 2010.
pursuing Ph.D in the Department of ECE,
J.N.T.University, Kakinda. She presented many
papers in variousnational and international
conferences and journals of repute. Her research
interests include Applied Electromagnetics, Array
Antennas and EMI/EMC. Ms. D.Ramadevi is the life
member of IETE,SEMCE,ISOI.
Miss. S. SHABEENA received
B.Tech. degree from Avanthi
Institute
of
Engineering
and
Technology Narsipatnam in the year
2013and presently pursuing M.Tech
degree in VLSI in MVGR College of
Engineering, Vizianagaram.
Dr. R. RAMANA REDDY did
AMIE in ECE from The
Institution of Engineers (India) in
2000, M.Tech (I&CS) from JNTU
College of Engineering, Kakinada
in 2002, MBA (HRM &
Marketing)
from
Andhra
University in 2007 and Ph.D in Antennas in 2008
from Andhra University. He is presently working as
Professor & Head, Dept. of ECE in MVGR College
of Engineering, Vizianagaram. Coordinator, Center
of Excellence – Embedded Systems, Head, National
Instruments Lab VIEW academy established in
Department of ECE, MVGR College of Engineering.
Convener of several national level conferences and
workshops.Published about 50 technical papers in
National / International Journals Conferences. He is a
member of IETE, IEEE, ISTE, SEMCE (I), IE, and
ISOI. His research interests include Phased Array
Antennas, Slotted Waveguide Junctions, EMI/EMC,
VLSI and Embedded Systems.
Ms.D.RAMADEVI did her B.E in
Electronics and Communication
Engineering
from
Andhra
University in 1999. In 2006, she
obtained
her
M.Tech
(Instrumentation
and
control
systems) degree from J.N.T.
University. She is having 15 years of teaching
experience and presently she is working as an
Associate Professor in Department of ECE, MVGR
College of Engineering, Vizianagaram. She is also
ISSN: 2231-5381
http://www.ijettjournal.org
Page 239