International Journal of Engineering Trends and Technology (IJETT) – Volume 24 Number 3- June 2015
Efficient CMOS Design of Reversible Shift Register using PTL Logic
Anju Devi1, Dr. Rajesh Mehra2
M.E. Student1, Associate Professor ECE2
NITTTR
Chandigarh, India
Abstract— The reversible logic is used due to its low power
consumption as compare to the irreversible logic. The PTL logic is
used in this design implementation because PTL technique allows
reducing the power consumption, area. In this paper PTL technique
is used to design the 4 bit reversible shift register. The area is
reduced in reversible shift register designed by using Fredkin and
Feynman gates as compare to reversible shift register designed by
using the Sayem gates. The power variation with supply voltage and
temperature can be performed on BSIM-4. Result shows that the area
consumed by proposed reversible shift register is 2996.3µm2. At 1.4V
of input supply voltage the proposed shift register has shown an
improvemement of 92.4% in power. Simulations are run on
Microwind3.1 design tool and the schematic diagrams are drawn in
DSCH2 using 180nm technology file.
Keywords—PTL, Reversible logic, Microwind, Low power VLSI,
CMOS design.
I. INTRODUCTION
Shift registers are a type of sequential logic circuit, mainly for
storage of digital data. They are a group of flip-flops
connected in a chain so that the output from one flip-flop
becomes the input of the next flip-flop. Most of the registers
possess no characteristic internal sequence of states. All flipflops are driven by a common clock, and all are set or reset
simultaneously. Shift registers are the cascade of flip flops
used to shift and store the input data. The input is loaded
either in serial form or in parallel form and output is appear
either in serial form or parallel form. Shift registers can
perform shifting in both directions either from left to right or
right to left. Shift registers are not only used to store data, but
also used for the serial and parallel data transformation, data
computing, signal transmission delays and data processing so
the study of the shift register are of great significance. In
digital logic circuit, a one-bit shift register can be built using
D flip-flop. “D” is the input data and clock is the enable signal
of D flip-flop. After one clock cycle, the value of D is shifted
out
as
output
Q.
Shift
registers
can
have
both parallel and serial inputs and outputs. These are often
configured as 'serial-in, parallel-out' (SIPO) or as 'parallel-in,
serial-out' (PISO). Shift registers are relatively important
timing circuits, commonly used in digital circuits. Shift
registers are not only used to store information, but also used
for the serial and parallel data transformation, signal
transmission delays, data processing and data computing, so
the study of the shift register are of great significance [1]. The
conventional, complementary metal oxide semiconductor
circuits use direct current power supply, the energy always
converts from electrical energy into heat in an irreversible
form, resulting in non-energy recovery. Although reducing
node capacitances, supply voltage, and switching activity are
ISSN: 2231-5381
used to reduce power consumption, energy saving is limited
[2]. Power consumption of CMOS consists of dynamic and
static components. Dynamic power is use up when transistors
are switching and static power is consumed regardless of
transistor switching [3]. In one complete cycle of CMOS
logic, current go from VDD to the load capacitance to charge
it and then go from the charged load capacitance to ground
during discharge. Due to this one complete charge/discharge
cycle, a total of Q=CLVDD thus transferred from VDD to
ground. Multiply by the switching frequency on the load
capacitances to get the current used, and multiply by voltage
[4]. Despite many advantages, CMOS suffers from more
power dissipation, increased area and correspondingly
increased capacitance and delay, as the logic gates become
more complex [5]. All NMOS and PMOS transistors used in
this circuit have the same W/L ratio [6].
In irreversible logic some information about the inputs is lost
every time a logic operation is performed. Thus we cannot
deduce the input from knowing the output alone. Energy loss
is of great significance issue in modern VLSI designs. Though
the improvement in higher-level integration and the
development of new fabrication processes have significantly
reduced the heat loss over the last decades, physical limit
exists in the reduction of heat. According to R. Landauer’s
research in the 1960s, the amount of energy dissipated for
every irreversible bit operation is given by KTln2, K is the
Boltzmann’s constant having the value 1.3807X10 -23 JK-1. T is
the operating temperature. At room temperature the
dissipating heat is around 2.8X10-21 J, which is small but nonnegligible. Reversible logic does not erase the information,
dissipate zero heat. For a given system to be reversible, it has
to be able to operate in backward direction. This ability allows
us to reproduce input from only knowing the output. The C.
H. Bennett in 1973 concluded that no energy would dissipate
from a system as long as the system was able to return to its
initial state of its final state. Reversible logic is an emerging
technology and become very popular due to its low power
consumption feature but the main drawback is that it require
more hardware, so our main objective in this paper is to
reduce the number of transistors and area in the reversible Dflip flop and reversible shift register. Reversible logic is the
logic supporting the process of running the system in the
backward direction. These circuits are used where low power
consumption is desirable. The applications of reversible logic
circuits are optical computing, nanotechnology, quantum
computing, reversible memory circuits and ultra low power
CMOS design [7].
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International Journal of Engineering Trends and Technology (IJETT) – Volume 24 Number 3- June 2015
II. BASIC IDEAS OF REVERSIBLE LOGIC
In this section some commonly used reversible logic gates and
their quantum cost is discussed.
The figure 4 shows the transistor implementation of the
Fredkin gate. The 4 transistors are required to implements the
Fredkin gate.
1.) Feynman gate (FG)
The Feynman gate is also called controlled NOT gate or the
quantum XOR gate due to its popularity in the quantum
computing. The Feynman gate is a reversible (2X2) gate,
because it has 2 inputs and 2 outputs.
A
X=A
Feynman
Gate
B
Y=A XOR B
Figure 1. Feynman Gate (2 X 2)
Here in the figure 1 input A serves as a control input. If A=0
then Y is the duplicate copy of input. If A=1 then o/p Y is the
inverse of B. For this reason, the Feynman gate is also called
the controlled NOT (CNOT) gate. The quantum cost of every
2 X 2 gate is the same and the cost is unity.
Figure 4. Transistor realization of Fredkin Gate
3.) Sayem Gate (SG)
The Sayem gate is the 4X4 gate that means this gate has 4
inputs and 4 outputs. The 4 inputs are A, B, C, D and 4
outputs are W, X, Y, Z.
A
B
C
D
Sayem
Gate
W=A
X=ĀB XOR AC
Y= ĀB XOR AC XOR D
Z= ĀC XOR AB XOR D
Figure 5. Sayem gate (4 X 4)
The output W is the copy of the input A. The input A is the
control input of the Sayem gate [10].
Figure 2. Proposed Transistor realization of Feynman Gate
The figure 2 shows the proposed transistor implantation of
Feynman gate using only six transistors. The logic style used
for the realization is the pass transistor logic.
2.) Fredkin Gate (FRG)
The Fredkin gate is 3 X 3 logic gate because it has 3 inputs
and 3 outputs. The 3 inputs are A, B, C and the 3 outputs are
X, Y, Z. This gate is most widely used reversible logic gate. In
the Fredkin gate X=A, Y=ĀC + AB and Z=ĀB + AC. The
output X is the copy of input A.
A
B
C
Fredkin
Gate
X=A
Y= ĀC + AB
Z=ĀB + AC
Figure 3. Fredkin gate (3 X 3)
Figure 6. Transistor realization of Sayem gate
The Fredkin gate shown in the figure 3 along with Feynman
gate is used to construct reversible D flip-flop [8]. The
quantum cost of FG gates is 5.
The Fredkin gate uses A as a control input. If A = 0, then the
outputs are simply duplicates of the inputs, otherwise if A= 1,
then the two input lines (B and C) are interchanged[9].
ISSN: 2231-5381
The figure 6 shows the transistor realization of the Sayem
gate. The Sayem gate use 32 transistors for logic realization.
4.) Toffoli Gate
The toffoli gate is the 3 X 3 reversible gate. Figure 7 shows
the of Toffoli gate. In the proposed implementation, the
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International Journal of Engineering Trends and Technology (IJETT) – Volume 24 Number 3- June 2015
Y=Q
The characteristic equation of the D flip flop is Q+ =
D.CLK+Q.CLK, where Q+ is the next state of the D flipflop[14]. The reversible D flip flop is implemented by using
the Fredkin gate and Feynman gate. The Fredkin gate in the
figure 9 has three inputs CLK, D and the third input is the
feedback from the output of the Feynman gate. The first
output of Fredkin gate is the CLK output. The second output
of the Fredkin gate is the garbage output, which is not used.
The third output of the Fredkin gate is fed to the first input of
the Feynman gate. The second input of the Feynman gate is
always 0.
Z=(P.Q) XOR R
CLK
outputs P and Q are directly generated from inputs A and B
respectively by hardwiring. The proposed implementation is
also suitable for both the forward as well as backward
computation. In forward computation X=P, Y=Q, if inputs P
AND Q=0 then Z is the copy of R else the Z is the inverse of
input R. In backward computation, P=X, Q=Y, if X AND Y=0
then R is the copy of Z otherwise R is the inverse of Z[11].
P
X=P
Toffoli
Gate
Q
R
D
Figure 7. Toffoli Gate
CLK
G1
Fredkin
Gate
The figure 8 shows the proposed transistor implementation of
the Toffoli gate. The gate consists of six transistors.
0
Feynman
Gate
Q
Q
Figure 9. Reversible D Flip-Flop
The first output of Feynman gate is the Q and the second
output is connected to the third input of the Fredkin gate.
Figure 10. Reversible D flip flop using PTL logic
Fig. 8 Proposed Transistor realization of Toffoli Gate
The Toffoli gate is the 3 X 3 gate consists of three inputs i.e.
P, Q and R and the three outputs are X,Y and Z.
III. REVERSIBLE D-FLIP-FLOP SIMULATION
ANALYSIS
A flip-flop or latch is a circuit that has 2 stable states and can
be used to store state information. A flip-flop is a bistable
multivibrator. The circuit can be made to change state by
signals applied to 1 or more control inputs and will have 1 or
2 outputs. It is the basic storage element in sequential
logic[12]. Flip-flops and latches are a fundamental building
block of digital electronics systems used in computers,
communications, and many other types of systems. Flip-flops
and latches are used as data storage elements. A flip-flop
stores a single bit (binary digit) of data; one of its two states
represents a "one" and the other represents a "zero". Such data
storage can be used for storage of state, and such a circuit is
described as sequential logic[13].
ISSN: 2231-5381
The figure 10 shows the schematic diagram of reversible Dflip flop which is drawn in the DSCH2 design tool. The
verilog file is also generated by this schematic in the DSCH2
design tool. The figure shows the design of reversible D flipflop which is designed by using the FG & FRG gates.
Figure 11. Timing diagram of Reversible D flip flop
The figure 11 shows the timing diagram of reversible D flipflop which is designed by PTL logic.
The figure 12 shows the layout of the proposed reversible Dflip flop which is generated by the verilog file. This layout is
generated in Microwind3 back end design tool at 180nm.
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International Journal of Engineering Trends and Technology (IJETT) – Volume 24 Number 3- June 2015
1.3
0.269
0.006
1.5
0.352
0.009
1.7
0.438
0.022
1.9
0.526
0.049
The figure 14 shows the graphical representation of the power
variation with respect to supply votage. This figure shows the
the power variation with supply voltage is less in proposed
design as compared to the existing design.
Figure 12. Layout of reversible D flip-flop by PTL logic
The analog analysis of the given layout is also performed in
Microwind back end design tool to find the different
parameters like power variation with time etc. The figure 13
shows the analog simulations results of the proposed
reversible D- flip flop.
Figure 14. Power Variation with Supply Voltage
The table II shows the power variation with respect to
temperature of proposed reversible D-flip flop which is
observed in the Microwind3.
Table II. Power Variation with Temperature
Figure 13. Analog simulation of proposed reversible D-FF
t°
D-FF using Sayem
Gate by CMOS[7]
Proposed D-FF using
FRG & FG Gate by
PTL
20
0.575
0.069
40
0.563
0.065
60
0.553
0.062
80
0.545
0.059
100
0.539
0.055
120
0.537
0.052
The table I shows the power variation with respect to supply
voltage of proposed reversible D-flip flop which is observed
in the Microwind3.
Table I. Power Variation with Supply Voltage
Vdd(V)
Power(mWatt)
Reversible D-FF by
Sayem Gate [7]
Proposed Reversible DFF using FRG & FG
Gate by PTL
0.1
0
0
0.3
0
0
0.5
0.013
0.006
0.7
0.09
0.007
0.9
0.162
0.006
1.1
0.223
0.005
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power(mWatt)
(temp. coef.)TC=0.0 mV/°C
The figure 15 shows the graphical representation of the power
variation with respect to Temperature. This figure shows that
the power variation with temperature is less in proposed
design as compared to the existing design.
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International Journal of Engineering Trends and Technology (IJETT) – Volume 24 Number 3- June 2015
CLK
CLK
Reversible
D
Flip-Flop
Reversible
D
Flip-Flop
Reversible
D
Flip-Flop
Reversible
D
Flip-Flop
D
D
D
D
Serial
Serial
Q
Q
Q
Q
I/P
O/P
Figure 16. Reversible SISO shift register (4 bit)
This design consists of 4 Fredkin gates and 4 Feynman gates.
The data output of one flip-flop is the data input of next flipflop.
Figure 15. Power Variation with Temperature
The table III shows that the reversible D flip-flop designed by
PTL technique consume less area as compared to the
reversible D flip-flop designed by sayem gate.
Table III Comparison of reversible D-FF using Sayem gate
& reversible D-FF using FRG and FG gate
Parameter
D FF by Sayem
Gate [7]
Proposed D FF by FRG
and FG gates using PTL
Figure 17. Proposed reversible SISO shift register (4 bit)
Area
4166.3µm2
559.7µm2
Power
0.571mW
0.067mW
The figure 17 shows the schematic representation of the 4-bit
reversible shift register in the DSCH design tool. The shift
register is drawn by using PTL logic.The proposed design
consists of 40 transistors.
In this paper, we use the reversible D flip-flop designed by
using FRG and FG gates to construct the 4-bit reversible shift
register which is area efficient as compared to the reversible
shift register designed by using Sayem gate.
IV. DESIGN OF REVERSIBLE SHIFT REGISTER
The shift register is one of the most extensively used
functional devices in digital systems. A shift register consists
of an array of flip-flops connected together so that information
bits can be shifted one position to either right or left
depending on the design of the device. The shift registers are
also used as a buffer circuit. The reversible shift registers are
used to construct the Quantum computers. The serial in the
serial output shift register (SISO) is the simplest shift register.
The 4 bit reversible shift registers is implemented by using 4
reversible D flip-flops which is designed by using the Fredkin
gate and Feynman gate. The area consumed by this shift
register is less as compare to the reversible shift register
designed by the reversible D flip-flops using Sayem gate. The
serial input is entered in the first flip-flop and serial output
appears at the last flip flop. This shift register is called serial
in serial out shift register because the input is entered in serial
manner and output is also appears in serial form.
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Figure 18. Timing diagram of reversible shift register
The figure 18 shows the timing diagram of reversible shift
register by PTL logic.
The figure 19 shows the layout of the reversible shift register.
This layout is observed in the Microwind software to calculate
the overall area and power consumed by this proposed shift
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International Journal of Engineering Trends and Technology (IJETT) – Volume 24 Number 3- June 2015
register. The layout of the proposed design is used to find the
area of the reversible shift register. This facility of area and
number of transistor calculation is provided by the
Microwind3 back end design tool.
1.2
0.991
0.062
1.4
1.307
0.099
1.6
1.725
0.157
1.8
2.253
0.268
The figure 21 shows the graphical representation of the power
variation with respect to supply votage of the proposed
reversible shift register at 180nm technology.
Figure 19. Layout of reversible shift register
The figure 20 shows the analog simulation of the proposed
reversible shift register in Microwind3 at 180nm technology.
Figure 21. Power Variation with Supply voltage
This figure 21 shows the the power variation with supply
voltage is less in proposed design as compared to the existing
design.
The table V shows the power variation with respect to the
Temperature of proposed reversible shift register which is
observed in the Microwind3 at 180nm technology.
Table V. Power Variation with Temperature
Figure 20. Analog simulation of proposed reversible SR
The table IV shows the power variation with respect to supply
voltage of proposed reversible shift register which is observed
in the Microwind3 at 180nm technology. The analog
simulation is used to calculate the delay of the proposed
reversible shift register circuit.
Table IV. Power Variation with Supply voltage
Vdd(V)
Power(mWatt)
Reversible SR by
Proposed Reversible SR
Sayem Gate using
by FRG & FG Gate
CMOS[7]
using PTL
0
0
0.2
0.4
0.007
0.053
0.6
0.218
0.054
0.8
0.473
0.053
1
0.728
0.055
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t°
Power(mW)
SR by Sayem Gate
using CMOS [7]
Proposed SR by FRG &
FG Gate using PTL
20
2.922
0.415
40
2.777
0.399
60
2.667
0.384
80
2.589
0.369
100
2.517
0.355
120
2.453
0.342
(temp. coef.)TC=0.0 mV/°C
The figure 22 shows the graphical representation of the power
variation with respect to Temperature of the proposed
reversible shift register at 180nm technology.
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International Journal of Engineering Trends and Technology (IJETT) – Volume 24 Number 3- June 2015
REFERENCES
Figure 22. Power Variation with Temperature
This figure shows the the power variation with Temperature is
less in proposed design as compared to the existing design.
Table VI. Comparison of reversible D-FF using Sayem
gate & reversible D-FF using FRG and FG gate
Parameter
Reversible SR by
Sayem gate using
CMOS [7]
Proposed Reversible
SR by FRG ang FG
gate using PTL
Area
19523.9µm2
2996.3µm2
Power
2.838 mW
0.409mW
The table VI shows that the reversible shift register designed
by PTL technique consume less area and power as compared
to the reversible shift register designed by Sayem gate. The
proposed reversible shift register designed by using the FRG
and FG gate consumes 84.6% less area as compare to
reversible shift register designed by using the Sayem gate. The
power consumed by the proposed reversible shift register is
85.5% less as comare to existing reversible shift register
design. The results in the table VI shows that the proposed
design is an efficient design.
VI. CONCLUSION
This paper proposes the design of reversible 4-bit shift register
by using reversible D flip-flop designed by using PTL
technique. The proposed work is used to reduce the area as
compare to the reversible shift registers designed by other
techniques like CMOS. The proposed reversible D-FF use the
area 559.7µm2 which is less than the existing techniques of
reversible D-flip flop. The simulation is performed in BSIM4
in Microwind back end design tool. The proposed 4-bit
reversible shift register use only 40 transistor which are less
than the existing results. The proposed design has the
applications to build reversible memory circuits. This paper
forms an important step in the building of complex reversible
sequential circuits for building quantum computers.
ISSN: 2231-5381
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AUTHORS BIOGRAPHY
Anju Devi is currently pursuing Regular M.E. from National
Institute of Technical Teachers Training and Research,
Chandigarh Sector 26. She has completed her B.Tech from
M.G. Institute of Engineering and Technology Badhoo,
Mandi.
Dr. Rajesh Mehra is currently Associate Professor at
National Institute of Technical Teachers’ Training &
Research, Chandigarh, India. He has completed his M.E. from
NITTTR, Chandigarh, India and B. Tech. from NIT,
Jalandhar, India. Mr. Mehra has more than 16 years of
academic experience. He has authored more than 100 research
papers including more than 50 in Journals. Mr. Mehra’s
interest areas are VLSI Design, Embedded System Design,
and Advanced DSP.
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