International Journal of Engineering Trends and Technology (IJETT) – Volume 23 Number 8- May 2015
Design and Implementation of less quiescent
current, less dropout LDO Regulator in 90nm
Technology
Madhukumar A S#1, M.Nagabhushan#2
#1
M.Tech student, Dept. of ECE. M.S.R.I.T,
Bangalore, INDIA
#2
Asst. Professor, Dept. of ECE., M.S.R.I.T,
Bangalore, INDIA
Abstract – There is a great demand for battery-powered
portable devices now-a-days. For reducing the standby power
and maximizing the battery runtime in these devices, power
management is compulsory. Here one such power
management module called low-dropout (LDO) regulator is
proposed and designed in 90nm technology. It converts an
input of 1V to an output of 0.5-0.932V. A two stage
operational amplifier is used as an error amplifier (EA)
which is having high gain and high output swing in order to
reduce the size of power MOS transistor. The reference
voltage of 0.5V for the LDO is derived from a piecewise
curvature compensated BGR in order to have LDO regulated
output invariant to temperature. These advantages permit the
proposed LDO regulator to operate over a wide range of
operating conditions by achieving current efficiency about
99.99%, 68mV dropout voltage, 0.02µA quiescent current
with a load regulation of 0.17mV/mA and line regulation of
5.41mV/V at 0.932V output.
Keywords– Low-dropout (LDO) regulator, less quiescent
current, LDO tuning range, load regulation, Proportional to
absolute temperature (PTAT),Complimentary to absolute
temperature ( CTAT).
I. INTRODUCTION
Now-a-days battery powered devices such as mobile phones,
laptops, PDA’s etc are quite demanding in the current market
trend and also these are likely to be the most important
consumer products. The one critical parameter that needs to be
considered in working of these devices is the battery power.
Once the battery power starts draining and the efficiency of
these devices reduces with respect to the time. Hence power
management needs to be done for these battery equipped
devices. The one such power management module
ISSN: 2231-5381
we can think of is regulator. Regulator is of two types namely
linear regulator [1] and switching regulator [10]. In this paper
one example of linear regulator i.e. low-dropout (LDO)
regulator is designed and implemented in 90nm technology.
A low-dropout regulator is a DC linear voltage regulator
which can operate with a very small input–output differential
voltage. For a good LDO it must have high tuning range, high
current efficiency, low quiescent current I Q and very less
dropout voltage especially for sub 1-V operation.
A number of previous papers focused on reducing the dropout
voltage and reducing the quiescent current [1] – [6] of LDO
regulator. The design in [1] consumes a quiescent current of
about 60µA which is really a high value. If quiescent current
increases means the current efficiency decreases which is a
disadvantage. Hence in this paper the quiescent current
reduces to a very small value. Also the dropout voltage in
design [1] is 150mV which is a large value especially in sub 1V operation. Hence in this paper the dropout voltage also
reduced to a small value.
II. IMPROVED PERFORMANCE PARAMETERS
A LDO regulator basically consists of mainly four blocks
namely an error amplifier (EA), a power MOS transistor (M P),
a feedback network and a bandgap reference circuit (BGR) as
shown in Fig. 1. At the output side LDO regulator consists of
load capacitor (CL) and resistor (RSER) in order to compensate
for the stability of the circuit. Some of the improved
performance parameters are discussed in the following
sections.
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International Journal of Engineering Trends and Technology (IJETT) – Volume 23 Number 8- May 2015
D. Small area of LDO circuit.
The power MOS transistor used here in the LDO loop
consumes more area of the total overall consumed area by the
LDO circuit. Hence the aspect ratio of this power MOS
transistor must be reduced. This can be done by increasing the
swing and gain of the error amplifier (EA).
III. LDO REGULATOR CIRCUIT DESIGNING
LDO regulator consists of mainly four blocks and designing
of all four blocks are explained in the following sections.
Fig.1. Block diagram of proposed LDO
A. ERROR AMPLIFIER
The error amplifier is a two stage transconductance amplifier
as shown in Fig.2.
A. High Power Supply Rejection.
In order for LDO to give a constant accurate output voltage
especially in sub-1 V operation noise suppression must be
done. In order to suppress the noise here in the proposed LDO
architecture the error amplifier uses two stages. The first stage
of EA is used to attenuate the power noise and the second stage
of EA rejects the common mode noise at its inputs. And also
power noise cancellation at gate of power MOS increases PSR.
B. High Stability by LDO compensation.
Here the power MOS MP contributes a non-dominant pole at a
low frequency. In order to compensate for stability i.e. to
cancel this non-dominant pole a large equivalent series
resistance of CL (RSER) is required to produce a low frequency
zero.
C. Very less dropout voltage and Quiescent current (IQ).
The dropout voltage of LDO is the difference between the input
and the output voltage. Quiescent current is the difference
between the input and the output current. For a good LDO both
these should be very less. The dropout voltage is directly
proportional to the maximum load current of the circuit. Hence
by choosing the maximum load current as low as possible we
can achieve very less dropout voltage. If dropout voltage
decreases means the Quiescent current also decreases to very
low value in the circuit.
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Fig.2. Two stage Error amplifier (EA)
The first stage is the differential amplifier and second stage is
the common source amplifier. Here in order to achieve the
phase margin of amplifier greater than 60 0 the compensation
capacitor is selected as 800 fF. The transistors M1 and M2 are
matched transistors and are designed by first selecting the
transconductance of M1 and M2 as 130µ in order to have high
gain bandwidth product. The transistors M3 and M4 are
matched transistors and are designed using the high input
common mode range parameter. By knowing the bias current
for the circuit I5 transistors M5- M7 are designed.
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International Journal of Engineering Trends and Technology (IJETT) – Volume 23 Number 8- May 2015
The gain and swing of the amplifier must be more in order to
reduce the aspect ratio requirement of the power MOS
transistor. The gain of the first stage and second stage is given
by equation (1) and equation (2) respectively. The total gain is
the sum of these gains in dB i.e. in equation (3).
(1)
(2)
(3)
B. POWER MOS TRANSISTOR.
Power MOSFET used here is the PMOS with high aspect ratio.
The value or the aspect ratio of the power MOSFET is based on
the dropout voltage and the maximum load current required. To
have very less dropout voltage, we need to use very less load
current. The relationship between dropout voltage and
maximum load current is given in equation (4). From this
relation the power MOS is designed.
Fig.3. Piecewise curvature compensated BGR
(4)
C. PIECE WISE CURVATURE CORRECTED BGR.
Fig.4. Reference curves for first order and curvature compensated BGR
The proposed piecewise corrected BGR is shown in Fig.3. It
consists of consists of a startup circuit, a conventional firstorder BGR and the proposed curvature-corrected current
generator. We know that the first order BGR generate a
reference with slightly negative temperature coefficient as is
given in Fig.4. The curvature-corrected current generator
provides a piecewise nonlinear current given in equation (5) to
correct the nonlinear temperature dependence to achieve lower
negative TC as shown in Fig.4.
Proposed architecture uses two NMOS differential input opamps, of which one is used to generate PTAT and second opamp is used to generate a CTAT. Due to the positive TC of
R5/R2, a PTAT voltage is achieved at the gate-source voltage
of transistor M12. This voltage is used to overcome the
negative TC and tries to move the reference curve upwards
with respect to temperature. The reference voltage generated
by this piecewise curvature compensated BGR is 0.5 V which
is used by the LDO regulator circuit as a reference voltage.
(5)
D. FEEDBACK NETWORK
(6)
The feedback network consists of two resistors R1 and R2.
These resistors are designed by taking the regulated output
voltage required and the reference voltage from bandgap
reference circuit as given in equation (7).
(7)
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International Journal of Engineering Trends and Technology (IJETT) – Volume 23 Number 8- May 2015
IV. IMPLEMENTATION, RESULTS & ANALYSIS
The complete schematic circuit of the two stage error amplifier
is created in virtuoso schematic editor and is as shown in Fig.5.
The functionality is shown Fig.6.when the input is given to
inverting terminal of EA.
Fig.8. Piecewise curvature compensated BGR
Fig.5. Two stage error amplifier (EA)
Fig.9. BGR output curves – VREF, CTAT and PTAT
Fig.6. Inverting output
The complete LDO regulator circuit is created in cadence
virtuoso schematic editor and is shown in Fig.10.
The gain of the EA obtained is ~50dB i.e. 48.929dB and the
same gain plot is shown in Fig.7.
Fig.10. Complete LDO regulator circuit
Fig.7. EA gain plot
The piecewise curvature compensated BGR is shown in Fig.8.
and the outputs obtained with respect to the temperature is
shown in Fig.9. and the reference voltage is 500mV.
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The LDO regulator test circuit with load resistance RL for
plotting the load regulation is shown in Fig.11.
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International Journal of Engineering Trends and Technology (IJETT) – Volume 23 Number 8- May 2015
Fig.11. LDO regulator test circuit with RL
This LDO can be tuned in the range from 0.5 V to 0.932V in
increments of 10mV, 50mV and 100mV. This can be done by
changing the values of R1 and R2 resistors.
Fig.13. Variation of Vout vs. Vin at 500mV regulated voltage
Table 1.1. Line regulation at 500mV regulated voltage
Case (1): When LDO is tuned to give a regulated output
voltage of 500mV.
The LDO can be tuned to 500mV by using resistors R1 and R2
at the output side to 1Ω and 500Ω respectively. And by varying
load resistor RL we can see the load regulation of LDO. Fig.12.
shows the outputs from internal blocks when LDO tuned at
500mV.
Fig.12. LDO outputs when it is tuned to 500mV
We can infer from the above figure that the output from Error
amplifier is 752.724mV in order to keep power MOSFET in
saturation region so that the output will be a regulated constant
voltage i.e. 500mV. The variation of output regulated voltage
with respect to input voltage is called line regulation and is
plotted in Fig.13.for regulated voltage of 500mV. The
corresponding values of output versus input are tabulated as
shown in the table 1.1.
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Vin(mV)
Vout(mV)
518.56
500.26
560.045
500.702
606.364
500.919
668.0
501.162
729.714
501.414
852.4
501.922
911.2
502.18
968.571
502.441
Case (2): When LDO is tuned to give a regulated output
voltage of 932mV.
The LDO can be tuned to 932mV by using resistors R1 and
R2 at the output side to 430Ω and 500Ω respectively. Fig.14.
shows the outputs from each and every block when LDO
tuned at 932mV. The line regulation and is plotted in Fig.15.
for regulated voltage of 932mV. The corresponding values of
output versus input are tabulated as shown in the below
table.1.2.
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International Journal of Engineering Trends and Technology (IJETT) – Volume 23 Number 8- May 2015
Fig.14. . LDO outputs when it is tuned to 932mV
Fig.16. Load Regulation at 932mV output voltage
We can infer from the above graph that the variation of output
voltage is very less with respect to the load current i.e. load
resistor RL which is a good characteristic of LDO.
Fig.15. Variation of Vout vs. Vin at 932mV regulated voltage
Finally all the parameters of LDO regulator are calculated and
tabulated in the table 1.3 and in the same table all the
parameters of this work are compared with the recent previous
work of [1]. In this work the quiescent current and dropout
voltage are decreased to a very less value. The current
efficiency also increased and load regulation is decreased as
well which is a good characteristic.
Table 1.2. Line regulation at 932mV regulated voltage
Table 1.3. Comparison of LDO Parameters
Vin(mV)
Vout(mV)
Parameters
Ref1 [2014]
This work
949.283
932.058
Technology
90nm
90nm
1.00376V
932.835
Vin
1V
1V
1.05025V
933.315
LDO Tuning Range
0.5 – 0.85
0.5 – 0.932
1.116V
933.875
In Increments of
-
10mV,50mV,100mV
1.17247V
934.3
Dropout Voltage
150mV
68mV
1.19346V
934.725
Max Load current, Imax
100mA
1mA
Quiescent Current, IQ
60µA
0.02µA
Current Efficiency
99.94%
99.99%
Efficiency of LDO
84.94%
93.19%
Line Regulation
-
5.41mV/V
Load Regulation
0.28mV/mA @ Vout
=0.85V
0.17mV/mA @ Vout
= 0.932V
After this 932mV regulated output voltage if we want to tune
further means it’s not possible because the power MOS
transistor enters into linear region and hence we cannot expect
a regulated voltage at the output side and hence the dropout
voltage is 68mV. Load regulation is a measure of the circuit’s
ability to maintain the specified output voltage under varying
load conditions. The plot of load regulation i.e. variation of
output voltage with respect to load resistor is shown in Fig.16.
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International Journal of Engineering Trends and Technology (IJETT) – Volume 23 Number 8- May 2015
V. CONCLUSION
The paper describes a LDO which is working with very less
dropout voltage of about 68mV and very less quiescent current
of 0.02 µA which are the characteristics of good LDO. The
LDO output is invariable to temperature since reference voltage
[7] P. Pournima,” Piecewise Curvature-Corrected Bandgap Reference in 90
nm CMOS”, IJSTE - International Journal of Science Technology &
Engineering ,Volume 1,Issue 2,August 2014.
[8] J. Hu, B. Hu, Y. Fan, and M. Ismail, “A 500 nA quiescent, 100 mA
maximum load CMOS low-dropout regulator,” in Proc. IEEE Int. Conf.
Electron. Circuits Syst., Dec. 2011, pp. 386–389.
for regulator is derived from BGR circuit which also again
[9] Phillip. E. Allen, Douglas. R. Holeberg, “CMOS Analog Circuit Design”,
Second Edition, Qxford University Press 2002.
good characteristic. The designed LDO can be used to provide
[10] http://educypedia.karadimov.info/library/f5.pdf -switching regulators.
stable voltages in the range from 0.5V to 0.932V and this range
of voltages can be used as stabilized source voltages for
devices working in sub 1 V operation.
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