International Journal of Engineering Trends and Technology (IJETT) – Volume 9 Number 14 - Mar 2014
An Area and Power Efficient Glitch-less Digitally
Controlled Delay Lines
[1]
Preethi.D
[1]
P.G.Scholar, I M.E. VLSI Design, Department of Electronics and Communication Engineering,
Avinashilingam Institute For Home Science And Higher Education For Women-University,
Faculty Of Engineering,
Coimbatore.
Abstract - In the previous NAND gate based delay lines, when the
control input. They are intended to define a time reference for
control code word increased by more than one there were
the movement of data within those systems. For e.g., as in
occurrences of glitches due to momentary changes in the output
PLL system if we require four phase shift of 45o, 90o, 180o
which limited the performance of such delay lines in a number of
and 270o we can use delay lines programmed to each of the
applications. Hence as advancement, the arrangement of the
NAND gates were modified to eliminate the glitches by
introducing a second control bit and driving circuit to provide
delay between the two control bits, to avoid the lack of
synchronization. In order to minimize power and area in the
above circuit MUX based delay line using thermometric code is
proposed. This includes only one control bit but also eliminates
above degrees separately using the delay elements.
Various delay elements are used to improve the
performance of delay lines which includes multiplexers,
inverters and NAND [4], [6], [7] gates. A delay chain is
constructed using delay cells. In case of multiplexers the
glitches without driving circuits. These delay lines are applied in
tradeoff between the minimum delay and the required delay
the fields of DLL, PLL and UWB.
will vary thereby reducing its efficiency in communicating the
essential information. Since the tree based multiplexer
Index Terms: DLL, Driving Circuits, PLL, Thermometric Code,
UWB.
topology was used, as the number of cells increases the delay
associated with it will also increase drastically. In addition to
it the layout complexity and difficulty in fabrication adds to
I. INTRODUCTION
the above drawback.
DCDLs are used in number of applications such as
phase locked loops and delay locked loops. They are used to
mainly process the clock signals. These lines produce a
programmable delay to the output with respect to the input
and also adjust the relative difference between the two signals
to produce the reliable data transfer. It is also finds its
applications in digital- to-analog converter where time domain
resolution [3] is given more importance than the voltage
resolution. A digital delay line, this includes a plurality of
The inverters when used as a delay element in
combination with the multiplexers or NAND gates there will
definitely be a delay and resolution mismatch which adds on
to more delay than required. The use of NAND gates
effectively reduces the tradeoff problem and also has regular
architecture. This provides very good linearity and resolution
as compared with the above delay elements. Hence the further
implementations were made using NAND gates.
delay elements, arranged in sequence having an associated
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International Journal of Engineering Trends and Technology (IJETT) – Volume 9 Number 14 - Mar 2014
Hazards in any system are obviously an un-desirable
The delay lines could be used in the following areas such as:
effect caused by either a deficiency in the system or external
influences. In digital logic hazards they are of three types
namely static, dynamic and functional. This is however a
temporary problem and the logic will finally come to the
desired function. Despite the logic arriving at the correct
output, it is iterative that hazards be eliminated as they can
have an effect on other systems. Static are those whose one
A. Phase locked loop (PLL):
The PLL consists of a voltage controlled oscillator
whose frequency is equal to the frequency of the PLL
input[7]. The voltage controlling the VCO must
monotonically vary with the frequency of input of
PLL.
input variable changes, the output changes momentarily when
it shouldn't. A dynamic hazard is the possibility of an output
changing more than once as a result of a single input change
and often occurs in larger logic circuits. Function hazards are
non-solvable hazards which occur when more than one input
variable changes at the same time and cannot be logically
eliminated.
The one more advantage of choosing NAND gates is
that the logical effort is small in this case i.e., 4/3 got by the
formula (n+2)/3 where n is the number of inputs. The parallel
Fig 2. Block diagram of PLL
arrangement of PMOS increases the delay linearly.
A PLL consists of a negative feedback loop in which
A general block diagram of a delay line is depicted in
the output of a phase detector is applied to the control input of
the figure 1. Each stage composes of voltage controlled
at VCO. The VCO applies a periodic waveform to the phase
oscillator, delay element in cascade and output buffers.
detector, the phase of which is compared with the phase the
input. Delay lines are introduced in such circuits to introduce
an optimum delay between the input and output.
B. Delay locked loop (DLL):
It is as that of a phase locked loop but the only
difference is the absence of internal VCO. They are used to
change the phase of the signal to enhance clock rise to data
output and are also used in clock recovery[8], [9]. Main
component is the delay chain containing delay elements
connected front to back. The PLL in clock recovery can be
Fig 1. Block Diagram of a Delay Line
replaced by DLL but the only difference being VCO
substituted by a VCDL. The VCDL is adjusted so that the
output is phase locked with the input. The design of daelay
lines of DLL is simpler than PLL.
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The paper is arranged as follows: the existing
method, proposed work, simulation results followed by
conclusion.
II. EXISTING METHODOLOGY
A. NAND based DCDL and Glitching:
The occurrence of glitches may limit the performance
of delay lines in their applications. In the previously proposed
paper NAND gates were used to produce the delay. They have
Fig 3. Block diagram of DLL
assumed one control bit Si in this paper[3].
C. UWB receivers:
When the control code is one: When the control code is one
The frontend of these receivers consists of an antenna
along with the filters in order to remove the interference in
case of FM radios and VHF television signals[12]. The
interleaved ADCs will now sample the received signals. A
S0:0, S1:1 by the condition that S i= 0 for i < c and Si= 1 for i >
c. this condition didn’t cause any glitches.
When the control code increased more than one: When the
control code is increased by more than one there were
single ADC will increase the power consumption, hence
occurrences of glitches. The control bit at this stage would be
parallel interleaved ADCs are used. The digital backend is
S0:0, S1:0, S2=1. Hence there will be momentary change in the
used to perform acquisition and synchronization operation
output causing a glitch to occur. For e.g., If the input is ‘0’ the
followed by tracking and data detection where DCDLs play a
output goes to ‘1’ and then gets back to ‘0’(non-inverting
vital role.
topology). All the lower DE cells are all stuck at ‘1’.
Therefore the intermediate signals contribute to glitch[3], [10].
Fig 5 : Glitching When Control Code Is One [3], [10]
Fig 4. Block diagram of UWB receivers
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International Journal of Engineering Trends and Technology (IJETT) – Volume 9 Number 14 - Mar 2014
In all the figures the yellow colored NAND gates are
This method has produced the output with same
active cells and the red colored NAND gates are dummy cells resolution but has reduced the output jitter by reducing the
used for load balancing. The dashed lines represent the delay glitches. The figure represents the non-inverting topology
path. . The code which is specified in terms of the control where the out is’1’ for the in:’1’. A non inverting delay cell
word is called thermometric code.
topology is placed in front of the inverting topology.
Fig 6 : Glitching When Control Code When Increased More Than One [3], [10]
Fig 8: Glitch Free NAND Operation When Control Code Is Two (NonInverting Topology)[1]
B. Glitch Free NAND Operation
C. Driving Circuit
The next proposed method that follows this is to
eliminate the glitches from the above network. Hence they
have proposed to control bits Si and Ti[1] with the conditions:
The driving circuit [13], [14], [15] used here in order
to provide a delay between the two control bits is a D Flip-flop.
Two D Flip-flops are used and its working as follows:
Si= 0 for i < c and S i= 1 for i > c ; Ti =1 for i≠ c+1 and Tc+1 =0.
In order to provide a delay between these two bits driving
The first D Flip-flop [1] directly gives the input
circuits are designed in this paper. The last lower DE cell is (control bit T) to the output (Ti) whereas the second one will
stuck at ‘1’ for non-inverting topology and stuck at ‘0’ for get another control bit S and introduces some delay by using
inverting topology. When the control code word is two, the three NAND gates and finally gives it at the output (S i). Both
control bits S0-1:0, S2:1, T0-2:1, T3:0[3], [10]. Here as the input is the flip-flops are given the same clock input.
given ‘0’ the output from the inverting topology is ‘1’.
Fig 8: Driving Circuit [1]
Fig 7: Glitch Free NAND Operation When Control Code Is Two (Inverting
Topology) [1]
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III. PROPOSED METHODOLOGY
To reduce the larger area henceforth the larger power
The above table1 explains that whenever the control
consumption the proposed methodology with multiplexers[2]
bit is ‘0’ the data at the input terminal ‘0’ of the MUX will be
using thermometric code[1] is proposed. This method also
sent at the output and if the control bit is ‘1’ the data at the
eliminates the use of driving circuits i.e., the NAND gates
input terminal ‘1’of the MUX will be sent at the output.
followed by D flip-flops[1]. This architecture replaces 6
B. Inverting Topology
NAND gates (4 active + 2 dummy) with just 2
multiplexers+1[2] for providing the turn state. One of the
inputs of the last MUX is kept at ‘0’ ensuring that the n-1th
state will always carry the data present at the input ‘1’ of the
nth bit. As we already discussed in the existing method, both
the inverting and non-inverting topology can be constructed.
The control bits are based on the same thermometric code as
used in existing methodology.
A. Non- Inverting Topology
Fig 10: Inverting Topology Of MUX For Control Code: 1
The table2 explains that whenever the control bit is
‘0’ the data at the input terminal ‘0’ of the MUX will be sent
at the output with an inversion and if the control bit is ‘1’ the
data at the input terminal ‘1’of the MUX will be sent at the
output with an inversion.
Table 2: Operation of MUX in inverting topology
Fig 9: Non-Inverting Topology Of MUX For Control Code: 1
Terminal
Data
0
1
1
1
Control
bit
0
1
MUX
output
1
1
The above topology is specified for the control code c=’1’.
Here even with one control bit Si we can achieve a glitch free
operation. The multiplexers used here are 2:1 MUX, with their
select lines being the delay code word.
The cascading is in such a way that even when the
control code increases by more than one, there will be no
glitch because the next stage always depends on the present
Table 1: Operation of MUX in non-inverting topology
state limiting on the condition that the first delay element
though has shorter propagation delay than the second will not
Terminal
Data
0
1
1
1
Control
bit
0
1
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MUX
output
1
1
produce any intermediate output producing a glitch.
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International Journal of Engineering Trends and Technology (IJETT) – Volume 9 Number 14 - Mar 2014
The number of transistors required to construct a
second produces an output earlier to the second. Hence based
multiplexer along with an inverter is four, which is same as in
on the output from the first delay line the final output will
case of NAND gates. The number of transistors as required by
experience a momentary change. These glitches do not occur
the existing method for one delay element is 24(6 NAND *
in the delay lines whenever the control code is ‘1’ since it
4transistors) without considering the driving circuit whereas
involves only a single delay element.
for proposed method with multiplexers we need only 12
B. Removal of glitches in NAND Based DCDL
transistors (3 MUX * 4transistors).
IV. SIMULATION RESULTS AND ANALYSIS
Software used: Modelsim SE 10.0b &
Xilinx ISE 9.1i
Scripting: VHDL
The results are achieved by coding the programs in
VHDL, simulated using MODELSIM SE 10.0b and they are
Fig 12: Removal of glitches in NAND based DCDL
analyzed with logical reasons.
The screenshot in figure 12 shows the absence of
A. Presence of glitches in NAND Based DCDL
glitches. The glitch free operation is got by introducing a
delay to the second delay element by including an additional
control bit Ti to the existing control bit Si. This eliminates
lack of synchronization between the delay elements, thus
eliminating the glitches.
C. Removal of glitches in MUX Based DCDL
Fig 11: Presence of glitches
The above snapshot in figure 11 is got from the non
inverting topology of the previously existing NAND based
delay lines which causes glitches in the circuit. The output as
analyzed shows that when the input is ‘0’ the output should be
‘0’ but at some instances the output momentarily goes to ‘1’
and then comes back to ‘0’.
Fig 13: Removal of glitches in MUX based DCDL (Thermometric Code)
The reason for the deviation in output producing a
The above output is got by implementing the
glitch is due to the reason that when the control code is more
proposed work. The NAND gates in the existing work are
than one, the first delay element having a less delay than the
replaced by multiplexers and this also eliminates the need for
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driving circuit, thereby reducing the area and power
consumed. There will not be any momentary change in output
since the select line of multiplexers is provided by a
thermometric code which preserves the intended output.
The area and power are calculated using XILINX
ISE 9.1i for the proposed glitch less delay line.
Fig 16.1: Power(mW) summary for NAND based DCDL
Fig 14.1: Area summary for NAND based DCDL
Fig 16.2: Power(mW) summary for MUX based DCDL
POWER
30.5
30
Fig 14.2: Area summary for MUX based DCDL
29.5
POWER
29
AREA
28.5
1000
950
900
850
NAND
MUX
AREA
Fig 15: Power(mW) comparison for NAND and MUX based DCDL
NAND
MUX
The area has been reduced by 5% and power has
been reduced by 3.33% than the existing NAND based delay
Fig 15: Area comparison for NAND and MUX based DCDL
lines.
V. CONCLUSION
The NAND and multiplexer based delay lines are
reviewed for the glitch parameter when either of these was used
as the delay element. The results of both these shows that
though the existing NAND based delay lines removes glitches
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International Journal of Engineering Trends and Technology (IJETT) – Volume 9 Number 14 - Mar 2014
introduces area, latency and power complexity. Owing to the
11.
bottlenecks in that DCDL, MUX based delay lines using
thermometric code was introduced. This topology shows that it
12.
had not only eliminated the glitches but also has reduced the
area occupied by the circuitry and power consumption. It has
replaced six delay elements representing a single control code
13.
by just three multiplexers. There is not much latency problems
as was present in NAND based DCDLs due to absence of flip-
14.
flops. It also provides intended delay to the circuitry without
output jitter.
15.
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