International Journal of Engineering Trends and Technology (IJETT) – Volume 21 Number 1 – March 2015
Performance analysis of trinary /quaternary
Multivalve Logic Digital Circuit
Braj kishor1, Anand Kumar Singh2, Sachin Bandewar3
1
IV SEM, SSSCE Bhopal (M.P.)
Asst. Prof. EC Deptt. SSSCE Bhopal (M.P.)
3
Asst. Prof. EC Deptt. SSSCE Bhopal (M.P.)
2
Abstract:
Multivalve logic carry more information
on a single line . It minimizes the number
of gates needed and largest number of
gates in any path from input to output.
Minimizing number of gates will reduce
the chip area, and minimizing depth will
give opportunity to use highest clock
frequency. In this paper the multivalve
logic gates has been design in multivalve
system and output as binary valued circuit.
Keywords: - MVL, Current mode, Voltage
mode, BITSWAP, Current mirror.
Designing of quaternary logic reduces the
number of digits to half compare to binary
logic.
A. Binary Logic
The binary logic has two levels in input
and output represented by i.e 0 and `1. An
AND Binary gate has two or more inputs
and produce one output as follows: output
=1; if all the inputs are high, output=0; if
one or more inputs are low. Similarly in Or
logic binary gate has two or more inputs
and produce one output as follows: output
=0 ; if all the inputs are high, output=1; if
one or more inputs are high.
I INTRODUCTION
The binary logic have two logic levels is
input and output represented by 0, 1.
While the ternary and quaternary logic
have three ( i.e 0, 1, 2) and four (0, 1, 2, 3)
logic levels. MVL reduces the number of
interconnects wires since it carries more
information on a single line.
Many
arithmetic and logical function are design
using MVL but there successful
implementation is yet to be done. The
ternary number system can be
writtenas0,1,2,10,11,12,20,21,22,100,101
,102,110,111,112, 1000 .etc whereas the
quaternary number system can be written
as0000,0001,0002,0003,0010,0011,0
B.Ternary/Quaternary logic level
The major area of binary logic base ICs are
occupied by the interconnection. The more
effective utilization of interconnections
possible uses a larger set of signals over
the same area in multiple valued logic
(MVL) devices. The higher radix in use is
the ternary (radix-3) and the quaternary
(radix-4). Two logic systems are available
in ternary logic, balanced ternary logic -1,
0 and 1 and simple ternary logic 0, 1 and 2.
The quaternary logic uses 0, 1, 2 and 3
logic levels. Figure 1 shows ternary logic
with a supply voltage. Figure 2 shows
quaternary logic levels.
012,0013,0100,0101,….etc.
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International Journal of Engineering Trends and Technology (IJETT) – Volume 21 Number 1 – March 2015
Fig 1 Ternary logic level
Figure 1 Quaternary logic levels.
II.RELATED WORK
LITERATURE REVIEW
Milton Ernesto Romero, Evandro Marina
Martins, Ricardo Ribeiro dos Santos, and
Mario Enrique Duarte Gonzalez design the
ternary and quaternary logic gates on
0.35um technology. They design the
multiplexer and latch circuit using these
multivalve gates. But there work is not
considered the parametric analysis of
power consumption, delay, fan in and fanout capabilities [1]. They get power
consumption in the range of 721uw to
1370 uW and the delay in the range of
30ns to 550ns [1]. Fatwa Sarica1
and Avni Morgul design a new latch
and restoration circuit which
improves
the
performance
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of
previously designed flip-flop circuit. The
major problem with this multi-valued logic
circuits is that they are not self restored
unlike the binary logic circuits. The
predefined current levels can be deviate
from their original values due to some
variations in active element dimensions,
power supplies, technology parameters, etc
[2]. Vasundara Patel, k s gurumurthy
design the quaternary multivalve logic
base
addition,
subtraction
and
multiplication
operations.
Minimal
functions have been obtained from the
Karnaugh diagrams for the addition and
multiplication and then simplified as much
as possible using all possible gate types.
Minimal functions obtained from the
minimal polynomials extracted from the
Karnaugh diagrams [3].
Ternary logic system contains three input
logic levels i.e 0, 1, 2. In this logic there
find different logic circuit gates.
In quaternary logic system, logic levels
ranges from 0 to 3 as against 0 and 1 in
binary logic. The logic system uses logic
gates and their operation is known as
operators. Quaternary algebra operators
are classified in two categories, namely
fundamental operators and functional
operators. The fundamental operators are
those selected operators that are sufficient
to completely define the quaternary
algebra and can be used to derive other
operators which includes AND, OR, NOT,
BITSWAP and the functional operators
are those operators that are described as
the combination of two or more
fundamental operators which includes
Inward Inverter, Outward Inverter,
Equality, MIN, MAX, XOR logics.
the
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International Journal of Engineering Trends and Technology (IJETT) – Volume 21 Number 1 – March 2015
A. Fundamental Operators:
AND/ OR/ NOT Gate: These gate have
two or more than two inputs and one
output. The truth table is shown below:
Table 1: Truth Table for Fundamental
Operators:
Input
Input
A
B
AND Y
OR Y
NOT
BIT
A
SWAP
0
0
0
0
3
0
0
1
0
1
3
0
0
2
0
2
3
0
0
3
0
3
3
0
1
3
1
1
2
2
1
1
0
3
2
2
A
1
2
1
3
2
2
2
3
2
2
1
1
2
2
2
3
1
1
3
3
3
3
0
3
A NOT gates have one input and produce
one output in quaternary algebra. BIT
SWAP swaps the two bits of the binary
equivalent of
the quaternary operand. It leaves the
symmetrical numbers unchanged but
inverts the asymmetrical numbers. Some
example are BITSWAP AND (AND
followed by BITSWAP), BITSWAP NOR
(NOR
followed
by
BITSWAP),
BITSWAP XNOR (XNOR followed by
BITSWAP) etc. In the BITSWAP NAND,
NOR, NOT and XNOR the inverter is
obviously NOT but not the inward or
outward inverter.
B. Functional operators Inward Inverter,
Outward Inverter, Equality, MIN, MAX,
XOR.
The inward inverter inverts the input just
like the NOT; but after that, it changes the
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symmetrical
values
to
nearest
asymmetrical values. Therefore, when the
output of the NOT would be 3 or 0, in the
case of the inward inverter, the value will
be 2 or 1, respectively. These inverters
may as well be used with other operators
to form compound operators; some
Examples are the inward AND, the inward
OR and the inward XOR where the inward
inverter follows the AND, OR and XOR
operators respectively [4, 5, 6].
Table 2: Truth Table for Functional
Operators:
Input
Input
A
B
0
0
0
XOR
Inward
Outward
INV
INV
Max
Min
0
2
3
0
0
1
1
2
3
1
0
0
2
2
2
3
2
0
0
3
3
2
3
3
0
1
3
0
2
3
1
1
1
1
3
2
3
2
1
1
2
2
2
3
3
1
2
3
0
1
0
2
2
2
2
1
1
0
3
2
3
3
0
1
0
3
3
The outward inverter inverts the input just
like the NOT, but after that it changes the
asymmetrical
values
to
nearest
symmetrical values. So when the output of
the NOT would be 2 or 1, in the case of the
outward inverter, the value will be 3 or 0,
respectively. The operator is named as
outward or full inverter because it converts
the output of the NOT to the nearest
absolute state. If we consider an outward
inverter instead of the inward inverter in
the above examples, then we get the
outward AND, the outward OR and the
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International Journal of Engineering Trends and Technology (IJETT) – Volume 21 Number 1 – March 2015
outward XOR operators, respectively.
MAX Gate is just like OR gate, Min Gate
is just like OR gate.
III.METHODOLOGY AND
IMPLEMENTATION
We can design the multivalve logic gate
truth table and then by converting binary
equivalent truth table to multivalve logic
truth table, we can design the CMOS
layout on MICROWIND layout editor
tool. Multiplexor type logic is design for
implementation of quadrature value logic.
It has n + l inputs, one of which is an n
valued
Control input whose value determines
which of the other n-valued inputs is
selected for output. Where xk is a fourvalued controlling or selecting input that
takes on values (0, 1, 2, 3). For xk =0,
input x, is selected; for xk =1, xp is
selected, and so on. Thus, in general xo =
< x l, x2, x3, x4>, using the stringsequence notation introduced in the main
text. For this implementation we can use
transmission gate logic.
Fig Transmission Gate base quadrature value logic.
Depending on the working MVL can be
realize in voltage-mode or current-mode
logic. in voltage mode , the data is transfer
in the form of voltage levels, whereas in
current mode the data is transfer in the
form of current levels. in voltage mode the
circuit density will increase and a very
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little power can be dissipated per cell to
avoid the chip from overheating. As Power
dissipation is directly proportional to
square of supply voltage, thus reduction in
supply voltage will reduce power
consumption. As a result, we have limited
radix at voltage-mode. Using transistors
having variable threshold voltages can be
thought as a solution for voltage mode
designs but it is still limited with
quaternary logic levels. In current mode
logic allow higher radix than voltage-mode
circuits. The main advantage of the
current-mode multi-valued circuits is the
simplicity of the addition operation.
A.Basic Multi-Valued Circuit
Elements
Sum: The major benefit of current-mode
implementation of multiple-valued circuits
is its summation operation. Currently
coming at the node is equal to its algebraic
summation as P: y = x1 + x2 +…..+ xn,
(algebraic sum).
Addition operation in voltage mode binary
circuits need an XOR and AND operator
which has 20 transistors in total.
Current mirror
Mirror circuits are used to produce the
copy of input currents. They can be
designed as n-type or p-type. Current
mirror is use to increase output current
driving capability, because current-mode
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International Journal of Engineering Trends and Technology (IJETT) – Volume 21 Number 1 – March 2015
CMOS logic allows fan-out of only one. In
addition, by rescheduling transistor sizing,
several current values in the design can be
multiplied by a constant scale factor k.
Switch: The NMOS or PMOS transistors
can be use as a switch The voltage level at
gate terminal will switch on or OFF the
MOSFET device which control the current
flow through this switch[7,8].
IV. CONCLUSION
Logic having more than two levels to a
single wire decreases the number of wires
for the same range of data, and this reduce
number of pins required for design. The
reduction in logic circuit also reduces the
wire interconnection length which in turn
decreases resistance and capacitance of
contacts and interconnections, and the
interconnection delay can be greatly
decreased. By using the platform of binary
logic system the complexity of digital
circuit is reduce in design circuit higher
than binary logic system is multivalve
logic. CMOS technology is chosen for the
circuit realization; embedding MVL
circuits in binary structure will perform
better than binary only. Multiple-valued
logic has many theoretical advantages -its
potential to increase the functional density
of metal-limited digital integrated circuit
layouts by reducing the number of signal
interconnections.
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[2] Fatma Sarica1 and Avni Morgül “Basic Circuits for MultiValued Sequential Logic" 7th International Conference on
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