International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 3- Dec 2013
Area Optimized Design for Data Archival to SD Card
Konatham Naga Lakshmi 1
P. Bala Nagu 2
PG Student (M. Tech), Dept. of ECE, Chirala Engineering College, Chirala, A.P, India.
2 Associate Professor, Dept. of ECE, Chirala Engineering College, Chirala, A.P, India .
*
1
Abstract: The main objective of this paper is to present the design of an efficient, real-time
data archival system to a Secure Digital flash memory card via softcore. The data access from
the SD card is implemented completely using Verilog and hence there is no use of any
microcontroller or on-chip general purpose processors. And since the complete design is a
single purpose system, no extra hardware is required. The design has four independent
modules for the required different operations on the SD memory card. These four modules are
for single block write, multiple block write, single block read, and multiple block read
operations. The modeled design can be simulated using Modelsim tool and the intended
functionality can be verified with the help of its simulation results and also it can be
synthesized using the Xilinx tool.
Keywords: SD, SDSC, SDXC, SDHC, Volatile, Non-Volatile, Simulation, Xilinx
families are the original Standard-
1. Introduction
Secure Digital (or SD) is a non-
Capacity (SDSC), the High-Capacity
volatile memory card format for use in
(SDHC),
portable
devices,
(SDXC),
phones,
digital
such
as
mobile
cameras,
GPS
the
and
combines
eXtended-Capacity
the
SDIO,
input/output
which
functions
tablet
with data storage.234 The three form
Digital
factors are the original size, the "mini"
standard was introduced in 1999 as
size, and the "micro" size. There are
an
many combinations of form factors
navigation
devices,
computers.
The
evolutionary
and
Secure
improvement
over
MultiMediaCards (MMC). The Secure
Digital standard is maintained by the
SD
Card
Association
(SDA).
SD
technologies have been implemented
in more than 400 brands across
dozens
of
product categories
and
and device families.
Electrically passive adapters allow
the use of a smaller card in a host
device built to hold a larger card.
Host devices that comply with
newer versions of the specification
provide backward compatibility and
more than 8,000 models.1
The Secure Digital format includes
accept older SD cards, but there are
four card families available in three
several factors that can prevent the
different
use of a newer SD card:
form
factors.
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The
four
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International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 3- Dec 2013
•A
newer
card
may
offer
greater
High Capacity) and SDXC (Secure
capacity than the host device can
Digital
handle.
cards redefine the interface so that
• A newer card may use a file system
the host device cannot navigate.
be
input/output
These
they cannot be used in older host
• It defined an SDIO card family that
designed
for
the
provides input-output functions and
functions
the
card
may also provide memory functions.
provides.
These cards are only fully functional
• The organization of the card was
changed
Capacity).
devices.
• Use of an SDIO card requires the host
device
eXtended
starting
with
theSDHC
in host devices designed to support
their input-output functions.
family.
• Some vendors produced SDSC cards
above 1 GB before the SDA had
standardized a method of doing so.
The SDA uses several trademarked
logos to enforce compliance with its
specifications and assure users of
compatibility.
Types of cards
Figure 1 Physical size of a SD card
The SDA has extended the SD
specification in various ways:
Size comparison of families: SD
• It defined electrically identical cards
in smaller sizes: miniSD and microSD
(blue), miniSD (green), microSD (red)
(originally named TransFlash or TF).
The SD card specification defines
Smaller cards are usable in larger
three physical sizes. The SD and
slots
passive
SDHC families are available in all
adapter. By comparison, Reduced Size
three sizes, but the SDXC family is
MultiMediaCards
are
not available in the mini size, and the
simply shorter MMCs and can be
SDIO family is not available in the
used in MMC slots by use of a
micro size.
through
use
of
a
(RS-MMCs)
Standard size
physical extender.
• It defined higher-capacity cards, some
with
faster
capabilities:
speeds
SDHC
ISSN: 2231-5381
and
added
(Secure
Digital
• SD (SDSC), SDHC, SDXC, SDIO
• 32.0×24.0×2.1 mm (1.26×0.94×0.083
in)
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International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 3- Dec 2013
• 32.0×24.0×1.4 mm (1.26×0.94×0.055
in) (as thin as MMC) for Thin SD(rare)
cards.1
However,
host
devices
designed for SDSC do not recognize
Mini size
SDHC
• miniSD, miniSDHC, miniSDIO
although some devices can do so
• 21.5×20.0×1.4 mm (0.85×0.79×0.055
through a firmware upgrade.8 Older
in)
or
SDXC
memory
cards,
operating systems require patches to
Micro size
support
The micro form factor is the smallest
Microsoft Windows XP before SP3
SD card format.6
SDHC.
For
instance,
requires a patch to support access to
• microSD, microSDHC, microSDXC
SDHC cards.9 Windows Vista also
• 15.0×11.0×1.0 mm (0.59×0.43×0.039
requires service pack 2.
in)
Figure 3 Official SDXC logo
The
Figure 2 SDHC official Logo
The Secure Digital High Capacity
Capacity
Secure
(SDXC)
Digital
format
eXtended
supports
(SDHC) format, defined in Version 2.0
cards up to 2TB (2048 GB), compared
of
to a limit of 32 GB for SDHC cards in
the
SD
specification,
supports
cards with capacities up to 32 GB.2
the SD 2.0 specification.
2. Technical Specifications
The SDHC trademark is licensed to
Transfer modes
ensure compatibility.7
Cards
SDHC cards are physically and
may
support
various
standard-
combinations of the following bus
capacity SD cards (SDSC). The major
types and transfer modes. The SPI
compatibility issues between SDHC
bus mode and one-bit SD bus mode
and SDSC cards are the redefinition
are mandatory for all SD families, as
of
(CSD)
explained in the next section. Once
register in Version 2.0 (see below),
the host device and the SD card
and the fact that SDHC cards are
negotiate a bus interface mode, the
shipped preformatted with the FAT32
usage of the numbered pins is the
file system.
same for all card sizes.
electrically
the
identical
Card-Specific
to
Data
Host devices that accept SDHC
cards are required to accept SDSC
ISSN: 2231-5381
• SPI
bus
mode:
Serial
Peripheral
Interface Bus is primarily used by
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International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 3- Dec 2013
embedded microcontrollers. This bus
type
supports
only
a
3.3-volt
interface.
• One-bit
Inside a 512 MB SD card:NAND
flash
SD
bus
mode:
Separate
chip
that
holds
the
data
(bottom) and SDcontroller (top)
command and data channels and a
proprietary transfer format.
• Four-bit SD bus mode: Uses extra
pins plus some reassigned pins. UHSI and UHS-II requires this bus type.
The physical interface comprises 9
pins, except that the miniSD card
Figure 6 Internal Cross Section 2GB SD
adds two unconnected pins in the
Inside a 2 GB SD card: two NAND
center and the microSD card omits
flash chips (top and middle), SD
one of the two VSS (Ground) pins.
controller chip (bottom)
Figure 7 Inside a 16 GB SDHC card
Command interface
SD cards and host devices initially
Figure 4 Official Pin out for SD cards
Official pin numbers for each card
type
(top
to
bottom):
MMC,
SD,
communicate through a synchronous
one-bit
interface,
where
the
host
miniSD, microSD. This shows the
device provides a clock signal that
evolution from the older MMC, on
strobes single bits in and out of the
which SD is based.
SD card. The host device thereby
sends 48-bit commands and receives
Interface
responses. The card can signal that a
response will be delayed, but the host
device can abort the dialogue.
Figure 5 Internal Cross Section 512 MB SD
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International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 3- Dec 2013
Through
issuing
various
commands, the host device can:
support for the four-bit SD bus is
• Determine the type, memory capacity,
and capabilities of the SD card
different
clock
either optional or mandatory.41
After determining that the SD card
• Command the card to use a different
voltage,
supports it. For various card types,
speed,
or
advanced electrical interface
supports it, the host device can also
command the SD card to switch to a
higher
transfer
speed.
Until
• Prepare the card to receive a block to
determining the card's capabilities,
write to the flash memory, or read
the host device should not use a clock
and reply with the contents of a
speed faster than400 kHz. SD cards
specified block.
other than SDIO (see below) have a
The
command
an
"Default Speed" clock rate of 25 MHz.
MultiMediaCard
The host device is not required to use
(MMC) interface. SD cards dropped
the maximum clock speed that the
support for some of the commands in
card supports. It may operate at less
the
than the maximum clock speed to
extension
of
MMC
interface
the
protocol,
is
but
added
commands related to copy protection.
conserve
By using only commands supported
commands, the host device can stop
by both standards until determining
the clock entirely.
the type of card inserted, a host
SDIO cards
device can accommodate both SD and
power.41
Between
The SDIO family comprises Low-
MMC cards.
Speed and Full-Speed cards. Both
Electrical interface
types of SDIO cards support SPI and
All SD card families initially use a
3.3-volt
electrical
interface.
On
one-bit SD bus types. Low-Speed
SDIO
cards
are
allowed
to
also
command, SDHC and SDXC cards
support the four-bit SD bus; Full-
switch to 1.8-volt operation.
Speed SDIO cards are required to
At
initial
card
support the four-bit SD bus. To use a
selects
SDIO card as a "combo card" (for both
either the Serial Peripheral Interface
memory and I/O), the host device
(SPI) bus or the one-bit SD bus by the
must first select four-bit SD bus
voltage
1.
operation. Two other unique features
Thereafter, the host device may issue
of Low-Speed SDIO are a maximum
a command to switch to the four-bit
clock
SD bus interface, if the SD card
communications, and the use of Pin 8
insertion,
the
level
power-up
host
device
present
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or
on
Pin
rate
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of
400
kHz
for
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International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 3- Dec 2013
as
"interrupt"
to
try
to
initiate
dialogue with the host device.
command
messages to pass to the
SD CMD
•Read response messages from the SD
3. Architecture design
CMD Host and forward it to the user
accessible
register
in
the
SD
Controller Top module.
•Keep track of the status of the CMD
Host module.
SD CMD Host
This
towards
Figure 8 Simplified internal architecture
module
is
the
interface
between the SDC Core and the bus .
Two WB interfaces (slave and master)
are used for this. The
internal
registers and buffer descriptors (BD)
WB Slave Interface. The master
interface is used for the internal DMA
to fetch and store data to and from an
external
memory.
contains
the
The
setting
module
and
status
register accessible by user from the
WB slave, and the required
logic to
interface
SD/MMC
cards
of the physical sending and receiving
of the messages, adding start bits,
stop bits and CRC checksum.
SD (Bd) Buffer descriptor
The
transmission
and
the
descriptors. Two sequential wrings to
this module is required to create one
buffer descriptor. First the source
address (Memory location) of the data
is written then the card block address
is written.
SD DATA Master
Starts to check if there are any
access this.
new BD thats need to be processed if
SD CMD Master
SD CMD Master module
synchronize the communication from
the host interface with the physical
interface . perform has three main
so the module generate a command
and set up the DMA to read/write to
correct address. If the command line
is free the module send the command
and wait fore response. If response is
tasks:
•Read a set of register from the user
accessible
the
reception processes are based on the
are all accessed through the same
The
physical
is
command pin. This module takes care
SD controller top
This
module
register
in
the
SD
valid the
module starts the DMA if
not valid the CMD is resent again.
Controller Top to compose a 40 bit
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International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 3- Dec 2013
During transmission the module
DAT3), one command line (CMD) and
keep track for FIFO buffet underflow
a
or overflows, when the transmission
operating in push pull mode, all
is completed it check for valid CRC. If
signals except CLK shall have a pull
anything
up resistor of a recommended size of
goes
wrong
during
a
clock line (CLK). All signals are
transmission a stop command is sent
10-100kΏ
and the module try to restart the
Bus protocol
transmission n times before giving up.
SD Data Host
This
module
Communication over the SD bus is
based on command and data bit
is
the
interface
streams that are initiated by a start
towards physical SD card device Data
bit and terminated by a stop bit. A
port. The interface consist of only 5
command is used start an operation
signals, one clock SDCLK, and the 1-
in the card, most command gives a
4 bit bi-direction Data signal DAT.
response token as reply.
The module perform the following
actions.
Command transfer
When
• Synchronized request for write and
read data and .
the
bus
is
free/idle,
meaning command line is high, an
command transfer can be initiated by
• Adding a CRC-16 checksum on sent
sending a start signal. A start signal,
data and check for correct CRC-16 on
usually referred to as the S-bit, which
received commands.
is defined as a high-to-low transition
SD FIFO Tx/Rx Filer
of the CMD line. The command bit is
This module works as the DMA it
manager the receive and transceiver
sent in a MSB to LSB fashion.
Data transfer
FIFO buffer for the data stream. It
To start a data transmission first a
keeps track of the status of the FIFO:s
command request for data has to be
if somethings goes wrong, like full
sent
receiver FIFO or empty transfer buffer
transmission starts with a S-bit on
it signals this.
DAT0 line. The data is sent in a
SD Clock Divider
lowest byte first, highest byte last
Divide the input clock with 2 4 6
to
the
card.
A
data
then
manner, with MSB to LSB manner for
etc..
each byte.
SD/MMC Operation
Core Operation
The SD/MMC cards bus includes
Note that the Rx and Tx FIFO is
the following,a serial data line (DAT0-
not intended to be implemented as
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International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 3- Dec 2013
RAM-block and therefore require a
step. First the command index and
lots of logic if setting to high. If FIFO
transmission
overflow or underflow a option is
command to be, sent is written into
instead to lower the clock speed to the
the Command setting Register. Next
card or enchant the performance of
the commands argument bits of the
the system around to not use the
command
memory as much leaving more free
argument register, which then initiate
bus access cycler to the SD core.
the transfer. Upon response bit 0 in
Resetting the core
the Normal interrupt status register is
The
RST_I
signal
is
used
for
settings
is
be
for
written
to
the
the
set to 1 and the response is available
resetting all modules. This can also be
in response register.
If any of the
done by setting the SRST bit in the
requested error check
fails will this
Software reset register to 1 .
be visible in the Error interrupt status
Setting up the core
register.
• Reset the core
Buffer descriptors
• Set the timeout register
The
transmission
and
the
• Assert Software reset
reception processes are based on the
Host Interface Operation
descriptors. The Transmit
The host interface connects the IP
Descriptors
Core to the rest of the system (RISC,
transmission
memory) via the WISHBONE bus. The
Descriptors
WISHBONE
serves
while
(RxD)
are
the
are
used
for
Receive
used
for
access
the
reception. The buffer descriptors are
and
the
64 bits long. The first 32 bits contain
DMA
the pointer to the associated buffer
for
(where data is stored) while the last
transferring the data from/to the
32 bits contain the card block address
memory.
to read or write from. The core has a
Configuration Registers
internal ram that can store up to 255
configuration
memory.
transfers
to
(Tx)
registers
Currently,
are
only
supported
The function of the configuration
registers is transparent and can be
easily
understood
by
reading
the
Tx and Rx BD.
Data block transmission
To transmit a block of data, the
Registers section
RISC has to perform several steps.
Sending commando
First make sure the card is initiated
The sending of a command to the
correctly and is ready for data with
SDC/MMC card is performed in two
the block size of 512 byte with all 4
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International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 3- Dec 2013
data bits enabled. If interrupt is used,
The no of IOB’s required to test
those associated with the command
the
line should be disabled to not receive
proposed SD CARD which is obtained
unnecessary interrupts when the data
from the design summary report . The
module use the CMD line. Enabling
modeled design can be simulated
interrupts
using Modelsim tool and the intended
generated
by
the
data
module should instead be activated.
functionality
is
less
for
this
functionality can be verified with the
Then it has to check the BD status
help of its simulation results and also
register to see if there are any free
it can be synthesized using the Xilinx
BD. If so it store what to be sent in
tool. Fig 9 & 10 Shows the Simulation
the memory after that it writes the
Results of the Designed module & Fig
start address of the stored data to the
11 shows the RTL schemetic.
the TX Buffer descriptor register and
the
destination
block
address.The
core continuously reads the first BD,
where it reads the pointer to the
memory storing the associated data
and starts then reading data to the
internal FIFO. At the end of the
Figure 9 SD Controller top module simulation results-1
transmission, the transmit status is
written to the data interrupt status
register
and
interrupt might be
generated (when enabled). The next
descriptor is then loaded if more is
qued up, and the process starts all
over again.
Figure 10 SD Controller top module simulation results-2
4. Results& Conclusions
A bidirectional core for the SD
card
design
was
implemented
in
XILINX ISE. Secure Digital (or SD) is a
non-volatile memory card format for
use in portable devices, such as
mobile phones, digital cameras, GPS
navigation
devices,
and
tablet
computers.
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International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 3- Dec 2013
ProdManualSDCardv1.9.pdf,
accessed
April 2010.
[3] C. Lin and L. Dung. “A NAND Flash
Memory Controller for SD/MMC Flash
Memory Card,” IEEE Transactions on
Magnetics, Vol. 43, 2007.
[4] C. Li, Q. Wang, and L. Wang. “A high
efficient Flash storage System for Two
way Cable Modem,” in Proceedings of
Figure 11 Internal RTL Schematic of SD controller
IEEE
Design Statistics
# IOs
:1
#
:1
GND
[5] O. Elkeelany and G. Vince. "Portable
: 77
#
: 77
Analog
kilobytes
The authors would like to thank
reviewers
for
their
comments which were very helpful in
improving the quality and presentation
of this paper.
M.
Abdallah
“Simultaneous
Acquisition
and
39th
Using
Custom
Southeastern
Symposium
on
System Theory, pp. 120-123, 2007.
Han. “Read/write SD Card based on
Microcontroller
and
O.
Elkeelany.
Multi-channel
Storing
Data
System,”
in
MSP430,”
Journal
of
Biomedical Engineering Research, 2004.
[7] Y. Ming-Ji, L. Yuan, and S. Ji-Yu.
“Interface
Digital
References:
[1]
Capture
[6] D. Young, C. Zhen-Cheng, and S.
Acknowledgements
anonymous
Data
Processing," in Proceedings of The IEEE
Total memory usage is 186332
the
on
pp. 551-556, 2008.
# IO Buffers
OBUF
Workshop
Computer and Information Technology,
: 150
# BELS
International
Design
Card
between
and
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Secured
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Authors Profile:
Konatham Naga Lakshmi
proceedings of International Conference
is Pursuing her M. Tech
on
from Chirala Engineering
Computing,
Engineering
and
Information ICC‟09, pp.233-236, 2009.
College,
Chirala
in
the
[2] SanDisk SD card product manual,
department of Electronics & Communications
available:
Engineering
http://www.cs.ucr.edu/~amitra/sdcard/
VLSI & Embedded systems.
ISSN: 2231-5381
(ECE)
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with
specialization
Page 148
in
International Journal of Engineering Trends and Technology (IJETT) – Volume 6 Number 3- Dec 2013
P. Bala Nagu is working
as an Associate Professor
in
the
department
Electronics
of
&
Communication Engineering in Chirala
Engineering College,Chirala. He has Nine
years of teaching experience along with
one year industrial experience.
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