International Journal of Engineering Trends and Technology (IJETT) – Volume 5 Number 6 - Nov 2013
Low Power Coding Approach With Error Free Coding
Scheme in VLSI Design
1
Rajyalakshmi 2SK Rahil Hussain
M.Tech ,VLSI&Embeded Systems
2
Asst.Professor, Dept of ECE,Amrita Sai Institute of Science and Technology
Paritala,Kanchikacherla(md),Krishna(Dt)
1
ABSTRACT—The low power has emerged
VHDL definition using active HDL tool for
as a principle design requirement in today’s
its
electronics industry. The need for low power
synthesized on Xilinx ISE for synthesis and
consumption
FPGA editor for its practical realization.
has
become
important
functional
simulation
and
to
be
consideration as performance & area. Even
KEYWORDS — power optimization, bit
several methods exists, still there requires
transition, lagger algorithm, hamming code,
enhancement for optimization of power
bus shuffling, bit streams.
consumption in VLSI circuits. There were
several approaches in circuit level, but a
INTRODUCTION
very few approaches made at system level,
such as bus transition power consumption. A
The integration of devices in System
large amount of power gets dissipated under
On Chip (SOC) the issue of power
the transition of bit sequence from ‘0’ to ‘1’
consumption is increasing. There is a need
or ‘1’ to ‘0’ transitions. These powers could
to develop simpler and efficient low power
be saved if these transitions could be
coding scheme, which can reduce the power
minimized.
optimization
consumption at routing level and logical
approach in bus transitions using Hamming-
level. Though various techniques were
coding scheme called ‘Lagger algorithm’ for
developed
transition power reduction in VLSI design is
consumption in logical devices the other
to be developed. As to minimize the
power consumption approaches is also
transition, the code bit streams are shuffled
needed to be improved. In this work a focus
before transmission using an Encoder unit
is given towards minimization of power
and bit streams are regenerated using a
consumption in data transition time. For the
decoder algorithm by bus shuffling scheme.
evaluation of the developed approach the
The proposed work is to be developed on
coding approach is integrated with an error
The
power
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minimize
the
power
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International Journal of Engineering Trends and Technology (IJETT) – Volume 5 Number 6 - Nov 2013
coding
approach
to
evaluate
the
does the number of functional modules on a
minimization of power consumption in
chip
transition. The error coding technique used
requirements among the modules demand
in the current low power coding approach.
more complicated and more efficient buses.
ERROR CODING TECHNIQUE
Increasing
communication
SWITCHING POWER DISSIPATION
In any digital system the information
This is due to the charging and
bits are fed into the encoder to encode the
discharging of capacitive loads during logic
information.
changes. The dominant source of power
dissipation
Vector and the fault secure detector
is
thus
the
charging
and
discharging of the node capacitances also
of the encoder verify the validity of the
referred
to
encoded vector. If the detector detects any
dissipation.
as
the
dynamic
power
error, the encoding operation must be redone
to generate the correct codeword. Transient
The dynamic power dissipation and is given
errors accumulate in the Digital words over
by:
= 0.5 time. In order to avoid a dynamic power
(
)
dissipation.
where C is the physical capacitance of the
TRANSITION
OPTIMIZATION
USING
POWER
circuit, Vdd is the supply voltage, E(SW)
SWITCH
referred as the switching activity is the
LOGIC
average number of transitions in the circuit
per 1/fclk is the clock frequency.
Buses have been used as an efficient
communication
link
functional
A coding scheme called sequence-
modules in very large scale integration
switch coding (SSC) is developed to reduce
(VLSI) systems. Whereas the size of
the transition power consumption in this
functional modules decreases with the
work.
development of semiconductor technology,
transition-reduction coding schemes in that
the size of VLSI chips increases, and so
it is aimed at applications with the
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among
It
is
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different
from
previous
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International Journal of Engineering Trends and Technology (IJETT) – Volume 5 Number 6 - Nov 2013
stream-type data transfer pattern. SSC
application that transmits more than two
reduces the number of bus transitions by
data sequentially for most operations.
rearranging the transmission sequence of
data. An algorithm called switch algorithm
let us assume that there are 8data to
is presented to show the feasibility of SSC.
be sent via a bus as shown in figure is the
This algorithm reduces around 10% of bus
wave form of the bus ,when these are
transitions in transmission of the benchmark
transmitted without any modifications. If the
files. A switched sequence is defined as the
data is sent with a different order example
sequence of words transmitted according to
D1-D3-D4-D5-D6-D2-D8-D7,the
an SSC algorithm. Let us express the
from is changed as in figure. the number of
hamming distance between a word, W and a
transitions with the new order is 23
bus, B, as H(W;B).
compared to 32 with the original order.
wave
about 28 percent of bus changing only the
SEQUENCE SWITCH CODING
TECHNIQUE
transmission order reduces transitions .SSC
which is based on this observation, is a
method intended to reduce the power
consumption of busses by changing only the
data segment. The waveforms of eight-bit
The effect of transmission sequence on bus transitions original order and Different order
bus for the eight data are transmitted by the(
SSC is the first general-purpose coding
original order and a different order. So far,
scheme that employs the sequence of data
most of the previous transition-reduction
in reducing the number of bus transitions.
coding schemes have been developed for the
SSC needs no prior information on data to
granulated data, therefore, they have not
be sent, and it can be applied to
considered the sequence of data as an
any
important factor.
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International Journal of Engineering Trends and Technology (IJETT) – Volume 5 Number 6 - Nov 2013
DESIGN IMPLEMENTATION
illustrates the operational block diagram for the bus transition minimization using open
consumption using the suggested switching
switch Algorithm
logic approach is suggested.
The encoder unit consists of a comparator
A. Bus Transition Optimization
units and a counter unit for the generation of
Technique
data stream during coding phase.
For the optimization of power consumption
during
transition
The coding system reads the original
optimization for encoding and decoding
data stream and code to generate equivalent
architecture is developed.
in the below
coded streams passed as source data to the
illustrates the operational block
encoding unit. The source data in binary
diagram for the bus transition are passed to
format is passed to the encoding unit in
the encoding unit, after providing the error
parallel format and are encoded using
coding as explained in previous sections.
Hamming code distance for transition
These information bits are then coded for
minimizations. The transition minimization
low transition logic to reduce the power
is carried with a parity code and is passed to
Figure
data
transition
a
the
decoder
for
power
consumption
minimization. The internal functional units
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International Journal of Engineering Trends and Technology (IJETT) – Volume 5 Number 6 - Nov 2013
for
the
operation
of
the
suggested
architecture is as explained below.
xilinx ISE tool. The obtained simulation
results are as shown below,
The hamming code comparator unit
A. Timing Simulation Observation:
takes the three input data Din ,Bus and
Switch bus for the calculation of hamming
The obtained simulation observation on
distance for Switch and input data with data
performing write operation is as illustrated
bus.
below.
The obtained simulation result for
The decoder units with storage
the encoding system is as shown above. The
operation takes the hamming count and
error-coded information’s are passed to the
generates a count value based on the
encoder unit where a switching scheme is
hamming distance passed the comparison is
developed
made and if the hamming distance is
transitions to reduce the transition power
observed to be greater than the second value
consumption.
for
the
minimization
of
then status signal s=0 is generated or else a
'1 'is generated . The decoding operation of
the designed system and the probable
storage operation for the decoding operation
storing the segregated information for s='1'
in digital location(mem1) and s='0' for
digital location(mem2).Based on the digital
location filled the data is segregated as
block1 or block2 information
RESULT
For the evaluation of the suggested
approach an simulation is carried out in
The simulation result for the developed
active HDL tool and synthesized using
routing power transition minimization
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International Journal of Engineering Trends and Technology (IJETT) – Volume 5 Number 6 - Nov 2013
The modified data passed to the decoder
encoder and decoder approach and the coded
after switch logic transition is shown in
information is evaluated for accuracy using
above figure. It could be observed that the
the decoding logic developed. The approach
simulation result obtained after the decoding
of logical transition for the coded data is
of received modified information is same as
developed using open switch logic scheme.
the
This
Where the coded data stream is passed is
illustrates the accuracy of the developed
switched in an order to minimize transition
switch decoder logic after data bit switching.
based the code bit distance.
original
coded
information.
It illustrates the number of data transition
seen for the given data which is observed to
The developed system is observed to
be reduced from 94 transitions to 49
be accurate and provides about 50% lower
transitions in the developed approach.
transition to the original data transfer. The
Once the decoded information is retrieved
encoding and decoding approach for the
accurately the error decoding system is
developed system is tested for different data
processed
original
word bits and observed to be accurately
information back based on the developed
recovering for up to half the data bit
error decoding logic. The simulation clearly
transition. The process of encoding and
illustrates that the obtained data stream after
decoding operation is developed on VHDL.
to
retrieve
the
the decoding logic is exactly the same as the
original data sets. Synthesis Report is shown
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CONCLUSION
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International Journal of Engineering Trends and Technology (IJETT) – Volume 5 Number 6 - Nov 2013
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