University of Babylon/College of IT S/W Dept.
1st Class/Computer Organization
2. REGISTER SET
Registers are essentially extremely fast memory locations within the CPU
that are used to create and store the results of CPU operations and
other calculations. Different computers have different register sets. They
differ in the number of registers, register types, and the length of each
register. They also differ in the usage of each register. General-purpose
registers can be used for multiple purposes and assigned to a variety of
functions by the programmer. Special-purpose registers are restricted
to only specific functions. In some cases, some registers are used only to
hold data and cannot be used in the calculations of operand addresses.
The length of a data register must be long enough to hold values of most
data types. Some machines allow two contiguous registers to hold
double-length values. Address registers may be dedicated to a particular
addressing mode or may be used as address general purpose. Address
registers must be long enough to hold the largest address. The number
of registers in a particular architecture affects the instruction set design.
A very small number of registers may result in an increase in memory
references. Another type of registers is used to hold processor status
bits, or flags. These bits are set by the CPU as the result of the execution
of an operation. The status bits can be tested at a later time as part of
another operation.
2.1 General-Purpose Registers
The main tools to write programs in x86 assembly are the processor
registers. The registers are like variables built in the processor. Using
registers instead of memory to store values makes the process faster
and cleaner. The problem with the x86 serie of processors is that there
are few registers to use. This section describes the main use of each
register and ways to use them. That in note that the rules described here
are more suggestions than strict rules. Some operations need absolutely
some kind of registers but most of the you can use any of the freely.
Here is a list of the available registers on the 386 and higher processors.
This list shows the 32 bit registers. Most of the can be broken down to
16 or even 8 bits register.
As the title says, general register are the one we use most of the time
Most of the instructions perform on these registers. They all can be
broken down into 16 and 8 bit registers.
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University of Babylon/College of IT S/W Dept.
1st Class/Computer Organization
32 bits : EAX EBX ECX EDX
16 bits : AX BX CX DX
8 bits : AH AL BH BL CH CL DH DL
The "H" and "L" suffix on the 8 bit registers stand for high byte and low
byte. With this out of the way, let's see their individual main use
EAX,AX,AH,AL : Called the Accumulator register.
It is used for I/O port access, arithmetic, interrupt calls,
etc...
EBX,BX,BH,BL : Called the Base register
It is used as a base pointer for memory access
Gets some interrupt return values
ECX,CX,CH,CL : Called the Counter register
It is used as a loop counter and for shifts
Gets some interrupt values
EDX,DX,DH,DL : Called the Data register
It is used for I/O port access, arithmetic, some interrupt
calls.
2.2 Special-Purpose Registers
2.2.1 Memory Access Registers
Two registers are essential in memory write and read operations: the
memory data register (MDR) and memory address register (MAR). The
MDR and MAR are used exclusively by the CPU and are not directly
accessible to programmers.
In order to perform a write operation into a specified memory location,
the MDR and MAR are used as follows:
1. The word to be stored into the memory location is first loaded by the
CPU into MDR.
2. The address of the location into which the word is to be stored is
loaded by the CPU into a MAR.
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University of Babylon/College of IT S/W Dept.
1st Class/Computer Organization
3. A write signal is issued by the CPU.
Similarly, to perform a memory read operation, the MDR and MAR are
used as follows:
1. The address of the location from which the word is to be read is
loaded into the MAR.
2. A read signal is issued by the CPU.
3. The required word will be loaded by the memory into the MDR ready
for use by the CPU.
2.2.2 Instruction Fetching Registers
Two main registers are involved in fetching an instruction for execution:
the program counter (PC) and the instruction register (IR). The PC is the
register that contains the address of the next instruction to be fetched.
The fetched instruction is loaded in the IR for execution. After a
successful instruction fetch, the PC is updated to point to the next
instruction to be executed. In the case of a branch operation, the PC is
updated to point to the branch target instruction after the branch is
resolved, that is, the target address is known.
2.2.3 Segment registers
Segment registers hold the segment address of various items. They are
only available in 16 values. They can only be set by a general register or
special instructions. Some of them are critical for the good execution of
the program and you might want to consider playing with them when
you'll be ready for multi-segment programming
CS
: Holds the Code segment in which your program runs.
Changing its value might make the computer hang.
DS
: Holds the Data segment that your program accesses.
Changing its value might give erronous data.
ES,FS,GS : These are extra segment registers available for
far pointer addressing like video memory and such.
SS
: Holds the Stack segment your program uses.
Sometimes has the same value as DS.
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University of Babylon/College of IT S/W Dept.
1st Class/Computer Organization
Changing its value can give unpredictable results,
mostly data related.
2.2.4 Indexes and pointers
2.2.4 .1 Index Registers
In index addressing, the address of the operand is obtained by adding a
constant to the content of a register, called the index register. The index
register holds an address displacement. Index addressing is indicated
in the instruction by including the name of the index register in
parentheses and using the symbol X to indicate the constant to be
added.
Segment Pointers : in order to support segmentation, the address
issued by the processor should consist of a segment number (base)
and a displacement (or an offset) within the segment. A segment
register holds the address of the base of the segment.
2.2.4 .2 Stack Pointer : a stack is a data organization mechanism
in which the last data item stored is the first data item retrieved. Two
specific operations can be performed on a stack. These are the Push and
the Pop operations. A specific register, called the stack pointer (SP), is
used to indicate the stack location
that can be addressed. In the stack push operation, the SP value is used
to indicate the location (called the top of the stack).
Indexes and pointer and the offset part of and address. They have
various uses but each register has a specific function. They some time
used with a segment register to point to far address (in a 1Mb range).
The register with an "E" prefix can only be used in protected mode.
ES:EDI EDI DI : Destination index register
Used for string, memory array copying and setting and
for far pointer addressing with ES
DS:ESI EDI SI : Source index register
Used for string and memory array copying
SS:EBP EBP BP : Stack Base pointer register
Holds the base address of the stack
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University of Babylon/College of IT S/W Dept.
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SS:ESP ESP SP : Stack pointer register
Holds the top address of the stack
CS:EIP EIP IP : Index Pointer
Holds the offset of the next instruction
It can only be read
2.2.5 Condition Registers
Condition registers, or flags, are used to maintain status information.
Some architectures contain a special program status word (PSW)
register. The PSW contains bits that are set by the CPU to indicate the
current status of an executing program. These indicators are typically for
arithmetic operations, interrupts, memory protection information, or
processor status.
The EFLAGS register
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University of Babylon/College of IT S/W Dept.
1st Class/Computer Organization
The EFLAGS register hold the state of the processor. It is modified by
many intructions and is used for comparing some parameters,
conditional loops and conditionnal jumps. Each bit holds the state of
specific parameter of the last instruction. Here is a listing :
Bit Label Desciption
--------------------------0 CF Carry flag
2 PF Parity flag
4 AF Auxiliary carry flag
6 ZF Zero flag
7 SF Sign flag
8 TF Trap flag
9 IF Interrupt enable flag
10 DF Direction flag
11 OF Overflow flag
12-13 IOPL I/O Priviledge level
14 NT Nested task flag
16 RF Resume flag
17 VM Virtual 8086 mode flag
18 AC Alignment check flag (486+)
19 VIF Virutal interrupt flag
20 VIP Virtual interrupt pending flag
21 ID ID flag
Those that are not listed are reserved by Intel.
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