A 76GHz PLL for mm-wave imaging applications
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Citation
Nguyen, Khoa M., Helen Kim, and Charles G. Sodini. “A 76GHz
PLL for Mm-wave Imaging Applications.” IEEE MTT-S
International Microwave Symposium Digest 2010 (MTT).
1316–1319. © Copyright 2010 IEEE
As Published
http://dx.doi.org/10.1109/MWSYM.2010.5515925
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Version
Final published version
Accessed
Thu May 26 20:17:37 EDT 2016
Citable Link
http://hdl.handle.net/1721.1/72668
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Detailed Terms
A 76GHz PLL for mm-Wave Imaging Applications
Khoa M. Nguyen, Helen Kim, Charles G. Sodini
Massachusetts Institute of Technology, Cambridge, Massachusetts, 02139, USA
Lincoln Laboratory, Lexington, Massachusetts, 02421, USA
Abstract
-
To Central
Processor
A 76GHz phase-locked loop (PLL) was designed
in O.13um IBM BiCMOS8HP technology with the intended
application of millimeter-wave imaging. The PLL has a type II
second order loop filter. The voltage-controlled oscillator (VCO)
uses a cross-coupled BJT topology with capacitor feedback. The
divider chain has nine divide-by-2 static frequency dividers in
which the first seven use ECL logic and are followed by two
CMOS stages. Measurement results show a de-embedded single­
ended output power of -2dBm, a phase noise of -81dBc/Hz at
IMHz offset from the carrier, and a total power dissipation of
Per-Antenna Processor
l07mW.
Index Terms
-
millimeter-wave imaging, PLL.
Fig. I.
Block diagram of receiver for imaging system.
I. INTRODUCTION
II. NOISE ANALYSIS
Millimeter wavelengths (MMW) are small enough to offer
sufficient spatial resolution for imaging yet large enough to
Beamforming
have low attenuation when passing through inclement weather
conditions.
This
makes
MMW
imaging
amenable
requires
accurate
phase
and
amplitude
estimates. At MMW frequencies, estimating the phase is a
for
major challenge, and the phase noise contribution from each
applications such as automotive collision avoidance systems.
component in the receiver must be considered. For our
The capability to penetrate articles of clothing and the high
performance specifications, we require that the timing jitter of
reflectivity contrast between the human body and metallic
the measured signal to be on the order of femtoseconds at the
objects make MMW imaging suitable for concealed weapons
carrier frequency. Rather than estimate the phase at the carrier
detection. Furthermore, advances in silicon processes have
frequency, we first mix down to an intermediate frequency
developed devices that are capable of operating at these
which will scale up the phase information and ease the
frequencies, which has led to the potential for low cost MMW
requirements on the phase estimation. When the input signal is
imaging provided that the MMW circuit design can meet the
mixed with the LO generated by the PLL, the noise from the
challenging performance specifications for these applications.
mixer, LNA, and PLL are added at the IF.
Fig. I shows the receiver architecture of an active imaging
For imaging applications, we expect a single tone signal as
system with potential use in automotive collision avoidance
opposed
applications. We target a pixel resolution of approximately
communications systems. This simplifies the noise analysis
to
a
broadband
signal
from
traditional
6cm for a 30m distance. The system will consist of an array of
and allows us to estimate the timing jitter contributed by the
lOOO receivers with per-antenna processor (PAP) units at a
LNA, mixer, and PLL before the signal is digitized.
carrier frequency of 770Hz. The 770Hz input signal will be
From the work presented in [ 1], the mixer has a conversion
downconverted by a mixer with a 760Hz local oscillator,
gain of 26dB and a noise figure of 14dB. We can calculate the
generated by a PLL, to obtain an intermediate frequency (IF)
increase in noise floor caused by this circuit. Using the
of 10Hz. This signal is digitized by an analog-to-digital
bandwidth of the mixer, we determine a noise power and then
converter that is sampling at twice the Nyquist frequency. The
estimate the mean squared voltage noise. Assuming the noise
digital
the phase and
is applied equally over the period of the sinusoid input, we
amplitude of the incoming signal and reduce the data rate to
divide the voltage noise by the expected slope at the zero­
the order of a kilohertz providing for easy low power
crossing to obtain an estimate of the timing jitter caused by the
logic
in each
PAP will
estimate
transmission off the array. A central processing unit (CPU)
mixer. For this mixer, the jitter is calculated to be about 40ps
will receive the data from each PAP in the array and perform
at the IF. We expect the LNA to have a gain of 20dB and a
digital beamforming with an expected frame rate of lOfps.
noise figure of 6dB at 770Hz [ 1]. Assuming a sinusoidal input
waveform, we can estimate the timing jitter due to the LNA to
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IMS 2010
be on the order of 90fs at the carrier frequency or 6.9ps at the
allowing one terminal of the varactor to be independently
IF.
biased, we can set that voltage to maximize the capacitance
These blocks contribute significant jitter but are still smaller
range of the MaS capacitor for a given voltage range of the
than what we expect from the PLL due to the challenges of
charge pump and passive loop filter, increasing the locking
designing low phase noise MMW frequency synthesizers. We
range.
require that the system, particularly the PLL, have low jitter
The VCO core is followed by a buffer stage that consists of
because jitter will corrupt the signal sent to the beamformer
an emitter follower and an emitter coupled pair. Transmission
and degrade the image quality. However, we will leverage the
lines were used for inductive peaking and to maximize output
oversampling from the IF to the kilohertz data rate to average
power to a 50n load. The buffer stage is biased independently
the estimates and reduce the error caused by phase noise by a
from the core to allow for better control of the output voltage.
factor
of
1000.
This
oversampling
can
relax
the
noise
specifications on the PLL to approximately 1ps of timing
jitter, which is 77ps at the IF. This paper describes the circuit
design to achieve this aggressive specification with a total
power dissipation of less than 100mW.
Out+
III. PLL ARCHITECTURE
There have been a number of MMW frequency synthesizers
that have been reported in the literature. PLLs at 600Hz have
been designed in both BiCMOS and CMOS technologies for
intended use in wireless communications [2] [3]. 770Hz PLLs
for automotive applications have been reported [4] [5]. This
design focuses on obtaining the desired jitter specification
while maintaining low power for use in the imaging array
system.
The PLL design uses a divide-by-5 12 integer-N architecture
Fig. 3.
shown in Fig 2. The reference clock is a 148MHz crystal
oscillator and the output is 760Hz.
B.
Schematic of cross-coupled yeO with capacitor feedback.
Frequency Divider Chain
76GHz
Fig. 2.
A.
Block diagram of PLL.
Voltage Controlled Oscillator
The schematic of the VCO is shown in Fig. 3. The VCO
core is a cross-coupled LC tank oscillator based on the design
presented in [ 1]. Capacitive coupling is used in the oscillator's
Fig. 4.
Schematic
inductive peaking.
of
the
first
frequency
divider
stage
with
feedback path. These capacitors act as capacitive dividers with
the c,t of the core transistors and allow for higher operating
frequency
and
output
power.
feedback,
the
transistor
Due
base
to
the
voltages
capacitors
could
be
in
set
independently and were biased with resistors. Transmission
lines were used to implement the inductance of the core. The
varactors were designed as a series connection between the
process's
accumulation
mode
MaS
capacitor
and
MIM
capacitors with the internal node resistively biased. Due to the
sensitivity to parasitic capacitances and inductances that may
conslstlOg
of
D-flipflops
in
a
master-slave
configuration. Static frequency dividers were chosen for their
wide bandwidth operation and robustness which we felt was
necessary despite the increased cost in power. The first seven
stages are created in emitter coupled logic and the last two are
designed in CMOS. The highest frequency divider utilizes
inductive peaking for increased operating frequency. The
inductors are planar spiral inductors created from the topmost
shift the VCO's center frequency, locking is a concern. By
978-1-4244-6057-1/101$26.00 C2010 IEEE
The divider chain has nine divide-by-2 static frequency
dividers
analog metal layer. The inductors were simulated using RFDE
1317
IMS 2010
Momentum and were sized with consideration given to the
simulated phase noise using CppSim. The total simulated
mutual inductance due to their close proximity to each other.
power dissipation is 97mW. At I MHz offset from the carrier,
Fig. 4 shows the circuit diagram of the first divider stage. The
the phase noise is simulated to be about -85dBc/Hz.
cascaded ECL divider stages are capacitively coupled. An
ECL-to-CMOS
conversion
circuit
is
used
to
transition
between the logic levels in the divider chain.
Fig. 6 is the layout of the design that was submitted for
fabrication. Particular care was placed in the layout of the
VCO core to ensure symmetry and to minimize parasitic
capacitances and
inductances.
Via
resistances
connecting
between the devices and the top analog metal used for
C.
transmission lines were also considered and minimized. The
Phase Detector/Charge Pump/Loop Filter
area of the PLL excluding bondpads is O.6mm by l.4mm.
A standard tri-state phase frequency detector was used to
compare the divider output and reference clock at 148MHz.
CppSim Simulated Phase Noise for Cell: plill_4, Lib: pll??_rev, Sim: test.par
The charge pump is a single-ended design with the switch
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placed at the source of the current sources and is based on a
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oxide transistors, which allowed these circuits to operate with
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divider chain, and also increased the voltage range of the
charge pump.
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A passive second order loop filter was implemented on
chip. The bandwidth of the loop filter was set to be 15MHz to
and
its
ancillary
PLL
Design
Assistant
were
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2.5V. This simplified the ECL to CMOS transition in the
CppSim
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the same voltage supply level as the VCO and ECL dividers of
balance the noise between the charge pump and VCO.
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removed to allow for a larger output swing to drive the VCO's
divider stages were implemented using the process's thick
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designed for I mA. In this design, the cascode devices were
varactors. The phase detector, charge pump, and CMOS
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Frequency Offset from Carrier (GHz)
Fig. 5.
Phase noise simulation of PLL using CppSim.
Fig. 6.
Die photo of PLL.
employed to determine the system dynamics and loop filter
characteristics [7].
IV. SIMULATION RESULTS
High-level full closed-loop simulations were performed
using CppSim. Verilog-A and SpectreRF were used for
simulation of individual blocks and smaller transient closed
loop simulations.
The transmission lines and interconnects in the VCO core
were
simulated
using
a
2.5D
EM
simulator,
RFDE
Momentum. The inductors in the first stage frequency divider
were also simulated in RFDE Momentum. Due to challenges
in
incorporating
the
generated
S-parameter
models
for
transient analysis in this simulation environment, the critical
components
were
replicated
by
using
the
design
kit
transmission line models and adjusting their parameters until
the
S-parameters
matched
the
simulated
ones
from
Momentum. These replicated models were then substituted
into the extracted design for more accurate simulations.
The VCO has a simulated output frequency range of
72.7GHz to 76.4GHz. The output power of the PLL is -3dBm.
The VCO core consumes
18mW while the VCO buffer
consumes 34mW from a 2.5V supply. The remaining PLL
circuitry consumes an additional 45mW. Fig. 5 shows the
978-1-4244-6057-1/101$26.00 C2010 IEEE
1318
IMS 2010
V. MEASUREMENT RESULTS
Testing
is
performed
at
a
probe
station
capacitors near the operating frequencies. Most of the rigorous
where
EM simulations were focused on the transmission lines of the
high­
VCO core rather than these capacitors. The routing to the
frequency GSG probes can directly probe the output of the
cross coupling capacitors and the vias required to reach the
PLL. Measurements are taken using an Agilent E4440A PSA
Series
Spectrum
Analyzer
with
the
Agilent
MIM capacitors in the varactors contributed significantly to
1 1970W
reducing the oscillation frequency of the VCO.
Waveguide Harmonic Mixer. The dies are packaged in an
open cavity QFN to minimize lead inductance for the DC
VI. CONCLUSION
signals while allowing for direct probing of the high frequency
signals. This packaging also allows for easier swapping of dies
A MMW PLL was designed and fabricated in IBM's
that are prone to damage due to probing. Voltage and current
BiCMOS8HP process as a key component in an active
sources are generated externally via circuitry on a printed
imaging
circuit board. Particular care was taken to bypass the supplies
system.
Preliminary
results
show
feasibility
to
achieve the specifications for this system. Further analysis and
and bias signals.
modeling is required to move the center frequency to 76GHz.
The operating range of the PLL is 64.25 to 68.84GHz. Due
to the change in frequency range, the reference clock is driven
by an Agilent 8247C signal generator. Fig. 7 shows phase
ACKNOWLEDGEMENT
noise measurement taken with a carrier frequency of 66.9GHz.
This work was funded in part by the FCRP Focus Center for
This result is a single-ended measurement taken from one of
Circuit & System Solutions (C2S2), under contract 2003-CT-
the differential outputs. The phase noise is -80.99dBc/Hz at
888. The authors also wish to acknowledge the Massachusetts
I MHz offset. The reference spur is visible at 130.6MHz and
Institute of Technology Center for Integrated Circuits and
was measured to be -33.8dBc. Assuming a reduction of 3dB in
Systems for funding.
phase noise by including the other differential output, we
integrate the phase noise to produce a timing
jitter of
approximately 825fs. The measured output power is -9.5dBm
REFERENCES
for a single ended output. Cables and waveguides account for
[1]
an additional 7.5dBm of loss. Accounting for a differential
output, the total output power is I dBm. The VCO core and
buffer dissipate 60.5mW. The remainder of the PLL consumes
46.lmW yielding a total power dissipation of 106.6mW. The
[2]
power consumption is larger than simulated because the
output buffer was boosted to provide enough power for
accurate
phase
noise
measurements
from
the
spectrum
[3]
analyzer.
I Carrier F req 66.89791451 GHz
[4]
[5]
[6]
[7]
Fig. 7.
J. D. Powell, H. Kim, and C. G. Sodini, "SiGe Receiver Front
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November 2008.
W. Winkler, 1. Bomgraber, B. Heinemann, and F. Herzel, "A
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H. Hoshino, R. Tachibana, T. Mitomo, N. Ono, Y. Yoshihara,
and R. Fujimoto, "A 60-GHz Phase-Locked Loop with Inductor­
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IEICE Transactions on Electronics, vol. E92-C, no. 6, pp. 785791, June 2009.
V. Jain, B. Javid, and P. Heydari, "A BiCMOS Dual-Band
Millimeter-Wave Frequency Synthesizer for Automotive
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Y. Kawano, T. Suzuki, M. Sato, T. Hirose, and K. Joshin, "A
77GHz Transceiver in 90nm CMOS," 2009 IEEE International
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M. Rhee, "Design of High-Performance CMOS Charge Pumps
in Phase-Locked Loops," 1999 IEEE International Symposium
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M. H. Perrott, CppSim Behavioral System Simulator,
http://www.cppsim.com.
Phase noise measurement at 66.90GHz output frequency.
The operating frequency is lower than simulated. This is
due to larger than expected parasitics from the components
and
interconnects
in
the
varactors
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and
cross-coupling
1319
IMS 2010