Silicon CMOS Ohmic Contact Technology for Contacting
III-V Compound Materials
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Citation
Pacella, N. Y., K. Mukherjee, M. T. Bulsara, and E. A. Fitzgerald.
“Silicon CMOS Ohmic Contact Technology for Contacting III-V
Compound Materials.” ECS Journal of Solid State Science and
Technology 2, no. 7 (May 31, 2013): P324–P331.© 2013 The
Electrochemical Society.
As Published
http://dx.doi.org/10.1149/2.015307jss
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P324
ECS Journal of Solid State Science and Technology, 2 (7) P324-P331 (2013)
2162-8769/2013/2(7)/P324/8/$31.00 © The Electrochemical Society
Silicon CMOS Ohmic Contact Technology for Contacting III-V
Compound Materials
Nan Y. Pacella,z Kunal Mukherjee, Mayank T. Bulsara, and Eugene A. Fitzgerald∗
Department of Materials Science and Engineering, Massachusetts Institute of Technology, Cambridge,
Massachusetts 02139, USA
Silicon (Si)-encapsulated III-V compound (III-V) device layers enable Si-complementary metal-oxide semiconductor (CMOS)
friendly ohmic contact formation to III-V compound devices, allowing for the ultimate seamless planar integration of III-V and Si
CMOS devices in a common fabrication infrastructure. A method of making ohmic contacts to buried III-V films using silicide
metallurgies has been established. NiSi/Si/III-V dual heterojunction contact structures are found to be optimal for integration. These
structures allow contact resistivities to be controlled by Si/III-V interfaces and eliminate interactions between the buried III-V device
and metal layers. Using a modified transmission line method (TLM) test structure fabricated using standard CMOS processing
techniques, the specific contact resistivities of Si/GaAs and Si/Inx Ga1-x As interfaces are extracted. The relationship between specific
contact resistivity and heterojuntion barrier width is considered. Among the structures tested in this work, p-type Si/GaAs and n-type
Si/Inx Ga1-x As yielded the lowest contact resistivities. Using the p-type Si/GaAs interface, a GaAs/Alx Ga1-x As laser with NiSi top
contact is demonstrated, confirming the feasibility of NiSi/Si/III-V contact structures for III-V devices.
© 2013 The Electrochemical Society. [DOI: 10.1149/2.015307jss] All rights reserved.
Manuscript submitted April 5, 2013; revised manuscript received May 15, 2013. Published May 31, 2013.
Integration of III-V compound (III-V) semiconductors with Si
complementary metal-oxide semiconductor (CMOS) has been an area
of great interest because of the circuit performance enhancement that
can be gained by placing Si and III-V devices in close spatial proximity. The Silicon-on-Lattice-Engineered Substrate (SOLES) platform
enables this integration monolithically. The SOLES wafer is a silicon wafer with an embedded template suitable for epitaxial III-V
device growth.1–3 CMOS devices are fabricated on the surface silicon
and III-V devices are built on the template layer in windows. In
collaboration with other groups, we have successfully demonstrated
differential amplifiers with InP heterojunction bipolar transistors
(HBT) and Si CMOS devices on SOLES substrates.4 In this previous work, Si and III-V contact metallization steps were performed
separately in traditional CMOS and III-V infrastructure, respectively. We envision parallel metallization of the CMOS and III-V
devices using common CMOS infrastructure, in a manner consistent with Si processing, as a final step toward ultimate monolithic
integration.
A few key requirements must be considered in choosing the optimal contact structure. Contacting the III-V films through a Si encapsulation layer which fully embeds the III-V device and minimizes
exposure of III-V materials to the CMOS sequence will cause the least
disruption to CMOS processes. This Si may be grown in an epitaxial step that is integrated with III-V device growth, streamlining the
growth process.
Using CMOS-friendly metals and processing steps which parallel
those currently found in CMOS processing will also ease the integration. This metal must have a thermal budget of formation that is
low to minimize effects on the III-V device structure. But the contact must also be able to withstand the temperatures of Si back-end
processing steps (typically temperatures up to 500◦ C). Nickel silicide metallurgies, which are standard to CMOS technology, have low
thermal budgets of formation and are used in more advanced CMOS
processes, are explored in this work for Si-encapsulated III-V ohmic
contacts.
Carrier transport between silicides and semiconductor films occurs
through a tunneling mechanism requiring the silicon-encapsulation
layers to be degenerately doped in order to promote tunneling. Tunneling may also occur via mid-gap interface states, which also affects
the band structure. In this work, we invoke similar methods for analyzing our contact structures between nickel silicide and Si-encapsulated
III-V films. The effect of mid-gap states could be especially important
in these contacts through Si-encapsulated III-V films because the lat∗
z
Electrochemical Society Active Member.
E-mail: nanyang@alum.mit.edu
tice mismatch between Si and III-V films leads to a large concentration
of defect states at the Si/III-V interface.
Experimental
In order to isolate the effects of contact metallization, nickel silicide contacts were made to Si-encapsulation layers grown epitaxially on bulk III-V substrates. Metalorganic chemical vapor deposition
(MOCVD) was used for epitaxial growth in this work because of
its scalability and high throughput. A Thomas Swan/Aixtron closecoupled showerhead reactor with the unique capability of growing
compound semiconductors and group IV materials in the same chamber was used. Silane (SiH4 ) and germane (GeH4 ) were the precursors
for group IV growth and are doped with mixtures of phosphine (PH3 )
or diborane (B2 H6 ) diluted in hydrogen. The precursors for compound semiconductor growth relevant to this work are trimethylgallium (TMGa), trimethylindium (TMIn), trimethylaluminum (TMAl),
and arsine (AsH3 ), with dimethylzinc (DMZn) and disilane (Si2 H6 )
as the p- and n-type dopants, respectively.
The contact structures were grown on epi-ready semi-insulating
(100) GaAs and (100) InP wafers. Hall Effect structures were grown
on undoped films (for example doped GaAs/semi-insulating GaAs
wafer or doped Si/undoped homoepitaxial GaAs/semi-insulating
GaAs wafer) to confirm active carrier concentrations in each of the
layers of interest.
Contacts to GaAs were fabricated with degenerately doped Si on
degenerately doped GaAs homoepitaxial layers whereas contacts to
Inx Ga1-x As were fabricated with the following structure: degenerately doped Si/degenerately doped Inx Ga1-x As/homoepitaxial InP/InP
substrate. In0.53 Ga0.47 As was the composition chosen in this work because of its importance in electronic devices due to its lattice match
with InP. The degenerate doping enables tunneling between the silicide and III-V films. All carrier concentrations are determined by
Hall Effect measurements of single layer films grown on undoped
substrates.
In the Si/GaAs structures, Si is grown on Ga-terminated GaAs surfaces, achieved by baking the GaAs substrate in N2 without an AsH3
overpressure for 2 minutes at 650◦ C before introducing SiH4 , following the work of Bai, et al. for direct deposition of Ge on GaAs.5 The
same procedure could not be applied to growth of Si on In0.53 Ga0.47 As
due to In0.53 Ga0.47 As decomposition and In droplet formation. Instead, another technique employed by Bai, et al. was used.5 The
In0.53 Ga0.47 As film was cooled to 400◦ C under AsH3 overpressure,
and baked without the AsH3 overpressure prior to SiH4 introduction.
Because SiH4 decomposition at 400◦ C is extremely low, the temperature was gradually raised to 650◦ C at 1.7◦ C/minute in the presence of
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ECS Journal of Solid State Science and Technology, 2 (7) P324-P331 (2013)
Figure 1. Schematic of TLM fabrication sequence for (a) NiSi/Si control
structures and (b) NiSi/Si/III-V dual junction structures. (1,2) Mesas and contact areas are defined through etching. (3) Front-sides of the wafers are encapsulated in blanket PECVD SiO2 and holes are etched in the SiO2 to define
silicide contact pads. (4) Blanket Ni is E-beam evaporated onto the samples and
the samples are annealed to form nickel silicide in the SiO2 holes. Unreacted
Ni is removed in a wet etch. (5) Finally, E-beam evaporated Al is deposited
and patterned.
SiH4 gas flow. This method avoids decomposition of the In0.53 Ga0.47 As
film and produces a continuous Si thin film encapsulated surface.
Silicide metallurgies are a function of metal thickness and anneal
temperature. In the first part of this work, optimal contact metallurgies
for III-V/Si integration were evaluated by considering structural and
electrical properties of different silicide structures constructed on degenerately doped n-type Si films/n-type GaAs substrates. These films
were grown on n-type GaAs substrates to enable conduction through
the wafer and isolate the characteristics of a single NiSi to GaAs contact. Blanket back side-contact to these structures was made with a
NiGeAu alloy, a traditional III-V metallization material. Nickel was
E-beam evaporated on the front-side of the wafers and patterned in
a lift-off process. Various thicknesses of Ni were deposited, which,
after rapid thermal anneal (RTA), resulted in varying silicide reaction
depths. For contact isolation, the unreacted Si and degenerately doped
GaAs were etched, with the silicide serving as a self-aligned mask.
´ and target Ni
For this part of the work, the Si thickness was 900 Å
´
´
´
thicknesses were 200 Å, 600 Å and 900 Å.
I-V characteristics were measured through the wafers in order to
gain a qualitative understanding of whether the junctions between each
silicide metallurgy and GaAs produced ohmic or rectifying behavior.
The silicide was probed directly without the aid of an Al currentspreading layer for fabrication simplicity. Metallurgical properties of
these silicides were determined with cross-sectional transmission electron microscopy (TEM), X-ray diffraction (XRD) and secondary ion
mass spectroscopy (SIMS) analysis of unpatterned silicide samples.
2θ-ω XRD scans were taken between 2θ of 30◦ and 60◦ ; diffraction
peaks were compared against tabulated powder diffraction files for
phase identification. Through this analysis, the optimal metallurgical
structure for integration was identified.
The specific contact resistivity, ρc , is extracted for silicide ohmic
contacts to n- and p-type GaAs and Inx Ga1-x As films using the aforementioned optimal metallurgical structure. Determination of ρc was
based on the transmission line model (TLM). The traditional TLM
structure was modified in such a way as to allow determination of
NiSi to III-V film contact resistivity while maximizing CMOS processing compatibility. Si encapsulation layers and GaAs or Inx Ga1-x As
films were grown epitaxially on semi-insulating GaAs substrates in
order to confine current flow to a degenerately doped channel layer.
The fabrication process for these TLM test structures is detailed in
Figure 1. Figure 1a shows the fabrication sequence on Si control
samples with Si channel. These samples include Si substrates ionimplanted to 1e20 cm−3 with arsenic, as well as MOCVD-grown
n+ and p+ Si layers on undoped GaAs. Figure 1b shows the fabrica-
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Figure 2. Schematic illustrating Si-encapsulated 851 nm GaAs/AlGaAs quantum well (QW) graded-index separate confinement heterostructure (GRINSCH) laser structure.
tion process on the actual Si/III-V samples with degenerately doped
III-V films as the conductive channel.
The first steps of the process include (1,2) etching isolated mesas,
defining contact areas and exposing or removing III-V films. (3) After
etching, front-sides of the wafers are encapsulated in blanket PECVD
SiO2 for test structure isolation and holes are etched in the SiO2 to
define silicide contact pads. The rest of the fabrication process is
similar to a standard CMOS salicide (self-aligned silicide) process:
(4) Blanket Ni is E-beam evaporated onto the samples and annealed
to form nickel silicide in the SiO2 holes. The Ni deposited on top of
the SiO2 does not react and is removed in a wet etch that is selective to
silicide. Finally, (5) E-beam evaporated Al is deposited and patterned
in order to promote current spreading across the NiSi pads and to
facilitate contact probing.
Using the optimal p-type contact with the lowest ρc , a quantum well
(QW) graded-index-separate confinement heterostructure (GRINSCH) GaAs/AlGaAs oxide-stripe laser with CMOS-compatible silicide front-side contact was demonstrated. The laser structure is illustrated in Figure 2 and has 1.5 μm cladding layers (Al0.5 Ga0.5 As),
125 nm undoped GRIN-SCH layers (Al0.5 Ga0.5 As to Al0.3 Ga0.7 As),
followed by a 25 nm undoped SCH (Al0.3 Ga0.7 As), and a 10 nm
undoped quantum well (GaAs). It is then capped with degenerately
doped GaAs and Si to enable silicide contact formation. The target
doping for the cladding layers was 1e18 cm−3 and the laser structure was grown on n-type GaAs substrates in order to simplify device
fabrication and to allow for a front-to-back contacted device. (For
fabrication simplicity, back side contact was made using NiGeAu, a
traditional III-V metallurgy)
Edge-emitting oxide stripe lasers were made by first etching the
Si and GaAs layers into laser stripes for carrier confinement. Silicide front-side contacts were then made using the same fabrication
procedure as for the TLM test structures: SiO2 passivation, nickel
silicide formation and Al contact pad deposition (comparable to
Figure 1, steps 3 to 5). Similar structures, but with traditional III-V
metallurgy (TiPtAu) for front-side contact, were fabricated in parallel
for comparison.
In order to facilitate cleaving of these wafers into laser bars and
lower the overall series resistance through the bulk GaAs substrate,
the GaAs substrate was polished to a final thickness of approximately 100–150 μm. Blanket back side contact is made by depositing
NiGeAu using E-beam evaporation and annealing. The wafers were
then cleaved into laser bars and mounted on a copper heat sink using
solder for testing. Lasers were tested as-cleaved, with no additional
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ECS Journal of Solid State Science and Technology, 2 (7) P324-P331 (2013)
Figure 3. Cross-sectional TEM images of in-situ deposited epitaxial,
monocrystalline structures of Si on GaAs.
anti-reflective coatings on the facets. The front-side was probed directly with a tungsten probe tip whereas the back side was contacted
through the solder.
Lasers were tested at room temperature without additional temperature control. A Melles Griot Model 06DLD203A Diode Laser Driver
provided the input current and Agilent 33250A Function Generator
enabled pulsed operation. Output optical signals were collected with a
multimode fiber coupled to one of the laser facets. Laser spectra were
determined using an Ocean-Optics HR4000 CG-UV-NIR High Resolution Spectrometer. Laser power was measured with a Thor Labs
PDA36A Si Amplified Photodetector. Because continuous mode laser
operation saturated the photodetector power was measured in pulsed
mode using a 2 μs pulse width and 0.2% duty cycle. The peak intensity
of the power was recorded for each input current.
Results
A cross-sectional TEM image of Si-encapsulated GaAs is shown in
Figure 3. N-type and p-type Si-encapsulated GaAs and In0.53 Ga0.47 As
films look comparable, although with different degrees of surface
roughness. The growth of Si on III-V is epitaxial, monocrystalline
and continuous, despite high lattice mismatch between the two films.
Carrier concentrations for the films used in this work, as determined by
Hall Effect measurements, are shown in Figure 4. Degenerate doping
levels were achieved in each of the films.
Cross-sectional TEM images of various silicide on n-type Si/GaAs
films are shown in Figure 5, adapted from Pacella et al.6 With increasing thickness ratios of Ni:Si, the reaction depth of silicide into
the Si/GaAs structure increases. At an initial Ni:Si thickness ratio
of 2:9, only part of the Si reacts and the GaAs underneath appears
unperturbed, as seen in Figure 5a for a film annealed at 450◦ C for
5 minutes. Two internal heterojunctions are formed (silicide/Si and
Si/GaAs) and through-wafer I-V curves indicate that both junctions
are ohmic. When Ni:Si thickness ratio is increased to 2:3 and annealed
at 450◦ C for 5 minutes, all of the Si is consumed, as seen in Figure 5b.
The silicide/GaAs interface appears to be flat, suggesting that, once
again, there is little reaction between the silicide and underlying III-V
film. In this case, however, the interface becomes rectifying. Finally,
with a Ni:Si thickness ratio of 1:1, Ni appears to react with the un-
Figure 4. Active carrier concentration in epitaxial Si, GaAs and
In0.53 Ga0.47 As films determined by Hall Effect measurements.
Figure 5. Cross-section TEM images of Ni/Si/GaAs with (a) 2:9 Ni:Si, (b) 2:3
Ni:Si thickness ratio after rapid thermal anneal (RTA) at 450◦ C for 5 minutes
and (c) 1:1 Ni:Si after RTA at 600◦ C for 5 mintues, adapted from Pacella
et al.6
derlying GaAs. Figure 5c shows the structure after 5 minute anneal
at 600◦ C. (The metallurgical structure for the same sample annealed
at 450◦ C can be seen in Figure 8.) Not only is all of the Si consumed
in the reaction, but additional, smaller grains are observed just above
the GaAs. The I-V data indicate this type of contact is ohmic.
Discussion
Si/III-V epitaxial structure.— The successful continuous epitaxial
growth of Si on III-V films indicates that III-V films can be wholly
encapsulated with Si. As noted previously, n-type Si caps have higher
surface roughness than p-type Si caps. This roughness is consistent
with previous observations and has been attributed to surface segregation of P atoms during growth.7,8 Micro-scale roughness should not,
however, affect the ability to fabricate ohmic contacts. Carrier concentrations in the Si and III-V films are critically important to ohmic
contact formation. It is especially important to determine if there is
any cross-doping between the various epitaxial layers because Si is
an n-type dopant for III-V films and group III and group V elements
are p- and n- type dopants in Si respectively.
Ga and As concentration profiles within Si films of two different
growth rates are shown in Figure 6. These SIMS profiles are taken
by topside sputtering through the Si layer. In Figure 6a, the growth
rate of Si is 2.8 nm/s (this corresponds to the growth rate in undoped
and p+ Si films) whereas in Figure 6b, the growth rate has been suppressed by a factor of 40 (this is for n+ Si). Ga concentrations in both
samples are around 1e18 cm−3 and may be the result of an exchange
mechanism, as has been theorized for Ge on GaAs.9 It is interesting, however, to note that arsenic concentrations are much higher in
films with faster Si growth rate. This data supports Bai, et al.’s theory
that As incorporation is due to desorption of volatile As-containing
compounds from the MOCVD reactor ambient.9 In this case, arsenic
species remain from growth of the GaAs homoepitaxial layer and
incorporates into Si growth. A reduced Si growth rate for the n+ Si
film enables the As-containing species to be purged out of the system
and suppresses arsenic incorporation into the silicon film. In order
to lower arsenic incorporation in p-type Si films with faster growth
rate, a reactor chamber purge might be implemented. Note that high
arsenic concentrations have not affected the overall ability to degenerately dope Si films p-type, (the measured carrier concentrations in
p-type Si were 1.90 ± 0.05e20 cm−3 ). III-V structures that have been
encapsulated with these Si films can then be migrated into CMOS
fabs.
A SIMS scan showing Si concentration in GaAs is presented in
Figure 6c. This data was taken from a p-Si/p-GaAs sample where the Si
encapsulation layer was removed via a dry etch. The apparent Si spike
at the top of the GaAs can be due to 1) Si diffusion10–14 or 2) incomplete
removal of the Si cap layer, combined with surface roughening from
dry etching prior to SIMS. The repercussion of possible Si diffusion on
ohmic contact formation rests on whether the diffusing Si is neutral10,15
or negatively charged.13,16 For p-type contacts, in-diffusion of charged
Si species may not be desirable because it can potentially counter-dope
the III-V film. At worst, it can render the top surface of the III-V film
n-type, creating a barrier at the p-type Si/III-V interface. As will be
shown later, if this interfacial layer exists, it does not affect the ohmic
behavior of the contact although it may affect contact resistance.
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ECS Journal of Solid State Science and Technology, 2 (7) P324-P331 (2013)
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Figure 7. X-ray diffraction (XRD) patterns for the Ni/Si/GaAs structures
shown in Figure 5, and tabulated NiSi (black) and Ni2 Si (gray) reference
peaks. X-ray peaks can be correlated with the references to determine the
phases present in each sample. A transition from NiSi to Ni2 Si is observed
with increasing Ni:Si thickness ratio.
Figure 6. Concentration profiles of As (black) and Ga (gray) in epitaxially
grown Si/GaAs structures with 40x difference in Si growth rate: (a) undoped Si
grown at 2.8 nm/s and (b) n-type Si with slower growth rate. (c) Concentration
profile of Si in p-type GaAs substrate. The Si/GaAs interface position is set to
zero.
Ni/Si/GaAs metallurgical reactions.—Ni:Si thickness ratio of 2:9.—
When “thin” Ni is deposited on a Si/GaAs structure, Ni reacts with Si without affecting the underlying GaAs as shown in
Figure 5a. This Si/GaAs interface stability is consistent with previous
observations.17,18 The restriction of the silicide reaction to occurring
between Ni and Si (i.e., no reaction with underlying GaAs) allows
for standard CMOS processing techniques to be applied with NiSi
phase formation determined by anneal temperature: At low temperatures (below 250–300◦ C), Ni diffuses into Si to form Ni-rich phases
such as Ni2 Si. At moderate temperatures (between 300◦ C and 700◦ C),
NiSi forms through a reaction of 1 nm Ni + 1.86 nm Si resulting in
2.22 nm NiSi. Finally, NiSi2 nucleates at higher temperatures.19,20
XRD 2θ-ω results for our films with initial Ni:Si thickness ratio of 2:9
and RTA temperature of 450◦ C is shown in black in Figure 7. The only
2θ peaks detected in XRD correspond to the expected X-ray signature
of NiSi, confirming that NiSi is the only phase. Additionally, SIMS
revealed that there is no additional out-diffusion of Ga or As after
NiSi formation.
Ni:Si thickness ratio of 2:3.—When the Ni:Si thickness ratio is increased to approximately 2:3, all of the Si is consumed after annealing. For temperatures up to 450◦ C, the interface appears abrupt and
the GaAs underneath the Si unperturbed, as shown in Figure 5b.
In this case, the atomic ratio of Ni:Si is approximately 5:4 and
XRD 2θ-ω scans of these samples after RTA, Figure 7, reveal
that a combination of Ni2 Si (gray X-ray peaks) and NiSi (black
X-ray peaks) have formed. The relative strength of the Ni2 Si signal versus the NiSi signal suggests that there are more Ni2 Si grains
than NiSi.
Ni:Si thickness ratio of 1:1.—With a further increased Ni:Si thickness
ratio of 1:1, there is an interaction with the underlying GaAs. The
calculated Ni:Si atomic ratio is 1.84 to 1. For this metallurgy, XRD
2θ-ω scans reveal that Ni2 Si is the predominant phase formed at
temperatures between 450◦ C and 600◦ C; no NiSi peaks are detected
at all, as seen in the gray curve in Figure 7. The peak at 2θ = 33.9◦ is
neither Ni2 Si nor NiSi but may be attributed the [101] plane of NiAs.
Additional TEM and XRD data for the phase evolution of this sample
as a function of RTA temperature is presented in Figure 8. At 450◦ C,
a thick Ni2 Si layer and thinner secondary layer are seen in Figure 8b.
The interface between these two layers is relatively flat and demarked
by a white line in the figure. When the anneal temperature is increased
to 600◦ C, the thickness of the Ni2 Si remains approximately constant
but the flat boundary between Ni2 Si and the secondary layer breaks
down (Figure 8c). This secondary layer also breaks into distinct grains,
accompanied by an increase in the intensity of the NiAs XRD peak
at 2θ = 33.9◦ . When the anneal temperature is further increased to
Figure 8. Phase evolution of films with 1:1 Ni:Si thickness ratio after RTA.
(a) XRD peaks of silicide films after 450◦ C, 600◦ C, and 700◦ C anneal for
5 minutes, indicating disappearance of a peak at 33.9◦ and appearance of a
peak at 31.5◦ between 600◦ C and 700◦ C. Overlaid on this experimental data are
tabulated peak positions from powder diffraction files which indicate possible
origins of each peak. Cross sectional TEM images of the films (from bottom
to top) after (b) 450◦ C anneal, (c) 600◦ C anneal and (d) 700◦ C anneal also
reveal that a buried phase disappears between 600◦ C and 700◦ C. The white
line in (b) indicates the original location of the Si/GaAs interface.
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ECS Journal of Solid State Science and Technology, 2 (7) P324-P331 (2013)
Figure 10. Current path and equivalent circuit in the contact edge for (a)
NiSi/Si single junction contact and (b) NiSi/Si/III-V dual junction contact
structures. The Si edge that overhangs NiSi in the NiSi/Si/III-V structure gives
rise to many equivalent current paths that must be represented in the equivalent
circuit. This added complexity makes evaluating the dual junction contacts
using the standard TLM method invalid.
Figure 9. Schematic of the interactions which may occur in Ni/Si/GaAs films
with 1:1 Ni:Si ratio with annealing.
700◦ C, the XRD peak at 33.9◦ disappears, as does the secondary layer
beneath the Ni2 Si. Coarsening occurs in the Ni2 Si grain structure,
leaving a bamboo structure which can be seen in the TEM image in
Figure 8d. A very strong peak at 2θ = 31.5◦ also appears. This peak
is most likely due to a surface oxide and can be attributed to either the
[220] plane of Ni2 SiO4 or the [102] plane of SiO2 . Cross-sectional
TEM images confirm the presence of a thin film on top of the Ni2 Si,
(Figure 8d).
A schematic of possible interactions which may give rise to these
film structures is shown in Figure 9. At 450◦ C the Si and GaAs layers
stay relatively stable with Ni diffusion dominating silicide formation,
similar to nickel silicide formation in CMOS.19–21 Excess Ni diffuses
beyond the Si layer and reacts with the underlying GaAs. In thin film
reactions between Ni and GaAs, both NiAs and NiGa are known to
form.22,23 However, the lack of NiGa peaks in the X-ray data may be
due to 1) NiGa grains being too small or too few to detect or 2) their
non-existence. We suspect that there is far less NiGa than NiAs in the
sample because the Ga easily diffuses into the Ni2 Si, leaving regions
of excess As. After a 5 minute anneal at 450◦ C, gallium incorporation
in the silicide is already higher than the arsenic, not shown. At 600◦ C,
this disparity might be even more pronounced.24 The result would
be an excess of arsenic atoms at the GaAs/Si interface which can
react with Ni to form NiAs. At 700◦ C, in contrast, arsenic diffusivity
in Ni2 Si increases substantially and diffusion into the Ni2 Si grains
occurs.24 Additional grain growth in the Ni2 Si can be seen and the
NiAs grains are absorbed into the silicide.
Ni/Si/GaAs electrical characteristics.— Two metallurgical structures result in ohmic contacts, one with partial Si consumption (2:9
Ni:Si thickness ratio) and one with reaction into the GaAs (1:1 Ni:Si
thickness ratio). The former must consist of two ohmic tunnel junctions, a NiSi/Si and a Si/III-V junction. The NiSi/Si junction is a
CMOS standard and akin to a metal-semiconductor junction, with its
ohmic behavior determined by doping in the semiconductor (Si). The
Si/III-V interface, on the other hand, is established epitaxially and
carrier conduction occurs because the semiconductors on either side
are degenerately doped.
For the structure where all the Si is consumed in the silicide reaction but GaAs remains stable (2:3 Ni:Si thickness ratio), a rectifying
junction is formed. Rectification at this interface suggests that an additional barrier to carrier conduction exists at the silicide/GaAs junction,
possibly because additional trap states are induced by direct contact
between silicide and GaAs.
In the samples where excess Ni enables reaction with both Si
and GaAs (1:1 Ni:Si thickness ratio), an ohmic contact is formed.
This behavior may be expected because ohmic contacts have been
formed using Ni thin films on GaAs in the past.23 For these samples,
interaction between Ni and GaAs may eliminate trap states at the
silicide-GaAs interface.
Between the two metallurgies that give rise to ohmic contacts,
the configuration with partial Si consumption is more optimal for
integration with CMOS because it is a simpler structure that is much
better understood. In contrast to the complex metallurgy of Ni reaction
with both Si and GaAs, the silicide phase of the Ni-Si reaction is
determined solely by anneal temperature. In addition, for CMOS,
NiSi is preferred over Ni2 Si because it has lower sheet resistance. The
relatively wide temperature window for formation of the NiSi phase
in the NiSi/Si/III-V structure enables additional processing flexibility.
Given that the properties of the NiSi film and NiSi/Si interface are well-known CMOS standards, the Si/III-V internal heterointerface becomes the main challenge to address when considering
the NiSi/Si/III-V structure for III-V/CMOS device integration. We
further studied contact resistivities across MOCVD-grown Si/III-V
interfaces. To our knowledge, the only other study of directly contacting GaAs with Si was by Kavanagh, et al., where amorphous
hydrogenated Si was deposited on GaAs and annealed to form polycrystalline Si. However, much lower doping concentrations used in
the previous work resulted in ρc in the 1e-4 -cm2 range.25
Specific contact resistivity of NiSi/Si/III-V structure.— The modified TLM structure shown in Figure 1 was used to determine ρc
of the NiSi/Si/III-V structures. If standard TLM formulas are used,
NiSi/Si/GaAs dual junction contacts appear to exhibit ρc below 1e-6
-cm2 . However, this standard analysis method assumes a simplification in the equivalent circuit model that cannot be used here. The
current path and equivalent circuit is shown in Figure 10a. Because the
metal (NiSi) contact has much higher conductivity than the semiconductor channel underneath, a simplification is typically made that there
is no potential drop in the metal contact. This assumption is acceptable
for NiSi/Si single junction contacts where Si is the conduction channel. The ρc for these NiSi/Si interfaces (with n-type ion-implanted Si
and epitaxially-grown n+ and p+ Si on undoped GaAs) are shown in
Figure 11a. All NiSi/Si interfaces have ρc below 1e-6 -cm2 . Since
doping concentrations in all samples are between 1–2e20 cm−3 , even
better ρc might be expected with further improvements via a more
established industrial fabrication process.
The dual junction NiSi/Si/III-V contact structure, however, is far
more complex because the Si and III-V now have comparable sheet
resistivities that convolute ρc analysis. The current path between the
III-V channel and NiSi contact is shown schematically in Figure 10b.
As compared to a simple NiSi/Si contact, there are now many equivalent current paths between the III-V channel and NiSi contact due to
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ECS Journal of Solid State Science and Technology, 2 (7) P324-P331 (2013)
P329
Figure 12. Possible band diagrams for (a) n-Si/n-GaAs, (b) n-Si/n-InGaAs
and (c) p-Si/p-GaAs, using the electron affinity rule for band alignments. The
gray curves are ideal band diagrams without interface states whereas the black
curves show band bending with the introduction of interface states. EF crosses
the energy axis at 0 eV and is depicted as a dashed line (---).
Figure 11. ρc of (a) NiSi/Si junction and (b) Si/III-V junction, as determined
by fitting data to an equivalent circuit model () and/or extrapolating contact
resistance of samples without a Si edge ().
the Si edge that extends beyond NiSi, labeled dSi_edge in the schematic.
These additional current paths must be represented in the equivalent
circuit. In order to accurately extricate ρc of Si/III-V from that of
NiSi/Si, two methods are employed.
First, a 1D 700 resistor equivalent circuit of the NiSi/Si/III-V contact was built using the Quite Universal Circuit Simulator (QUCS).
This model mimics the equivalent circuit shown in Figure 10b and
discretizes the contact structure into small sections of length δx. In
this model, the contact resistance between Si and III-V films is the
only unknown parameter. The total contact resistance, Rc, is extracted
from the modified TLM structure. Discretized sheet resistances of the
Si and III-V layers, δRs(Si) and δRs(III-V) , are extracted from Hall Effect measurements and discretized contact resistances of the NiSi/Si
junction, δRc(NiSi/Si), are determined from NiSi/Si single junction samples. With these input parameters, ρc is determined for a variety of
ohmic Si/GaAs and Si/In0.53 Ga0.47 As interfaces. Results are shown in
Figure 11b.
For some of the samples, an additional method of extracting ρc was
developed for comparison. A mask with TLM structures containing
similar contact areas but different lengths for the Si edge, dSi_edge,
was used. By comparing total Rc with dSi_edge , the value of Rc when
dSi_edge shrinks to zero was determined. Standard TLM formulas were
used to determine total ρc of the NiSi/Si/III-V dual junction stack,
from which ρc of the NiSi/Si junction could be subtracted to enable
determination of the Si/III-V single junction ρc . The data obtained
from this experimental method is overlaid on the data from modeling
in Figure 11b and shows good agreement.
The experimental extraction of ρc (by altering dSi_edge ) has some
advantages over extracting ρc using the QUCS model. It is less reliant
on accurate determination of the Si and III-V sheet resistances and
NiSi/Si contact resistance, which must be inputted into the equivalent
circuit model. However, because multiple TLM structures must be
measured in order to extract each ρc , it does require more resistance
measurements and a larger footprint on the wafer.
Understanding specific contact resistivity of the Si/III-V
interface.— Values of ρc for Si/III-V junctions studied in this work
range from below 1e-6 -cm2 to upwards of 8e-3 -cm2 . These contact resistances suggest a barrier to carrier transport at the Si/III-V
interface, despite degenerate doping on both sides of the interface.
A closer look at band alignments at the Si/III-V interface enabled
determination of the source of this barrier.
There is some disagreement in literature about the precise band
alignment between Si and III-V films. The most basic theory for predicting band alignments is the electron affinity model, which predicts
a conduction band offset, Ec , of 0.02 eV and valence band offset,
Ev , of 0.29 eV between Si and GaAs. (A literature review of heterojunction band alignment at the Si/GaAs interface suggests Ev
spanning 0.03 eV and 0.38 eV.26–35 This spread in band alignment
values is thought to exist because the electron affinity rule is an ideal
case but interface states, dipole interactions, strain, and surface reconstructions present non-idealities which modify band alignment from
this ideal.36 )
In this work, band alignments are modeled in 1D using nextnano, a
Poisson solver, using the electron affinity rule as a basis. The simulated
band alignments for Si on GaAs and In0.53 Ga0.47 As films are presented
in Figure 12. The band alignments shown in gray assume no Fermi
level, EF , pinning at the interface and negligible barriers to carrier
transport. This suggests that ρc should theoretically be low for all
of the heterojunction combinations. The higher ρc actually found in
this work indicates that an additional barrier at the interface exists.
If interface states pin EF , we predict the band alignments shown in
black. For n-type contact structures, EF is pinned at the energy of
donor states, 0.75 eV and 0.50 eV above the valence band for GaAs
and In0.53 Ga0.47 As, respectively, as found by Spicer et al.37 and Grillot
et al.38 For these n-type structures, interface states can produce a
substantial barrier to electron conduction at the Si/GaAs junction,
producing a high ρc . On the other hand, even with a pinned EF , there
is a much smaller barrier at the n-type Si/In0.53 Ga0.47 As interface and
much lower ρc . This lowering of ρc with the addition of In to GaAs, by
reducing the barrier between the Si and III-V film, was also predicted
by Woodall and Freeouf.39
Similar analyzes may be performed with the p-type films, using
the assumption that EF is pinned at the energy of acceptor states
(0.5 eV and 0.25 eV above the valence band for GaAs and
In0.53 Ga0.47 As, respectively37,38 ). The band alignment for p-type
Si/GaAs is shown in Figure 12c. Valence band discontinuity results
in a smaller depletion region on the Si side of the p-type Si/GaAs
interface. In addition, defect states pin the Fermi level closer to the
valence band for p-type samples than the conduction band for n-type
samples. These factors lead to a smaller barrier and lower ρc for p-type
Si/GaAs contacts than n-type Si/GaAs contacts.
For the p-type contacts, an additional possibility of Si in-diffusion
into the III-V film (suggested in Figure 6) must also be taken into
account. The small ρc of the p-type Si/GaAs junction suggests that
Si in-diffusion is not a major concern for this structure. However, ptype Si/In0.53 Ga0.47 As has much higher ρc, suggesting a larger barrier,
which may result from Si in-diffusion. Note the different Si growth
procedures that were used for the two films.
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P330
ECS Journal of Solid State Science and Technology, 2 (7) P324-P331 (2013)
Figure 13. ρc as a function of expected depletion width, xd . (a) In gray,
Stavitski et al.’s data for NiSi/n-Si (), PtSt/n-Si (), NiSi/p-Si () and
PtSi/p-Si () contacts are shown41 with xd calculated using literature values
for the silicide/Si barrier heights. The ρc of Si/III-V contacts investigated in
this work is also shown (). xd for these points are calculated from nextnano
simulations with Fermi level pinning. (b) Numerical values for these ρc
and xd.
The ρc across a metal-semiconductor barrier depends on barrier
height, B , carrier density in the semiconductor, N, dielectric constant
of the semiconductor, εs , and tunneling effective mass, m* tun . For field
emission,40
4πφ B εs m ∗tun
ρc ∝ exp
,
[1]
h
N
where h is Planck’s constant. ρc is often quantified as a function of
N because the barrier to current conduction results from band bending in the semiconductor layer. For a semiconductor-semiconductor
junction, band bending in both semiconductor layers contribute to
the interface barrier. To better understand ρc and draw comparisons
between metal-semiconductor data in literature and semiconductor
heterojunction data found in this work, we consider ρc as a function
of depletion width, xd . ρc can be re-written as
πxd 8m ∗tun φ B
ρc ∝ ex p
.
[2]
h
In Figure 13, ρc and xd for the semiconductor heterojunctions
measured in this work are overlaid on NiSi/Si and PtSi/Si data from
Stavitski et al.41 The xd at NiSi/Si and PtSi/Si interfaces are calculated
using literature values for barrier heights (0.67 eV for NiSi/n-Si,42,43
0.95 eV for PtSi/n-Si,44 0.45 eV for NiSi/p-Si42 and 0.24 eV for
PtSi/p-Si45 ). The general trend shows thinner xd resulting in lower ρc .
Therefore, we deem xd a good predictor of ρc at Si/III-V heterojunction
interfaces.
Laser with CMOS-metal front-side contact.— In order to demonstrate the feasibility of these NiSi/Si/III-V contacts on a functional
device, a laser with silicide front-side contact was fabricated. Though
a laser is not the most rigorous test of contact metallurgies, it provided
a simple way to provide a proof of concept. The Si/GaAs heterojunction forms the p-type contact with lowest ρc and was therefore the
heterojunction used for this laser demonstration. The device characteristics of these GaAs/AlGaAs laser structures fabricated using
silicide versus TiPtAu contacts are shown in Figure 14. For a laser
with silicide contact, the I-V characteristic is shown in Figure 14a, the
spectra before and after the onset of lasing, is shown in Figure 14b and
its current density, J, versus power, P, is shown in Figure 14c. Lasing
is achieved with room temperature continuous wave operation. As
mentioned above, because continuous wave operation saturated the
photodetector, power was measured in pulsed mode. Similar device
characteristics are found in devices contacted with silicide versus TiPtAu metallurgies. The series resistance, Rs , of both types of devices
is 4.4 ± 0.2 and the threshold current densities, Jth , is 3.9 ± 0.3
kA/cm2 for devices 4.5 μm to 7.6 μm wide and 510 to 530 μm long.
These lasers demonstrate the feasibility of NiSi/Si/III-V contacts for
current injection into laser devices.
Figure 14. Device characteristics of GaAs/Alx Ga1-x As lasers with silicide
front-side contacts: (a) I-V curve, (b) current density, J, versus power with
threshold current densities, Jth , for lasing indicated and (c) spectra below
(gray) and above (black) Jth . (d) Jth of lasers with silicide and TiPtAu frontside
contact, indicating comparable device performance. Optical data collected in
pulsed mode with 2 μs pulsewidth and 0.2% duty cycle to prevent saturating
the spectrometer.
Conclusions
A method of making contact to III-V films, which enables parallel
interconnection of III-V and CMOS devices, has been established.
III-V films can be fully encapsulated with degenerately doped epitaxial Si grown at 650◦ C. Nickel silicide can be used to contact the
III-V films through this Si encapsulation layer. The NiSi/Si/III-V dual
heterojunction structure enables contact formation without disturbing the buried III-V layers when thicknesses of the Ni and Si are
properly chosen. The specific contact resistivity of the NiSi/Si/III-V
contact structure has been found to be a function of barrier widths
at the Si/III-V interface. In this work, p-type Si/GaAs and n-type
Si/In0.53 Ga0.47 As have been found to yield the best contact resistivities. We demonstrated our contact scheme by fabricating a Si encapsulated GaAs/Alx Ga1-x As QWGRIN-SCH laser with silicide front-side
contact that performed equivalently to the same structure with a traditional III-V compound metallization scheme. Further exploration of
similar contacting schemes to a wider range of III-V films, such as
phosphide- or nitride-based films, may further our understanding of
Si/III-V interfaces, providing even greater flexibility in ohmic contact
design for full monolithic integration.
Acknowledgments
This work was funded by Raytheon Integrated Device Systems
and made use of MIT MTL and CMSE facilities.
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