System Development Platform
User Guide
Revision 1.2, November 2010
Part Number
82-100110-01
Analog Devices, Inc.
One Technology Way
Norwood, Mass. 02062-9106
a
Copyright Information
© 2010 Analog Devices, Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any form without prior, express written
consent from Analog Devices, Inc.
Printed in the USA.
Disclaimer
Analog Devices, Inc. reserves the right to change this product without
prior notice. Information furnished by Analog Devices is believed to be
accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use; nor for any infringement of patents or other rights of
third parties which may result from its use. No license is granted by implication or otherwise under the patent rights of Analog Devices, Inc.
Trademark and Service Mark Notice
The Analog Devices icon bar and logo, VisualDSP++, Blackfin, EZ-KIT
Lite, and EZ-Extender are registered trademarks of Analog Devices, Inc.
EZ-Board is a trademark of Analog Devices, Inc.
All other brand and product names are trademarks or service marks of
their respective owners.
Regulatory Compliance
The EVAL-SDP-CB1Z is designed to be used solely in a laboratory environment. The board is not intended for use as a consumer end product or
as a portion of a consumer end product. The board is an open system
design which does not include a shielded enclosure and therefore may
cause interference to other electrical devices in close proximity. This board
should not be used in or near any medical equipment or RF devices.
The EVAL-SDP-CB1Z board has been certified to comply with the essential requirements of the European EMC directive 89/36/EC amended by
93/68/EEC and therefore carries the “CE” mark.
The EVAL-SDP-CB1Z board evaluation system contains ESD (electrostatic discharge) sensitive devices. Electrostatic charges readily accumulate on the human body and equipment and can discharge without
detection. Permanent damage may occur on devices subjected to
high-energy discharges. Proper ESD precautions are recommended to
avoid performance degradation or loss of functionality. Store unused
EVAL-SDP-CB1Z boards in the protective shipping package.
CONTENTS
PREFACE
Product Overview .......................................................................... -iii
Purpose of This Manual ................................................................. -iv
Intended Audience .......................................................................... -v
Manual Contents ............................................................................ -v
What’s New in This Manual ............................................................ -v
Technical or Customer Support ...................................................... -vi
Product Information ...................................................................... -vi
Analog Devices Web Site .......................................................... -vi
Notation Conventions ................................................................... -vii
GETTING STARTED
Package Contents .......................................................................... 1-1
PC Configuration ......................................................................... 1-2
USB Installation ........................................................................... 1-2
Installing the Software ............................................................. 1-3
Connecting the SDP Board to the PC ...................................... 1-3
Verifying Driver Installation .................................................... 1-3
Powering Up/Down the SDP ......................................................... 1-5
SDP User Guide
i
Contents
Powering Up the SDP Board ................................................... 1-5
Powering Down the SDP Board ............................................... 1-5
HARDWARE DESCRIPTION
LEDs ........................................................................................... 2-1
POWER LED (LED2) ............................................................ 2-1
LED 1 .................................................................................... 2-2
Connector Details ........................................................................ 2-2
Connector Pin Assignments ..................................................... 2-3
Pin Sharing ........................................................................... 2-10
Power ......................................................................................... 2-11
Daughter Board Design Guidelines ............................................. 2-11
Connector Location .............................................................. 2-11
Keep Out Area ...................................................................... 2-14
Restriction on Right Angle Connectors .................................. 2-14
Mechanical Specifications ........................................................... 2-14
SCHEMATIC
ii
SDP User Guide
PREFACE
Thank you for purchasing the EVAL-SDP-CB1Z System Development
Platform (SDP) from Analog Devices, Inc. The SDP is used as part of the
evaluation system for many ADI components.
The SDP board is designed to be used in conjunction with various ADI
component evaluation boards as part of a customer evaluation environment. The SDP provides USB connectivity through a USB 2.0 high speed
connection to the computer allowing users to evaluate components on this
platform from a PC application. The SDP is based on ADSP-BF527
Blackfin processor, with the Blackfin processor peripheral communication
lines available to the component daughter board through the two identical
120-pin small footprint connectors
Product Overview
The board features:
• Analog Devices ADSP-BF527 Blackfin processor
• Core performance up to 600 MHz
• 208 -ball CSP-BGA package
• 24 MHz CLKIN oscillator
• 5 Mb of internal RAM memory
SDP User Guide
iii
Purpose of This Manual
• 32Mb flash memory
• Numonyx M29W320EB or
• Numonyx M25P32
• SDRAM memory
• Micron MT48LC16M16A2P-6A - 16 Mb x 16 bits (256
Mb/32 MB)
• 2 x 120-pin small foot print connectors
• Hirose FX8 -120P-SV1(91),120 Pin Header
• Blackfin processor peripherals exposed
• SPI
• SPORT
• TWI/I2C
• GPIO
• PPI
• Asynchronous Parallel
For more information, go to http://www.analog.com/sdp.
Purpose of This Manual
The SDP User Guide provides instructions for installing the SDP hardware
(EVAL-SDP-CB1Z board) and software onto your computer. The necessary installation files are provided with the evaluation daughter board
package.
iv
SDP User Guide
Preface
Intended Audience
The primary audience for this manual is a system engineer who seeks to
understand how to set up the SDP board and begin USB communications
to the computer.
Manual Contents
The manual consists of:
• Chapter 1, “Getting Started” on page 1-1
Provides software and hardware installation procedure, PC system
requirements and basic board information.
• Chapter 2, “Hardware Description” on page 2-1
Provides information on the EVAL-SDP-CB1Z components.
• Chapter 3, “Schematic” on page 3-1
Provides EVAL-SDP-CB1Z schematics.
What’s New in This Manual
Revision 1.2 of the SDP User Guide adds the following:
• Corrected the pin names for pin 21 (PAR_RD) and pin 22 (PAR_CS)
in the table describing the 120 pin connector. In Table 2-1 on
page 2-3 of the revision 1.1 book, the pin names were swapped, but
the pin descriptions were correct. The pin assignments in
Figure 2-1 on page 2-3 following the table of the revision 1.1 book
were correct.
SDP User Guide
v
Technical or Customer Support
Technical or Customer Support
You can reach Analog Devices, Inc. Customer Support in the following
ways:
• Visit the SDP Web site at
http://www.analog.com/sdp
• E-mail processor questions to
processor.support@analog.com (World wide support)
processor.europe@analog.com (Europe support)
processor.china@analog.com (China support)
• Phone questions to 1-800-ANALOGD
• Contact your Analog Devices, Inc. local sales office or authorized
distributor
• Send questions by mail to:
Analog Devices, Inc.
One Technology Way
P.O. Box 9106
Norwood, MA 02062-9106
USA
Product Information
Product information can be obtained from the Analog Devices Web site.
Analog Devices Web Site
The Analog Devices Web site, www.analog.com, provides information
about a broad range of products—analog integrated circuits, amplifiers,
converters, and digital signal processors.
vi
SDP User Guide
Preface
Also note, MyAnalog.com is a free feature of the Analog Devices Web site
that allows customization of a Web page to display only the latest information about products you are interested in. You can choose to receive
weekly e-mail notifications containing updates to the Web pages that meet
your interests, including documentation errata against all manuals.
MyAnalog.com provides access to books, application notes, data sheets,
code examples, and more.
Visit MyAnalog.com to sign up. If you are a registered user, just log on.
Your user name is your e-mail address.
Notation Conventions
Text conventions used in this manual are identified and described as
follows.
Example
Description
Close command
(File menu)
Titles in reference sections indicate the location of an item within the
VisualDSP++ environment’s menu system (for example, the Close command appears on the File menu).
{this | that}
Alternative required items in syntax descriptions appear within curly
brackets and separated by vertical bars; read the example as this or
that. One or the other is required.
[this | that]
Optional items in syntax descriptions appear within brackets and separated by vertical bars; read the example as an optional this or that.
[this,…]
Optional item lists in syntax descriptions appear within brackets delimited by commas and terminated with an ellipse; read the example as an
optional comma-separated list of this.
.SECTION
Commands, directives, keywords, and feature names are in text with
letter gothic font.
filename
Non-keyword placeholders appear in text with italic style format.
SDP User Guide
vii
Notation Conventions
Example
viii
Description

Note: For correct operation, ...
A Note provides supplementary information on a related topic. In the
online version of this book, the word Note appears instead of this
symbol.

Caution: Incorrect device operation may result if ...
Caution: Device damage may result if ...
A Caution identifies conditions or inappropriate usage of the product
that could lead to undesirable results or product damage. In the online
version of this book, the word Caution appears instead of this symbol.

Warning: Injury to device users may result if ...
A Warning identifies conditions or inappropriate usage of the product
that could lead to conditions that are potentially hazardous for the
devices users. In the online version of this book, the word Warning
appears instead of this symbol.
SDP User Guide
1 GETTING STARTED
This chapter provides specific information to assist you with using the
SDP board as part of your evaluation system.
The following topics are covered.
• “Package Contents”
• “PC Configuration”
• “USB Installation”
• “Powering Up/Down the SDP”
Package Contents
Your EVAL-SDP-CB1Z board package contains the following items.
• EVAL-SDP-CB1Z board
• 1m USB Standard-A to mini-B cable
Contact the vendor where you purchased your SDP board or contact Analog Devices, Inc. if any item is missing.
SDP User Guide
1-1
PC Configuration
PC Configuration
For correct operation of the SDP board, your computer must have the following minimum configuration
• Windows XP Service Pack 2 or Windows Vista
• USB 2.0 port
The SDP board evaluation system contains ESD (electrostatic discharge) sensitive devices. Electrostatic charges readily accumulate on
the human body and equipment and can discharge without detection.
Permanent damage may occur on devices subjected to high-energy discharges. Proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Store unused SDP boards in
the protective shipping package.
When removing the SDP board from the package, handle the board carefully to avoid the discharge of static electricity, which can damage some
components.
USB Installation
Perform the following tasks to safely install the SDP board onto the
computer.
There are two stages in the software application installation procedure.
The first installs the application software. The second installs the .NET
Framework 3.5 and the necessary drivers.
1-2
SDP User Guide
Getting Started
Installing the Software
1. Run the application install provided. The first stage will install the
Applications GUI and necessary support files onto the computer
2. Immediately following the application install, the .NET Framework 3.5 and the driver package for the SDP board is installed. If
the .NET Framework 3.5 is already pre-installed on the computer
in question, this stage will be skipped and step two will consist of a
driver package installation only
Connecting the SDP Board to the PC
• Attach the SDP board to a USB 2.0 port on the computer via the
Standard-A to Mini-B cable provided.
Verifying Driver Installation
Before using the SDP board, verify the driver software has installed
properly.
• Open the Windows Device Manager and verify the SDP board
appears under ADI Development Tools as shown in Figure 1-1.
SDP User Guide
1-3
USB Installation
Figure 1-1. Device Manager
1-4
SDP User Guide
Getting Started
Powering Up/Down the SDP
The following sections describe how to safely power up and down the
SDP.
Powering Up the SDP Board
1. Connect the SDP board to the daughter evaluation board through
the 120 pin mating connectors.
2. Power the daughter board
3. Connect the USB port on the computer to the SDP board.
Powering Down the SDP Board
1. Power down the daughter evaluation board
2. Disconnect the USB port on the computer from the SDP board
3. Disconnect the SDP board from the daughter evaluation board
SDP User Guide
1-5
Powering Up/Down the SDP
1-6
SDP User Guide
2 HARDWARE DESCRIPTION
This chapter describes the hardware design of the EVAL- SDP -CB1Z
board.
The following topics are covered.
• “LEDs” — Describes the SDP on board LEDs.
• “Connector Details” — Details the pin assignments on the 120 pin
Connectors
• “Power” — Lists power requirements of the SDP and identifies
connector power inputs and output pins
• “Daughter Board Design Guidelines” — Provides guidelines
regarding how to design daughter boards for use with the SDP
• “Mechanical Specifications” — Provides dimensional information
LEDs
There are two LEDs located on the SDP board. Refer to Figure 2-1.
POWER LED (LED2)
The green power LED indicates that the SDP board is powered. This is
not an indication of USB connectivity between the SDP and the PC.
SDP User Guide
2-1
Connector Details
Figure 2-1. SDP Board LEDs
LED 1
The orange LED is an LED to be used as a diagnostic tool for evaluation
application developers.
Connector Details
The SDP board contains two identical Hirose FX8-120P-SV1(91),
120 pin header, connectors. Through these connectors, the peripheral
communication interfaces of ADSP-BF527 Blackfin processor are
exposed. The exposed peripherals are:
• SPI
• SPORT
• I2C/TWI
2-2
SDP User Guide
Hardware Description
• GPIO
• Asynchronous Parallel
• PPI
• UART
• Timers
Also, included on the connector specification are input and output power
pins, ground pins, and pins reserved for future use.
For further details on the peripheral interfaces, including timing diagrams,
see the ADSP-BF52x Blackfin Processor Hardware Reference.
Connector Pin Assignments
The connector pin assignments have been defined independently of the any
internal pin sharing, which occurs on the Blackfin processor. Table 2-1 lists
the connector pins and identifies the functionality assigned to each connector
pin on the SDP board.
Table 2-1. 120 Pin Connector Pin Assignments
Pin No.
Pin Name
Description
1
VIN
Power to SDP board. Requires 200mA @ 4 – 7 Volts.
2
NC
No Connect. Leave this pin unconnected. Do not ground.
3
GND
Connect to ground plane of board.
4
GND
Connect to ground plane of board.
5
USB_VBUS
Connected directly to the USB +5v Supply.
6
GND
Connect to ground plane of board.
7
PAR_D23
Parallel Data Bus Bit 23.1 (No connect.)
8
PAR_D21
Parallel Data Bus Bit 21.1 (No connect.)
9
PAR_D19
Parallel Data Bus Bit 19.1 (No connect.)
SDP User Guide
2-3
Connector Details
Table 2-1. 120 Pin Connector Pin Assignments (Cont’d)
2-4
Pin No.
Pin Name
Description
10
PAR_D17
Parallel Data Bus Bit 17.1 (No connect.)
11
GND
Connect to ground plane of board.
12
PAR_D14
Parallel Data Bus Bit 14.
13
PAR_D13
Parallel Data Bus Bit 13.
14
PAR_D11
Parallel Data Bus Bit 11.
15
PAR_D9
Parallel Data Bus Bit 9.
16
PAR_D7
Parallel Data Bus Bit 7.
17
GND
Connect to ground plane of board.
18
PAR_D5
Parallel Data Bus Bit 5.
19
PAR_D3
Parallel Data Bus Bit 3.
20
PAR_D1
Parallel Data Bus Bit 1.
21
PAR_RD
Asynchronous Parallel Read Strobe.
22
PAR_CS
Asynchronous Parallel Chip Select.
23
GND
Connect to ground plane of board.
24
PAR_A3
Parallel Address Bus Bit 3.
25
PAR_A1
Parallel Address Bus Bit 1.
26
PAR_FS3
Synchronous (PPI) Parallel Frame Sync 3.
27
PAR_FS1
Synchronous (PPI) Parallel Frame Sync 1.
28
GND
Connect to ground plane of board.
29
SPORT_DR3
SPORT Data Receive 3.1 (No connect.)
30
SPORT_DR2
SPORT Data Receive 2.1 (No connect.)
31
SPORT_DR1
SPORT Data Receive 1. Secondary SPORT Data into processor.
32
SPORT_DT1
SPORT Data Transmit 1. Secondary SPORT Data from processor.
33
SPORT_DT2
SPORT Data Transmit 2.1 (No connect.)
34
SPORT_DT3
SPORT Data Transmit 3.1 (No connect.)
SDP User Guide
Hardware Description
Table 2-1. 120 Pin Connector Pin Assignments (Cont’d)
Pin No.
Pin Name
Description
35
SPORT_INT
SPORT Interrupt. Used to trigger a non-periodic SPORT event.
36
GND
Connect to ground plane of board.
37
SPI_SEL_B
SPI Chip Select B. Use this to control a second device on the SPI
bus.
38
SPI_SEL_C
SPI Chip Select C. Use this for a third device on the SPI bus.
39
SPI_SEL1/ SPI_SS
SPI Chip Select 1.2 (See Pin Sharing.) Used to connect to SPI Boot
Flash if required. Also used as Chip Select when Blackfin processor
is operating as SPI Slave.
40
GND
Connect to ground plane of board.
41
SDA_1
I2C Data 1.2 (See Pin Sharing.)
42
SCL_1
I2C Data 1.2 (See Pin Sharing.)
43
GPIO0
General Purpose Input/Output.
44
GPIO2
General Purpose Input/Output.
45
GPIO4
General Purpose Input/Output.
46
GND
Connect to ground plane of board.
47
GPIO6
General Purpose Input/Output.2 (See Pin Sharing.)
48
TMR_A
Timer A flag pin. Use as first Timer if required.
49
TMR_C
Timer C flag pin.1 (No connect.)
50
NC
No Connect. Leave this pin unconnected. Do not ground.
51
NC
No Connect. Leave this pin unconnected. Do not ground.
52
GND
Connect to ground plane of board.
53
NC
No Connect. Leave this pin unconnected. Do not ground.
54
NC
No Connect. Leave this pin unconnected. Do not ground.
55
NC
No Connect. Leave this pin unconnected. Do not ground.
56
EEPROM_A0
EEPROM A0. Connect to A0 Address line of the EEPROM
57
NC
No Connect. Leave this pin unconnected. Do not ground.
SDP User Guide
2-5
Connector Details
Table 2-1. 120 Pin Connector Pin Assignments (Cont’d)
2-6
Pin No.
Pin Name
Description
58
GND
Connect to ground plane of board.
59
UART_RX
UART Receive Data.2 (See Pin Sharing.)
60
RESET_IN
Active low pin to reset EVAL-SDP-CB1Z board.
61
BMODE1
Boot Mode 1. Pull up with 10kΩ resistor to set SDP to boot from
SPI Flash. Enabled on Connector A only.
62
UART_TX
UART Receive Data.2 (See Pin Sharing.)
63
GND
Connect to ground plane of board.
64
NC
No Connect. Leave this pin unconnected. Do not ground.
65
NC
No Connect. Leave this pin unconnected. Do not ground.
66
NC
No Connect. Leave this pin unconnected. Do not ground.
67
NC
No Connect. Leave this pin unconnected. Do not ground.
68
NC
No Connect. Leave this pin unconnected. Do not ground.
69
GND
Connect to ground plane of board.
70
NC
No Connect. Leave this pin unconnected. Do not ground.
71
NC
No Connect. Leave this pin unconnected. Do not ground.
72
TMR_D
Timer D flag pin.2 (See Pin Sharing.)
73
TMR_B
Timer B flag pin. Use as second Timer if required.
74
GPIO7
General Purpose Input/Output.2 (See Pin Sharing.)
75
GND
Connect to ground plane of board.
76
GPIO5
General Purpose Input/Output.
77
GPIO3
General Purpose Input/Output.
78
GPIO1
General Purpose Input/Output.
79
SCL_0
I2C Clock 0. Daughter Board EEPROM must be connected to this
bus.
80
SDA_0
I2C Data 0. Daughter Board EEPROM must be connected to this
bus.
SDP User Guide
Hardware Description
Table 2-1. 120 Pin Connector Pin Assignments (Cont’d)
Pin No.
Pin Name
Description
81
GND
Connect to ground plane of board.
82
SPI_CLK
SPI Clock.
83
SPI_MISO
SPI Master In, Slave Out Data.
84
SPI_MOSI
SPI Master Out, Slave In Data.
85
SPI_SEL_A
SPI Chip Select A. Use this to control the first device on the SPI
bus.
86
GND
Connect to ground plane of board.
87
SPORT_TSCLK
SPORT Transmit Clock.
88
SPORT_DT0
SPORT Data Transmit 0. Primary SPORT Data from processor.
89
SPORT_TFS
SPORT Transmit Frame Sync.
90
SPORT_RFS
SPORT Receive Frame Sync.
91
SPORT_DR0
SPORT Data Receive 0. Primary SPORT Data into processor.
92
SPORT_RSCLK
SPORT Receive Clock
93
GND
Connect to ground plane of board.
94
PAR_CLK
Clock for Synchronous Parallel Interface (PPI).
95
PAR_FS2
Synchronous (PPI) Parallel Frame Sync 2.
96
PAR_A0
Parallel Address Bus Bit 0.
97
PAR_A2
Parallel Address Bus Bit 2.
98
GND
Connect to ground plane of board.
99
PAR_INT
Parallel Interrupt. Used to trigger a non-periodic Parallel event.
100
PAR_WR
Asynchronous Parallel Write Strobe.
101
PAR_D0
Parallel Data Bus Bit 0.
102
PAR_D2
Parallel Data Bus Bit 2.
103
PAR_D4
Parallel Data Bus Bit 4.
104
GND
Connect to ground plane of board.
105
PAR_D6
Parallel Data Bus Bit 6.
SDP User Guide
2-7
Connector Details
Table 2-1. 120 Pin Connector Pin Assignments (Cont’d)
Pin No.
Pin Name
Description
106
PAR_D8
Parallel Data Bus Bit 8.
107
PAR_D10
Parallel Data Bus Bit 10.
108
PAR_D12
Parallel Data Bus Bit 12.
109
GND
Connect to ground plane of board.
110
PAR_D15
Parallel Data Bus Bit 15.
111
PAR_D16
Parallel Data Bus Bit 16.1 (No connect.)
112
PAR_D18
Parallel Data Bus Bit 18.1 (No connect.)
113
PAR_D20
Parallel Data Bus Bit 20.1 (No connect.)
114
PAR_D22
Parallel Data Bus Bit 22.1 (No connect.)
115
GND
Connect to ground plane of board.
116
VIO(+3.3V)
+3.3V Output. 20mA max current available to power IO voltage on
daughter board.
117
GND
Connect to ground plane of board.
118
GND
Connect to ground plane of board.
119
NC
No Connect. Leave this pin unconnected. Do not ground.
120
NC
No Connect. Leave this pin unconnected. Do not ground.
1
2
Functionality not implemented on the EVAL-SDP-CB1Z.
Shared across both connectors.
Each interface provided by the SDP is available on unique pins of the
SDP’s 120 pin connector. The connector pin numbering scheme is outline in Figure 2-2.
2-8
SDP User Guide
Hardware Description
Figure 2-2. 120 Pin Connector Outline
SDP User Guide
2-9
Connector Details
Pin Sharing
Two types of pin sharing occur on the SDP board and must be taken into
account when using two or more of the connector's peripherals interfaces
between a daughter board and the SDP board. The first type is pin sharing
that occurs internally in the Blackfin processor. The second type is pin
sharing that occurs when a single Blackfin processor output pin is shared
across both connector A and connector B.
Internal Blackfin processor pin sharing can restrict the simultaneous availability of peripheral interfaces on a single connector or across both
connectors. The Blackfin processor's internal design has multiple signals
physically sharing each single output pin. As mentioned previously, the
pins on the 120 pin connector were defined independently of this pin
sharing. This has the effect of limiting the peripherals which can be used
simultaneously on the SDP. A system designer must consult the
ADSP-BF52x Blackfin Processor Hardware Reference for the ADSP-BF527
processor to ensure the selected peripherals are available simultaneously
and their signals do not share Blackfin processor output pins. An example
of this sharing is that the SPORT and PPI peripherals physically share the
same Blackfin processor pins. Therefore, these two interfaces cannot be
utilized in a single application.
Pin sharing also occurs from certain Blackfin processor output pins to
both Connector A and Connector B. The following signals are connected
from a single Blackfin processor output pin to both Connector A and
Connector B:
• I2C Bus 1, pins 42 and 43
• SCL 0 on I2C Bus 0, pin 79
• GPIO 6 and GPIO 7, pins 47 and 67
• Timer D, pin 72
• UART, pins 59 and 62
2-10
SDP User Guide
Hardware Description
Power
The SDP board requires that any daughter board connected to the SDP
board provides the SDP board with 5V @ 200mA. This supply should be
made available on Pin 1 (VIN) of the 120 pin connector. This supply is
required to power the Blackfin processor, the memory, and the other components on the SDP Board. The SDP board also provides 3.3V @ 20mA
on Pin 116 (VIO_3.3) to connected daughter boards as the VIO voltage
for the daughter board. Pin 5 (USB_VBUS) is connected to the +5V line
of the USB connector, providing 5V+/- 10% as an output of the SDP
board.
Daughter Board Design Guidelines
The daughter board design guidelines specify the layout, connector position, keep out areas and dimensions of potential daughter boards. This
guidance is to ensure that a daughter board can connect off either Connector A or Connector B of the SDP board. Following these guidelines
ensures that both connectors on the SDP can have any one of the catalogue of daughter boards physically attached to the connectors
simultaneously.
Connector Location
The daughter board connector and securing screw holes are to be located
in the top left hand corner. This arrangement can be seen for Daughter
Board A in Figure 2-3. Note Daughter Board B is the same as A rotated
clockwise through 90°. The exact location of the connector from the
board's edge is important in order to allow both boards connect at the
same time. As can be seen in Figure 2-3, if either board exceeds these
dimensions, it is not possible to connect the other. Every effort was made
to extend the 5.9mm dimension as large as possible in order to allow space
for vias between the connector and the edge of the board. These are abso-
SDP User Guide
2-11
Daughter Board Design Guidelines
lute max dimensions and should not be exceeded. See Figure 2-3 for
further details.
5.9mm
3.3mm
Daughter
Board A
Daughter Board B
3.3mm
5.9mm
Figure 2-3. Maximum Board Dimensions for Connector Placement
2-12
SDP User Guide
Hardware Description
The full specification drawing for the connector location on the daughter
board can be seen in Figure 2-4.
Figure 2-4. Connector Placement on Compatible Daughter Board
The mating daughter board 120 pin connector is the Hirose
FX8-120S-SV(21), 120-pin receptacle, FEC 132-4660, Digikey
H1219-ND. Please consult the connector's data sheet for full details on
the connector. Note pins 1 to 60 are placed on the left side of the connector and pins 61 to 120 are placed on the right side of the connector.
SDP User Guide
2-13
Mechanical Specifications
Keep Out Area
In order to allow the greatest flexibility for future controller boards, a
keepout area is established for components higher that 3mm. The keepout
area is 12.65mm wide and extends down the entire left side of the daughter board.
Restriction on Right Angle Connectors
Due to the close proximity of the edges of daughter boards A and B (seen
in Figure 2-3 on page 2-12) right angle connectors are not allowed on the
top and left edges of the daughter boards and (if required) should be
placed on the right or bottom edges. The phrase "right angle connector" is
used to describe any connector that requires the connection to protrude
over the edge of the board (for example, right angle SMB or screw
terminal)
Mechanical Specifications
The mechanical specifications of the SDP board are 2.75" x 2.25"
(69.85mm x 27.15mm). The height of the 120 pin connectors from the
bottom of the board is approximately 0.152" (3.86 mm). The tallest component on the top is approximately 0.125" (3.175 mm), and the tallest
components on the bottoms are the connectors at approximately 0.152"
(3.86 mm). Refer to Figure 2-5.
2-14
SDP User Guide
Hardware Description
Figure 2-5. SDP Board Mechanical Specifications
SDP User Guide
2-15
Mechanical Specifications
2-16
SDP User Guide
3 SCHEMATIC
This chapter provides the schematic drawings for the EVAL- SDP -CB1Z
board. The schematic pages include:
• System Development Platform—Power
• System Development Platform—Memory
• System Development Platform—Clocks_USB
• System Development Platform—Blackfin_I/O
• System Development Platform—Connector A
• System Development Platform—Connector B
SDP User Guide
3-1
3-2
SDP User Guide
6
5
4
3
2
1
REVISION RECORD
ECO NO:
LTR
APPROVED:
DATE:
D
D
U1-C
G12
+1.2V
VIN
7
IN
8
IN
6
SD
4
GND
D5
V-UNREG
BAT54
U2
C30
10uF
1
OUT
2
OUT
3
OUT
5
NR
C46
0.1uF
C19
10nF
C18
1nF
G14
H14
J14
+3.3V
ADP3335-LCSP
C1
1nF
C4
C20
0.1uF
G13
+
C5
4.7uF
K14
C34
20%
47uF
L14
R11
1k
C31
0.1uF
C23
0.1uF
C22
10nF
C21
1nF
M14
N14
P12
4.7uF
LED2
P13
GREEN
P14
VDDINT
VDDEXT
VDDINT
VDDEXT
VDDINT
VDDEXT
VDDINT
VDDEXT
VDDINT
VDDEXT
VDDINT
VDDEXT
VDDINT
VDDEXT
VDDINT
VDDEXT
VDDINT
VDDEXT
VDDINT
VDDEXT
VDDINT
VDDEXT
VDDINT
VDDEXT
VDDMEM
VDDMEM
C
VDDMEM
VDDMEM
VDDMEM
A16
+3.3V
C32
10uF
2
3
4
EN
7
IN
C6
R20
10nF
6
OUT
+2.5V
5
OUT
4.7uF
+
C7
4.7uF
ADP1706
2.5V
VDDUSB
VDDMEM
VDDUSB
VDDMEM
VDDMEM
8
GND SENSE
VDDMEM
VDDMEM
D19
C2
SS
IN
C24
10nF
G20
U3
1
C25
0.1uF
VDDRTC
L19
+2.5V
C35
20%
47uF
C33
10uF
C26
0.1uF
VDDOTP
VPPOTP
VROUT
VRSEL
G7
+3.3V
G8
G9
G10
G11
H7
H8
C10
10nF
C11
0.1uF
C12
0.1uF
C13
0.1uF
C27
10nF
C28
10uF
J7
J8
K7
K8
L7
L8
M7
M8
C
N7
N8
P7
C14
10nF
C15
0.1uF
C16
0.1uF
C17
10nF
C29
10uF
P8
P9
P10
P11
H20
F19
ADSP-BF522_3_4_5_6_7_208-BGA
U1-D
U4
1
B
2
3
4
C8
4.7uF
EN
SS
GND SENSE
IN
IN
A1
C3
OUT
OUT
ADP1706
1.2V
8
A17
7
A20
10nF
6
5
+1.2V
C9
4.7uF
+
C36
20%
47uF
B20
H9
H10
H11
H12
H13
J9
J10
J11
J12
J13
K9
K10
K11
K12
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
K13
L9
B
L10
L11
L12
L13
M9
M10
M11
M12
M13
N9
N10
N11
N12
N13
Y1
Y20
COMPANY:
ADSP-BF522_3_4_5_6_7_208-BGA
A
TITLE:
DRAWN:
DATED:
CHECKED:
DATED:
QUALITY CONTROL:
DATED:
RELEASED:
DATED:
Paddy Duignan
MICK McCARTHY
13-01-09
SIZE:
DRAWING NO:
SDP1Z
SCALE:
A
SYSTEM DEVELOPMENT PLATFORM
POWER
CODE:
14-01-10
ANALOG DEVICES
SHEET: 1 OF 6
REV:
B
6
5
4
3
2
1
REVISION RECORD
LTR
A[1:19]
33r
W3
D10
R34-F
33r
Y3
D9
R34-G
33r
W4
D8
R34-H
33r
Y4
D7
R35-A
33r
W5
D6
R35-B
33r
Y5
D5
R35-C
33r
W6
D4
R35-D
33r
Y6
R35-E
33r
D2
R35-F
33r
Y7
D1
R35-G
33r
W8
D0
R35-H
33r
Y8
D3
V19
33r
AMS2
AMS1
AMS0
L20
R39-D
33r
M19
R39-F
33r
K19
R39-H
33r
J19
33r
DATA9
ADDR14
DATA8
ADDR13
DATA7
ADDR12
DATA6
ADDR11
DATA5
ADDR10
DATA4
ADDR9
DATA3
ADDR8
DATA2
ADDR7
DATA1
ADDR6
DATA0
ADDR5
ABE1
ADDR3
ABE0
ADDR2
N20
M20
33R
N19
R42
AMS2
SRAS
AMS1
SCAS
AOE
SCKE
ARE
CLKOUT
AWE
SA10
SMS
P19
33r
A17
W12
R36-E
33r
A16
Y13
R36-D
33r
A15
W13
R36-C
33r
A14
Y14
R36-B
33r
A13
W14
R36-A
33r
A12
Y15
R37-H
33r
A11
W15
R37-G
33r
A10
Y16
R37-F
33r
A9
R37-E
33r
Y17
R37-D
33r
A7
W17
R37-C
33r
A6
Y18
R37-B
33r
A5
W18
R37-A
33r
A4
Y19
R38-H
33r
A3
W19
R38-G
33r
W20
R38-F
33r
T19
R38-A
U20
R38-B
W16
2
4
5
7
8
10
11
13
42
44
45
47
48
50
51
53
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A8
A[1:19]
U5-A
D[0:15]
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
40
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A12
A13
38
CLK
37
CKE
20
BA0
21
BA1
16
WE
17
CAS
18
RAS
19
CS
SWE
SCAS
SRAS
SMS
23
24
25
26
29
30
31
32
33
34
22
35
36
AWE
SCAS
T20
R39-A
A18
A19
A[1:19]
ABE0
ABE1
P20
R39-C
33r
K20
R39-G
33r
U19
R38-C
33r
R39-B
33r
R19
SCKE
C48
0.1uF
CLKOUT
SA10
C37
0.1uF
SMS
33r
ARDY
+3.3V
SWE
U5-B
MT48LC16M16A2P
C40
0.1uF
C49
0.1uF
D4
A19
C3
A18
B2
A17
E6
A16
D6
A15
C6
A14
A6
A13
B6
A12
D5
A11
C5
A10
A5
A9
B5
A8
A2
A7
C2
A6
D2
A5
B1
A4
A1
A3
C1
A2
D1
A1
E1
E
1
4
U20
C41
0.1uF
U6
C70
10nF
C71
1uF
G
W
A20
A19
DQ15
A18
DQ14
A17
DQ13
A16
DQ12
A15
DQ11
A14
DQ10
A13
DQ9
A12
DQ8
A11
DQ7
A10
DQ6
A9
DQ5
A8
DQ4
A7
DQ3
A6
DQ2
A5
DQ1
A4
DQ0
A3
RB
A2
G6
D15
F5
D14
G5
D13
F4
D12
G3
D11
F3
D10
G2
D9
F2
D8
E5
D7
H5
D6
E4
D5
H4
D4
H3
D3
E3
D2
H2
D1
E2
D0
D[0:15]
C
A3
A1
A0
H1
ADSP-BF522_3_4_5_6_7_208-BGA
2
D3
FLASH_A19
SRAS
33r
A4
FLASH_A20
A1
33r
F1
G1
ARE
SA10
MT48LC16M16A2P
A2
+3.3V
FLASH_CS
CLKOUT
SCKE
15
DQML
39
DQMH
N/C
RESET
33r
AMS0
AWE
33R
R36-F
AMS3
SWE
R41
ARE
ADDR15
ADDR1
R39-E
AMS3
DATA10
ADDR4
V20
R38-E
ABE0
C
33r
33r
R38-D
ABE1
W7
ADDR16
DATA11
Y12
D
G4
R34-E
ADDR17
A18
VCC
D11
DATA12
33r
F6
Y2
R36-G
BYTE
33r
W11
NC
R34-D
ADDR18
VSS
D12
DATA13
4MByte Flash
** Fit part MT48LC32M16A2P-75:C for 64 MByte SDRAM
A19
C4
W2
R36-H
H6
33r
Y11
B3
R34-C
ADDR19
VPP/WP
D13
DATA14
VSS
W1
B4
33r
RP
R34-B
DATE:
* Fit part MT48LC16M16A2P-75:D for 32 MByte SDRAM
DATA15
3
VDDQ
9
VDDQ
43
VDDQ
49
VDDQ
D14
V1
6
VSSQ
12
VSSQ
46
VSSQ
52
VSSQ
R34-A
28
VSS
41
VSS
54
VSS
D
D15
APPROVED:
32 MByte SDRAM
U1-A
1
VDD
14
VDD
27
VDD
D[0:15]
ECO NO:
M29W320EBZE
PAR_RD_WR
NC7S08
B
B
5
10
+3.3V
R40
1
2
3
4
6
7
8
9
RA
RB
RC
RD
RE
RF
RG
RH
COM COM
U12
ADG774A_LFCSP
AMS0
AMS1
AMS2
AMS3
2
5
7
10
D1
16
S1A
1
S1B
D2
3
S2A
S2B 4
CS_B
D3
9
S3A
8
S3B
CS_LATCH
D4
12
S4A
11
S4B
13
A
U8
4
FLASH_A19
4
FLASH_A20
NC7S08
VDD
EN
2
14
GND
1
CS_A
2
U7
NC7S00
1
1
2
U9
4
2
U10
4
FLASH_CS
NC7S08
NC7S08
IN
15
PG0/FLASH_EN
6
1
RES-RNA310
100k
COMPANY:
TITLE:
+3.3V
+3.3V
C43
0.1uF
C44
0.1uF
C50
0.1uF
C51
0.1uF
DRAWN:
DATED:
CHECKED:
DATED:
QUALITY CONTROL:
DATED:
RELEASED:
DATED:
Paddy Duignan
MICK McCARTHY
13-01-09
SIZE:
DRAWING NO:
SDP1Z
SCALE:
A
SYSTEM DEVELOPMENT PLATFORM
(MEMORY)
CODE:
14-01-10
ANALOG DEVICES
SHEET: 2 OF 6
REV:
B
6
5
4
3
2
1
REVISION RECORD
LTR
ECO NO:
APPROVED:
DATE:
D
D
+3.3V
+3.3V
R2
C42
0.1uF
Sets Boot Mode for 8-/16-bit Flash
or SPI Flash if BMODE1 pulled high
U1-K
R1
W9
10k
U11
5
Y9
VCC
MR
10k
4
RESET
MR
RESET
W10
BMODE1
3
1
R7
+3.3V
RESET
Y10
10k
RESET
BMODE2
NMI
BMODE1
SS/PG
BMODE0
EXT_WAKE
B18
RESET
B19
G19
J20
ADSP-BF522_3_4_5_6_7_208-BGA
GND
2
BMODE3
ADM6319
R6
10k
R5
R4
10k
200k
C
C
D7
VIN
BAT54
USB_VBUS
J1
U1-B
B
C20
U1-I
A14
RTXI
H19
RTX0
CLKBUF
A11
CLKIN
XTAL
A15
D20
C19
A19
A10
C38
0.1uF
ADSP-BF522_3_4_5_6_7_208-BGA
USB_ID
USB_VREF
USB_RSET
USB_XTALIN
USB_VBUS
L1
E19
1
2
USB_DM
USB_DP
F20
3
E20
4
5
USB_XTALOUT
A18
D3
D2
D1
ADSP-BF522_3_4_5_6_7_208-BGA
C53
VBUS
D-
B
SHLD
6
D+
IO
SHLD
7
GND
USB-MINI-B-THRU-HOLE
0.1uF
R8
DNP
ESD Diodes
R12
330R
Y1
24.000MHz
C45
8.2pF
C47
8.2pF
ANALOG DEVICES
COMPANY:
A
TITLE:
DRAWN:
DATED:
CHECKED:
DATED:
QUALITY CONTROL:
DATED:
RELEASED:
DATED:
Paddy Duignan
MICK McCARTHY
13-01-09
SYSTEM DEVELOPMENT PLATFORM
(CLOCKS_USB)
CODE:
14-01-10
SIZE:
DRAWING NO:
SDP1Z
SCALE:
A
SHEET: 3 OF 6
REV:
B
6
5
4
3
2
1
REVISION RECORD
LTR
U1-E
9
F1
R28-G7
33r
10
E2
R28-E5
33r
12
D2
R28-C3
33r
14
C2
R27-A16
33r
1
B2
R27-C14
33r
3
B3
R27-E12
33r
5
B5
R27-G10
33r
PF0/PPI_D0/DR0PRI
PF2/PPI_D2/RSCLK0
PF4/PPI_D4/TFS0/TACLK0
D
PF6/PPI_D6/DT0SEC/TACI0
PF8/PPI_D8/DR1PRI
PF10/PPI_D10/RFS1/SPISEL7
PF12/PPI_D12/DT1PRI/SPISEL2/COG
PF14/PPI_D14/DT1SEC/UART1TX
7
B6
33r
PF0
PF3
PF4
PF5
PF6
PF7
PF8
PF9
PF10
PF11
PF12
PF13
PF14
DATE:
U1-J
PF1
PF2
APPROVED:
PF15
E1
R28-F 11
D1
R28-D 13
33r
C1
R28-B 15
33r
2
B1
R28-A 16
33r
1
A2
R27-B 2
33r
15
A3
R27-D 4
33r
13
A5
R27-F 6
33r
11
A6
R27-H 8
33r
9
6
PF1/PPI_D1/RFS0
4
V2
JTAG_TCK
PF3/PPI_D3/DT0PRI
R1
JTAG_TDI
PF5/PPI_D5/TSCLK0/TACLK1
U2
JTAG_TMS
PF7/PPI_D7/DR0SEC/TACI1
U1
JTAG_TRST
PF9/PPI_D9/RSCLK1/SPISEL6
TCK
TDI
TMS
TRST
TDO
EMU
R10
T1
JTAG_TDO
0R
R9
T2
D
JTAG_EMU
0R
ADSP-BF522_3_4_5_6_7_208-BGA
PF11/PPI_D11/TFS1/CZM
R3
PF13/PPI_D13/TSCLK1/SPISEL3/CUD
10k
R28-H8
ECO NO:
PF15/PPI_D15/DR1SEC/UART1RX/TACI3
33r
ADSP-BF522_3_4_5_6_7_208-BGA
+3.3V
Will be driven low as soon
as core is ready to boot.
R19
R20
10k
10k
R21
U1-F
R29-A
PG0/FLASH_EN
PG2/SCK
PG10/TMR6/TSCLK0A/TACI6
33r
P2
N2
R29-E
33r
33r
M2
R30-A
33r
L2
R30-C
33r
K2
PG6/DT0PRIA/TMR2/PPI_FS3
PG8/TMR4/RFS0A/UART0RX/TACI4
R2
R29-C
R29-G
PG4/MOSI/DT0SECA
PG12/UART1TXA
C
+3.3V
PG14/TSCLK0A1/MOC
R30-E
33r
J2
R30-G
33r
H2
33r
PG0
PG3
PG4
PG5
PG8
P1
PG1
PG2
PG6
10k
R29-B
R29-D
33r
M1
R29-F
33r
L1
R29-H
33r
K1
R30-B
33r
J1
R30-D
33r
N1
PG7
PG9
PG10 PG11
PG12 PG13
PG14 PG15
H1
R30-F
33r
G1
R30-H
33r
JTAG
PG1/SPISS/SPISEL1
PG3/MISO/DR0SECA
PG5/TMR1/PPI_FS2
PG7/TMR3/DR0PRIA/UART0TX
PG9/TMR5/RSCLK0A/TACI5
R13
PG11/TMR7
+3.3V
PG13/UART1RXA/TACI2
4k7
PG15/TFS0A/MII_PHYINT/RMII_MDINT
33r
ADSP-BF522_3_4_5_6_7_208-BGA
JTAG_EMU
J3-1
J3-2
J3-3
J3-4
J3-5
J3-6
JTAG_TMS
J3-7
J3-8
JTAG_TCK
J3-9
J3-10
JTAG_TRST
J3-11
J3-12
JTAG_TDI
J3-13
J3-14
JTAG_TDO
C
Remove Pin 3 for keying
U1-G
R32-G
PH0/MII_CRS/RMII_CRSDV
PH2/MDIO
PH4/MII_TXCLK/RMII_REFCLK
PH6/ERXDO
33r
A8
R32-C
33r
A9
R32-B
33r
B10
R31-A
33r
A12
R31-C
33r
A13
R31-E
33r
B14
R31-G
33r
B16
PH8/SPISEL4/ERXD1/TACLK2
PH10/ERXD2
PH12/ERXD3
PH14/ERXDV
A7
R32-E
33r
PH0
PH1
PH2
PH3
PH4
PH5
PH6
PH7
PH8
PH9
PH10 PH11
PH12 PH13
PH14 PH15
B7
R32-H
B8
R32-F
33r
B9
R32-D
33r
B11
R32-A
33r
B12
R31-B
33r
B13
R31-D
33r
B15
R31-F
33r
B17
R31-H
33r
PH1/ERXER
PH3/ETXEN
PH5/ETXD0
PH7/ETXD1
PH9/SPISEL5/ETXD2/TACLK3
PH11/ETXD3
PH13/ERXCLK
PH15/COL
33r
ADSP-BF522_3_4_5_6_7_208-BGA
+3.3V
J5-1
+3.3V
J5-2
C57
B
J5-3
0.1uF
R43
PJ2/SCL
U1-H
PJ0/PP1_FS1/TMR0
33R
F2
G2
R33
PJ1/PPI_CLK/TMRCLK
SCL
PJ0
SDA
PJ1
A4
PJ2/SCL
B4
R16
R17
2k2
2k2
13
VDD
ADSP-BF522_3_4_5_6_7_208-BGA
33R
I2C_SEL_A
I2C_SEL_B
19
U13
ADG782
R18
R23
R24
200k
200k
200k
+3.3V
+3.3V
C39
0.1uF
I2C_SEL_C
D1 1
SDA_A
S2 14
17 IN2
R26
D[0:15]
1
2
AWE
NC7S32
U14
SDA_C
S4 4
D4 5
GND
3
YELLOW
COMPANY:
1 CLR
11
CLK
RESET
CS_LATCH
S3 12
9 IN3
7 IN4
LED1
1k
U19
SDA_B
D3 11
C56
0.1uF
4
D0
D1
D2
D3
D4
D5
D6
D7
3
4
7
8
13
14
17
18
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
B
J5-4
S1 2
IN1
D2 15
A
SDA_C
TITLE:
I2C_SEL_A
I2C_SEL_B
I2C_SEL_C
U21
2
4
CONA_PPI_DIR
CONA_PPI_EN
NC7S04
CONB_PPI_DIR
74AHC273
C58
0.1uF
U22
2
4
NC7S04
+3.3V
CONB_PPI_EN
C59
0.1uF
DRAWN:
DATED:
CHECKED:
DATED:
QUALITY CONTROL:
DATED:
RELEASED:
DATED:
Paddy Duignan
MICK McCARTHY
13-01-09
SIZE:
DRAWING NO:
SDP1Z
SCALE:
A
SYSTEM DEVELOPMENT PLATFORM
(BLACKFIN I/O)
CODE:
14-01-10
ANALOG DEVICES
SHEET: 4 OF 6
REV:
B
6
5
4
3
2
1
REVISION RECORD
ECO NO:
LTR
BMODE1_A
J2-92
SPORT_RSCLK
PF1/PPI_D1/RFS0
J2-90
SPORT_RFS
PF0/PPI_D0/DR0PRI
J2-91
SPORT_DR0
PF7/PPI_D7/DR0SEC/TACI1
J2-31
SPORT_DR1
Future Use
J2-30
SPORT_DR2
Future Use
J2-29
SPORT_DR3
PF5/PPI_D5/TSCLK0/TACLK1
J2-87
SPORT_TSCLK
PF4/PPI_D4/TFS0/TACLK0
J2-89
SPORT_TFS
PF3/PPI_D3/DT0PRI
J2-88
SPORT_DT0
PF6/PPI_D6/DT0SEC/TACI0
J2-32
SPORT_DT1
Future Use
J2-33
SPORT_DT2
Future Use
J2-34
SPORT_DT3
J2-35
SPORT_INT
J2-8
ARE
PAR_RD_WR
1
CS_A
2
U23
J2-113
D[23:16] (Future Use)
J2-9
4
J2-112
NC7S32
D[0:15]
D0
D1
D2
D3
D4
D5
D6
D7
A6
B5
B6
C5
C6
D5
D6
E5
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
U15-A
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
+3.3V
CONA_PAR_D[0:15]
J2-10
J2-111
A1
B2
B1
C2
C1
D2
D1
E2
CONA_PAR_D0
CONA_PAR_D1
CONA_PAR_D2
CONA_PAR_D3
CONA_PAR_D4
CONA_PAR_D5
CONA_PAR_D6
CONA_PAR_D7
C54
0.1uF
J2-37
SPI_SEL_B
PF12/PPI_D12/DT1PRI/SPISEL2/COG
J2-38
SPI_SEL_C
PG1/SPISS/SPISEL1
J2-39
SPI_SEL1/SPI_SS
CONA_PAR_D15
CONA_PAR_D14
PG4/MOSI/DT0SECA
J2-84
SPI_MOSI
PG3/MISO/DR0SECA
J2-83
SPI_MISO
J2-82
SPI_CLK
SDA_A
PJ2/SCL
PG10/TMR6/TSCLK0A/TACI6
SDA_0
J2-79
SCL_0
J2-41
SDA_1
J2-42
SCL_1
PG8/TMR4/RFS0A/UART0RX/TACI4
J2-59
UART_RX
PG7/TMR3/DR0PRIA/UART0TX
J2-62
UART_TX
J2-43
GPIO_0
PH1/ERXER
J2-78
GPIO_1
PH2/MDIO
J2-44
GPIO_2
PH3/ETXEN
J2-77
GPIO_3
J2-45
GPIO_4
PH5/ETXD0
J2-76
GPIO_5
PH6/ERXDO
J2-47
GPIO_6
J2-74
GPIO_7
PH4/MII_TXCLK/RMII_REFCLK
PH7/ETXD1
A
PG7/TMR3/DR0PRIA/UART0TX
PG5/TMR1/PPI_FS2
Future Use
PJ0/PP1_FS1/TMR0
J3
2DIR
2OE
CONA_PAR_D9
CONA_PAR_D8
C66
10nF
C73
1uF
CONA_PAR_D7
CONA_PAR_D6
CONA_PAR_D5
CONA_PAR_D4
CONA_PAR_D1
CONA_PPI_EN
PF0/PPI_D0/DR0PRI
PF1/PPI_D1/RFS0
PF2/PPI_D2/RSCLK0
PF3/PPI_D3/DT0PRI
PF4/PPI_D4/TFS0/TACLK0
PF5/PPI_D5/TSCLK0/TACLK1
PF6/PPI_D6/DT0SEC/TACI0
PF7/PPI_D7/DR0SEC/TACI1
1OE
A6
B5
B6
C5
C6
D5
D6
E5
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
+3.3V
U16-A
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
CONA_PAR_D0
CONA_PAR_D1
CONA_PAR_D2
CONA_PAR_D3
CONA_PAR_D4
CONA_PAR_D5
CONA_PAR_D6
CONA_PAR_D7
E6
F5
F6
G5
G6
H5
H6
J6
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
BAT54
J2-12
J2-2
J2-13
J2-108
V-UNREG
J2-14
J2-119
J2-120
J2-107
J2-15
USB_VBUS
J2-5
C
J2-106
J2-16
J2-105
J2-18
J2-103
J2-3
J2-19
J2-4
J2-102
J2-6
J2-20
J2-11
J2-101
J2-17
C61
0.1uF
J2-36
J2-40
J2-46
J2-21
PAR_RD
J2-52
AWE
J2-100
PAR_WR
J2-58
CS_A
J2-22
PAR_CS
J2-63
J2-99
PAR_INT
J2-69
J2-24
PAR_A3
J2-81
J2-97
PAR_A2
J2-86
J2-25
PAR_A1
J2-93
J2-96
PAR_A0
J2-98
J2-26
PAR_FS3
J2-109
PG5/TMR1/PPI_FS2
J2-95
PAR_FS2
J2-115
PJ0/PP1_FS1/TMR0
J2-27
PAR_FS1
J2-117
J2-94
PAR_CLK
ARE
U16-B
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
J2-110
J2-28
C60
0.1uF
74LVCH16245AZRDR
PF8/PPI_D8/DR1PRI
PF9/PPI_D9/RSCLK1/SPISEL6
PF10/PPI_D10/RFS1/SPISEL7
PF11/PPI_D11/TFS1/CZM
PF12/PPI_D12/DT1PRI/SPISEL2/COG
PF13/PPI_D13/TSCLK1/SPISEL3/CUD
PF14/PPI_D14/DT1SEC/UART1TX
PF15/PPI_D15/DR1SEC/UART1RX/TACI3
CONA_PAR_D0
J2-1
VIN
J2-23
A1
B2
B1
C2
C1
D2
D1
E2
PG9/TMR5/RSCLK0A/TACI5
+3.3V
J2-75
E1
F2
F1
G2
G1
H2
H1
J1
74LVCH16245AZRDR
PH0/MII_CRS/RMII_CRSDV
CONA_PAR_D8
CONA_PAR_D9
CONA_PAR_D10
CONA_PAR_D11
CONA_PAR_D12
CONA_PAR_D13
CONA_PAR_D14
CONA_PAR_D15
CONA_PAR_D10
CONA_PAR_D2
2OE
B
E1
F2
F1
G2
G1
H2
H1
J1
+3.3V
CONA_PPI_DIR
J4
PG12/UART1TXA
J2-80
CONA_PAR_D11
CONA_PAR_D3
A4
PG2/SCK
CONA_PAR_D13
74LVCH16245AZRDR
A3
PF9/PPI_D9/RSCLK1/SPISEL6
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
1DIR
SPI_SEL_A
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
J3
J2-85
E6
F5
F6
G5
G6
H5
H6
J6
J2-116
D4
CONA_PAR_D[0:15]
U15-B
2DIR
PH8/SPISEL4/ERXD1/TACLK2
D8
D9
D10
D11
D12
D13
D14
D15
+3.3V
C55
0.1uF
CONA_PAR_D12
J4
C
D
J2-114
74LVCH16245AZRDR
PG11/TMR7
DATE:
J2-7
DIR=1: A->B; DIR=0: B->A
A3
PF2/PPI_D2/RSCLK0
J2-61
1DIR
D
0R
RESET_IN
A4
R14
BMODE1
J2-60
1OE
MR
APPROVED:
CONA_PAR_D8
CONA_PAR_D9
CONA_PAR_D10
CONA_PAR_D11
CONA_PAR_D12
CONA_PAR_D13
CONA_PAR_D14
CONA_PAR_D15
A[1:19]
C67
10nF
C72
1uF
A4
A3
A2
A1
B
J2-104
PG6/DT0PRIA/TMR2/PPI_FS3
J2-118
PJ1/PPI_CLK/TMRCLK
Future Use
PG0/FLASH_EN
R25
DNP
J2-50
J2-71
J2-51
J2-70
J2-53
J2-68
J2-54
J2-67
J2-55
J2-66
J2-48
TMR_A
J2-56
J2-65
J2-73
TMR_B
J2-57
J2-64
J2-49
TMR_C
J2-72
TMR_D
COMPANY:
TITLE:
DRAWN:
DATED:
CHECKED:
DATED:
QUALITY CONTROL:
DATED:
RELEASED:
DATED:
Paddy Duignan
MICK McCARTHY
13-01-09
SIZE:
DRAWING NO:
SDP1Z
SCALE:
A
SYSTEM DEVELOPMENT PLATFORM
(CONNECTOR A)
CODE:
14-01-10
ANALOG DEVICES
SHEET: 5 OF 6
REV:
B
6
5
4
3
2
1
REVISION RECORD
ECO NO:
LTR
J4-90
SPORT_RFS
J4-91
SPORT_DR0
J4-31
SPORT_DR1
J4-30
SPORT_DR2
J4-29
SPORT_DR3
PF13/PPI_D13/TSCLK1/SPISEL3/CUD
J4-87
SPORT_TSCLK
PF11/PPI_D11/TFS1/CZM
J4-89
SPORT_TFS
PF12/PPI_D12/DT1PRI/SPISEL2/COG
J4-88
SPORT_DT0
PF14/PPI_D14/DT1SEC/UART1TX
J4-32
SPORT_DT1
J4-33
SPORT_DT2
J4-34
SPORT_DT3
J4-35
SPORT_INT
Future Use
Future Use
Future Use
Future Use
PG14/TSCLK0A1/MOC
PAR_RD_WR
1
J4-114
CS_B
2
J4-113
D[23:16] (Future Use)
U24
J4-9
4
A4
PF15/PPI_D15/DR1SEC/UART1RX/TACI3
NC7S32
D[0:15]
A6
B5
B6
C5
C6
D5
D6
E5
D0
D1
D2
D3
D4
D5
D6
D7
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
U17-A
A1
B2
B1
C2
C1
D2
D1
E2
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
CONB_PAR_D[0:15]
CONB_PAR_D0
CONB_PAR_D1
CONB_PAR_D2
CONB_PAR_D3
CONB_PAR_D4
CONB_PAR_D5
CONB_PAR_D6
CONB_PAR_D7
+3.3V
J4-111
C62
0.1uF
BAT54
CONB_PAR_D[0:15]
CONB_PAR_D15
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
U17-B
E1
F2
F1
G2
G1
H2
H1
J1
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
+3.3V
CONB_PAR_D8
CONB_PAR_D9
CONB_PAR_D10
CONB_PAR_D11
CONB_PAR_D12
CONB_PAR_D13
CONB_PAR_D14
CONB_PAR_D15
SPI_SEL_B
PF13/PPI_D13/TSCLK1/SPISEL3/CUD
J4-38
SPI_SEL_C
J4-39
SPI_SEL1/SPI_SS
PG4/MOSI/DT0SECA
J4-84
SPI_MOSI
CONB_PPI_DIR
J4-83
SPI_MISO
CONB_PAR_D2
PG3/MISO/DR0SECA
CONB_PPI_EN
CONB_PAR_D1
J4-82
SPI_CLK
PG12/UART1TXA
J4-41
SDA_1
J4-42
SCL_1
B
PG8/TMR4/RFS0A/UART0RX/TACI4
PG7/TMR3/DR0PRIA/UART0TX
J4-59
UART_RX
J4-62
UART_TX
A3
1DIR
A4
1OE
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
A1
B2
B1
C2
C1
D2
D1
E2
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
J4-18
J4-103
CONB_PAR_D0
CONB_PAR_D1
CONB_PAR_D2
CONB_PAR_D3
CONB_PAR_D4
CONB_PAR_D5
CONB_PAR_D6
CONB_PAR_D7
E6
F5
F6
G5
G6
H5
H6
J6
PF8/PPI_D8/DR1PRI
PF9/PPI_D9/RSCLK1/SPISEL6
PF10/PPI_D10/RFS1/SPISEL7
PF11/PPI_D11/TFS1/CZM
PF12/PPI_D12/DT1PRI/SPISEL2/COG
PF13/PPI_D13/TSCLK1/SPISEL3/CUD
PF14/PPI_D14/DT1SEC/UART1TX
PF15/PPI_D15/DR1SEC/UART1RX/TACI3
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
E1
F2
F1
G2
G1
H2
H1
J1
C64
0.1uF
J4-6
J4-20
J4-11
J4-101
J4-17
J4-28
C65
0.1uF
J4-36
J4-40
+3.3V
ARE
J4-21
PAR_RD
AWE
J4-100
PAR_WR
CS_B
J4-22
PAR_CS
J4-99
PAR_INT
PG13/UART1RXA/TACI2
CONB_PAR_D8
CONB_PAR_D9
CONB_PAR_D10
CONB_PAR_D11
CONB_PAR_D12
CONB_PAR_D13
CONB_PAR_D14
CONB_PAR_D15
J4-4
J4-102
J4-23
U18-B
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
J4-3
J4-19
CONB_PAR_D0
74LVCH16245AZRDR
2DIR
PG15/TFS0A/MII_PHYINT/RMII_MDINT
PF0/PPI_D0/DR0PRI
PF1/PPI_D1/RFS0
PF2/PPI_D2/RSCLK0
PF3/PPI_D3/DT0PRI
PF4/PPI_D4/TFS0/TACLK0
PF5/PPI_D5/TSCLK0/TACLK1
PF6/PPI_D6/DT0SEC/TACI0
PF7/PPI_D7/DR0SEC/TACI1
J3
SCL_0
A6
B5
B6
C5
C6
D5
D6
E5
C
J4-105
CONB_PAR_D3
+3.3V
J4-5
J4-16
CONB_PAR_D5
U18-A
USB_VBUS
J4-106
CONB_PAR_D4
J4
J4-79
J4-15
CONB_PAR_D6
74LVCH16245AZRDR
2OE
PJ2/SCL
J4-107
CONB_PAR_D7
J4-37
SDA_0
J4-14
CONB_PAR_D8
PF10/PPI_D10/RFS1/SPISEL7
J4-119
J4-108
CONB_PAR_D9
C75
1uF
J4-2
J4-120
J4-13
CONB_PAR_D10
C68
10nF
V-UNREG
J4-12
CONB_PAR_D11
SPI_SEL_A
J4-80
J4-110
CONB_PAR_D14
CONB_PAR_D12
E6
F5
F6
G5
G6
H5
H6
J6
J4-1
C63
0.1uF
J4-85
SDA_B
D6
VIN
CONB_PAR_D13
D8
D9
D10
D11
D12
D13
D14
D15
J4-116
J4-10
PH9/SPISEL5/ETXD2/TACLK3
PG2/SCK
+3.3V
J4-112
74LVCH16245AZRDR
C
PG1/SPISS/SPISEL1
D
J4-8
J4
PF8/PPI_D8/DR1PRI
DATE:
J4-7
ARE
A3
J4-92
PF10/PPI_D10/RFS1/SPISEL7
DIR=1: A->B; DIR=0: B->A
1DIR
PF9/PPI_D9/RSCLK1/SPISEL6
SPORT_RSCLK
D
2DIR
BMODE1_B
DNP
1OE
J4-61
R15
BMODE1
J3
RESET_IN
2OE
J4-60
MR
APPROVED:
J4-46
J4-52
J4-58
J4-63
J4-69
B
J4-75
C69
10nF
C74
1uF
J4-81
A4
J4-24
PAR_A3
J4-86
J4-97
PAR_A2
J4-93
J4-25
PAR_A1
J4-98
J4-96
PAR_A0
J4-104
PG6/DT0PRIA/TMR2/PPI_FS3
J4-26
PAR_FS3
J4-115
PG5/TMR1/PPI_FS2
J4-95
PAR_FS2
J4-117
PJ0/PP1_FS1/TMR0
J4-27
PAR_FS1
J4-118
PJ1/PPI_CLK/TMRCLK
J4-94
PAR_CLK
A[1:19]
A3
A2
74LVCH16245AZRDR
A1
J4-109
PH10/ERXD2
J4-43
GPIO_0
PH11/ETXD3
J4-78
GPIO_1
PH12/ERXD3
J4-44
GPIO_2
PH13/ERXCLK
J4-77
GPIO_3
PH14/ERXDV
J4-45
GPIO_4
PH15/COL
J4-76
GPIO_5
PH6/ERXDO
J4-47
GPIO_6
J4-74
GPIO_7
PH7/ETXD1
A
PG8/TMR4/RFS0A/UART0RX/TACI4
J4-48
TMR_A
PG6/DT0PRIA/TMR2/PPI_FS3
J4-73
TMR_B
J4-49
TMR_C
J4-72
TMR_D
Future Use
PJ0/PP1_FS1/TMR0
Future Use
J4-50
J4-71
J4-51
J4-70
J4-53
J4-68
J4-54
J4-67
J4-55
J4-66
J4-56
J4-65
J4-57
J4-64
COMPANY:
TITLE:
DRAWN:
DATED:
CHECKED:
DATED:
QUALITY CONTROL:
DATED:
RELEASED:
DATED:
Paddy Duignan
MICK McCARTHY
13-01-09
SIZE:
DRAWING NO:
SDP1Z
SCALE:
A
SYSTEM DEVELOPMENT PLATFORM
(CONNECTOR B)
CODE:
14-01-10
ANALOG DEVICES
SHEET: 6 OF 6
REV:
B