CMOS, ±5 V/+5 V/+3 V, Triple SPDT Switch
ADG633
FEATURES
FUNCTIONAL BLOCK DIAGRAM
±2 V to ±6 V dual-supply operation
2 V to 12 V single-supply operation
Automotive temperature range: −40°C to +125°C
<0.2 nA leakage currents
52 Ω on resistance over full signal range
Rail-to-rail switching operation
16-lead LFCSP and TSSOP packages
Typical power consumption: <0.1 μW
TTL-/CMOS-compatible inputs
Package upgrades to 74HC4053 and MAX4053/MAX4583
ADG633
S1B
D1
S1A
S3A
D3
S3B
S2A
D2
S2B
A0 A1 A2 EN
APPLICATIONS
SWITCHES SHOWN FOR A LOGIC 1 INPUT.
Automotive applications
Automatic test equipment
Data acquisition systems
Battery-powered systems
Communications systems
Audio and video signal routing
Relay replacement
Sample-and-hold systems
Industrial control systems
03275-001
LOGIC
Figure 1.
GENERAL DESCRIPTION
The ADG633 is a low voltage CMOS device comprising three
independently selectable single-pole, double-throw (SPDT)
switches. The device is fully specified for ±5 V, +5 V, and +3 V
supplies. The ADG633 switches are turned on with a logic low
(or high) on the appropriate control input. Each switch conducts
equally well in both directions when on and has an input signal
range that extends to the supplies. An EN input is used to enable
or disable the device. When the device is disabled, all channels
are switched off.
The ADG633 is designed on an enhanced process that provides
lower power dissipation, yet is capable of high switching speeds.
Low power consumption and an operating supply range of 2 V
to 12 V make the ADG633 ideal for battery-powered, portable
instruments. All channels exhibit break-before-make switching
action, preventing momentary shorting when switching channels.
All digital inputs have 0.8 V to 2.4 V logic thresholds, ensuring
TTL/CMOS logic compatibility when using single +5 V or dual
±5 V supplies.
The ADG633 is available in a small, 16-lead TSSOP package
and a 16-lead, 4 mm × 4 mm LFCSP package.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
Single- and dual-supply operation. The ADG633 offers
high performance and is fully specified and guaranteed
with ±5 V, +5 V, and +3 V supply rails.
Automotive temperature range: −40°C to +125°C.
Guaranteed break-before-make switching action.
Low power consumption, typically <0.1 μW.
Small, 16-lead TSSOP and 16-lead, 4 mm × 4 mm LFCSP
packages.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2003–2009 Analog Devices, Inc. All rights reserved.
ADG633
TABLE OF CONTENTS
Features .............................................................................................. 1 Absolute Maximum Ratings ............................................................6 Applications ....................................................................................... 1 ESD Caution...................................................................................6 Functional Block Diagram .............................................................. 1 Pin Configuration and Function Descriptions..............................7 General Description ......................................................................... 1 Typical Performance Characteristics ..............................................8 Product Highlights ........................................................................... 1 Terminology .................................................................................... 11 Revision History ............................................................................... 2 Test Circuits ..................................................................................... 12 Specifications..................................................................................... 3 Outline Dimensions ....................................................................... 14 Dual-Supply Operation ............................................................... 3 Ordering Guide .......................................................................... 14 Single-Supply Operation ............................................................. 4 REVISION HISTORY
11/09—Rev. 0 to Rev. A
Changes to Table 4 ............................................................................ 6
Added Table 5; Renumbered Sequentially .................................... 7
Changes to Table 6 ............................................................................ 7
Update Outline Dimensions ......................................................... 14
Changes to Ordering Guide .......................................................... 14
2/03—Revision 0: Initial Version
Rev. A | Page 2 of 16
ADG633
SPECIFICATIONS
DUAL-SUPPLY OPERATION
VDD = +5 V, VSS = −5 V, GND = 0 V, TA = −40°C to +125°C, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match
Between Channels, ΔRON
On-Resistance Flatness, RFLAT(ON)
LEAKAGE CURRENTS
Source Off Leakage, IS(OFF)
+25°C
B Version
−40°C to +85°C
VSS to VDD
52
75
0.8
1.3
9
12
90
100
1.8
2
13
14
±0.005
±0.2
Drain Off Leakage, ID(OFF)
Channel On Leakage, ID(ON), IS(ON)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
Y Version
−40°C to +125°C
±5
±0.005
tTRANSITION
V
Ω typ
Ω max
Ω typ
VDD = +4.5 V, VSS = −4.5 V
VS = ±4.5 V, IS = 1 mA; see Figure 20
VS = ±4.5 V, IS = 1 mA; see Figure 20
VS = +3.5 V, IS = 1 mA
Ω max
Ω typ
Ω max
nA typ
VS = +3.5 V, IS = 1 mA
VDD = +5 V, VSS = −5 V, VS = ±3 V, IS = 1 mA
VDD = +5 V, VSS = −5 V, VS = ±3 V, IS = 1 mA
VDD = +5.5 V, VSS = −5.5 V
VD = ±4.5 V, VS = +4.5 V; see Figure 21
nA max
VD = ±4.5 V, VS = +4.5 V; see Figure 21
nA typ
VD = ±4.5 V, VS = + 4.5 V; see Figure 22
±5
nA max
VD = ±4.5 V, VS = + 4.5 V; see Figure 22
±0.005
±0.2
±5
nA typ
nA max
VD = VS = ±4.5 V; see Figure 23
VD = VS = ±4.5 V; see Figure 23
2.4
0.8
0.005
2
60
90
V min
V max
μA typ
μA max
pF typ
ns typ
110
130
VIN = VINL or VINH
VIN = VINL or VINH
RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 24
ns max
RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 24
ns typ
RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 26
tON (EN)
70
95
25
120
135
tOFF (EN)
ns max
ns typ
RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 26
RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 26
40
40
45
50
Break-Before-Make Time Delay, tBBM
ns max
ns typ
ns min
pC typ
pC max
dB typ
% typ
dB typ
MHz typ
pF typ
pF typ
pF typ
RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 26
RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 3 V; see Figure 25
RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 3 V; see Figure 25
VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 27
VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 27
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28
RL = 600 Ω, 2 V p-p, f = 20 Hz to 20 kHz
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 30
RL = 50 Ω, CL = 5 pF; see Figure 29
f = 1 MHz
f = 1 MHz
f = 1 MHz
VDD = +5.5 V, VSS = −5.5 V
Digital inputs = 0 V or 5.5 V
Digital inputs = 0 V or 5.5 V
Digital inputs = 0 V or 5.5 V
Digital inputs = 0 V or 5.5 V
10
Charge Injection
Off Isolation
Total Harmonic Distortion, THD + N
Channel-to-Channel Crosstalk
−3 dB Bandwidth
CS(OFF)
CD(OFF)
CD(ON), CS(ON)
POWER REQUIREMENTS
IDD
2
4
−90
0.025
−90
580
4
7
12
0.01
1
ISS
0.01
1
1
Test Conditions/Comments
±0.2
±1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 1
Unit
Guaranteed by design; not subject to production test.
Rev. A | Page 3 of 16
μA typ
μA max
μA typ
μA max
ADG633
SINGLE-SUPPLY OPERATION
VDD = 5 V, VSS = 0 V, GND = 0 V, TA = −40°C to +125°C, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match
Between Channels, ΔRON
On-Resistance Flatness, RFLAT(ON)
LEAKAGE CURRENTS
Source Off Leakage, IS(OFF)
Drain Off Leakage, ID(OFF)
Channel On Leakage, ID(ON), IS(ON)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
+25°C
B Version
−40°C to +85°C
Y Version
−40°C to +125°C
Unit
Test Conditions/Comments
V
Ω typ
Ω max
Ω typ
VDD = 4.5 V, VSS = 0 V
VS = 0 V to 4.5 V, IS = 1 mA; see Figure 20
VS = 0 V to 4.5 V, IS = 1 mA; see Figure 20
VS = +3.5 V, IS = 1 mA
Ω max
Ω typ
±5
nA typ
nA max
nA typ
nA max
VS = +3.5 V, IS = 1 mA
VDD = 5 V, VSS = 0 V, VS = 1.5 V to 4 V, IS = 1 mA
VDD = 5.5 V
VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 21
VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 21
VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 22
VS = 1 V/4.5 V, VD = 4.5 V/1 V; see Figure 22
±5
nA typ
nA max
VS = VD = 1 V or 4.5 V; see Figure 23
VS = VD = 1 V or 4.5 V; see Figure 23
0 to VDD
85
150
4.5
160
200
8
13
9
14
10
16
±0.005
±0.2
±0.005
±0.2
±5
±0.005
±0.2
2.4
0.8
0.005
±1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 1
tTRANSITION
2
VIN = VINL or VINH
VIN = VINL or VINH
tON (EN)
100
150
100
150
25
190
220
tOFF (EN)
ns max
ns typ
RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 26
RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 26
35
90
45
50
Break-Before-Make Time Delay, tBBM
ns max
ns typ
ns min
pC typ
pC max
dB typ
dB typ
MHz typ
pF typ
pF typ
pF typ
RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 26
RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 3 V; see Figure 25
RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 3 V; see Figure 25
VS = 2.5 V, RS = 0 Ω, CL = 1 nF; see Figure 27
VS = 2.5 V, RS = 0 Ω, CL = 1 nF; see Figure 27
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 30
RL = 50 Ω, CL = 5 pF; see Figure 29
f = 1 MHz
f = 1 MHz
f = 1 MHz
VDD = 5.5 V
Digital inputs = 0 V or 5.5 V
Digital inputs = 0 V or 5.5 V
190
220
10
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth
CS(OFF)
CD(OFF)
CD(ON), CS(ON)
POWER REQUIREMENTS
IDD
0.5
1
−90
−90
520
5
8
12
0.01
1
1
V min
V max
μA typ
μA max
pF typ
Guaranteed by design; not subject to production test.
Rev. A | Page 4 of 16
ns typ
ns max
ns typ
RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 24
RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 24
RL = 300 Ω, CL = 35 pF, VS = 3 V; see Figure 26
μA typ
μA max
ADG633
VDD = 2.7 V to 3.6 V, VSS = 0 V, GND = 0 V, TA = −40°C to +125°C, unless otherwise noted.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match
Between Channels, ΔRON
LEAKAGE CURRENTS
Source Off Leakage, IS(OFF)
Drain Off Leakage, ID(OFF)
Channel On Leakage, ID(ON), IS(ON)
+25°C
B Version
−40°C to +85°C
0 to VDD
185
300
2
350
400
4.5
6
7
±0.005
±0.2
±0.005
±0.2
±0.005
±0.2
±5
±5
±5
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 1
tTRANSITION
Y Version
−40°C to +125°C
Test Conditions/Comments
V
Ω typ
Ω max
Ω typ
VDD = 2.7 V, VSS = 0 V
VS = 0 V to 2.7 V, IS = 0.1 mA; see Figure 20
VS = 0 V to 2.7 V, IS = 0.1 mA; see Figure 20
VS = +1.5 V, IS = 0.1 mA
Ω max
VS = +1.5 V, IS = 0.1 mA
VDD = 3.3 V
VS = 1 V/3 V, VD = 3 V/1 V; see Figure 21
VS = 1 V/3 V, VD = 3 V/1 V; see Figure 21
VS = 1 V/3 V, VD = 3 V/1 V; see Figure 22
VS = 1 V/3 V, VD = 3 V/1 V; see Figure 22
VS = VD = 1 V or 3 V; see Figure 23
VS = VD = 1 V or 3 V; see Figure 23
nA typ
nA max
nA typ
nA max
nA typ
nA max
2.0
V min
0.5
V max
μA typ
VIN = VINL or VINH
±1
μA max
VIN = VINL or VINH
0.005
2
pF typ
tON (EN)
170
300
200
310
30
380
420
tOFF (EN)
ns max
ns typ
RL = 300 Ω, CL = 35 pF, VS = 1.5 V; see Figure 26
RL = 300 Ω, CL = 35 pF, VS = 1.5 V; see Figure 26
40
180
55
75
Break-Before-Make Time Delay, tBBM
ns max
ns typ
ns min
pC typ
pC max
dB typ
dB typ
MHz typ
pF typ
pF typ
pF typ
RL = 300 Ω, CL = 35 pF, VS = 1.5 V; see Figure 26
RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 1.5 V; see Figure 25
RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 1.5 V; see Figure 25
VS = 1.5 V, RS = 0 Ω, CL = 1 nF; see Figure 27
VS = 1.5 V, RS = 0 Ω, CL = 1 nF; see Figure 27
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 30
RL = 50 Ω, CL = 5 pF; see Figure 29
f = 1 MHz
f = 1 MHz
f = 1 MHz
VDD = 3.3 V
Digital inputs = 0 V or 3.3 V
Digital inputs = 0 V or 3.3 V
370
400
10
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth
CS(OFF)
CD(OFF)
CD(ON), CS(ON)
POWER REQUIREMENTS
IDD
1
2
−90
−90
500
5
8
12
0.01
1
1
Unit
Guaranteed by design; not subject to production test.
Rev. A | Page 5 of 16
ns typ
ns max
ns typ
RL = 300 Ω, CL = 35 pF, VS = 1.5 V; see Figure 24
RL = 300 Ω, CL = 35 pF, VS = 1.5 V; see Figure 24
RL = 300 Ω, CL = 35 pF, VS = 1.5 V; see Figure 26
μA typ
μA max
ADG633
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter
VDD to VSS
VDD to GND
VSS to GND
Analog Inputs1
Digital Inputs1
Peak Current, S or D
Continuous Current, S or D
Operating Temperature Range
Storage Temperature Range
Junction Temperature
θJA Thermal Impedance
16-Lead TSSOP
16-Lead LFCSP, 4-Layer Board
Lead Soldering
Lead Temperature, Soldering
(10 sec)
IR Reflow, Peak Temperature
(<20 sec)
(Pb-Free) Soldering
Reflow, Peak Temperature
Time at Peak Temperature
ESD
Rating
13 V
−0.3 V to +13 V
+0.3 V to −6.5 V
VSS − 0.3 V to VDD + 0.3 V
GND − 0.3 V to VDD + 0.3 V or
10 mA, whichever occurs first
40 mA (pulsed at 1 ms, 10%
duty cycle maximum)
20 mA
−40°C to +125°C
−65°C to +150°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Only one absolute maximum rating can be applied at any one time.
ESD CAUTION
150.4°C/W
70°C/W
300°C
220°C
260(+0/−5)°C
20 sec to 40 sec
4 kV
Overvoltages at Ax, EN, S, or D are clamped by internal diodes. Current
should be limited to the maximum ratings given.
1
Rev. A | Page 6 of 16
ADG633
15
D2
D3 2
S3B 3
14
D1
S3A 3
S1B
12
S1A
EN 6
11
A0
VSS 7
10
A1
GND 8
9
A2
S3A 5
TOP VIEW
(Not to Scale)
12 D1
ADG633
11 S1B
TOP VIEW
(Not to Scale)
10 S1A
VSS 5
13
D3 4
EN 4
9 A0
NOTES
1. THE EXPOSED PADDLE CAN BE LEFT FLOATING
OR BE TIED TO VDD, VSS, OR GND.
03275-002
ADG633
PIN 1
INDICATOR
A1 8
S2A 2
S3B 1
A2 7
VDD
03275-003
15 S2B
16 S2A
16
GND 6
S2B 1
14 VDD
13 D2
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. LFCSP Pin Configuration
Figure 2. TSSOP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
TSSOP LFCSP
1
15
2
16
3
1
4
2
5
3
6
4
7
5
Mnemonic
S2B
S2A
S3B
D3
S3A
EN
VSS
8
9
10
11
12
13
14
15
16
N/A
GND
A2
A1
A0
S1A
S1B
D1
D2
VDD
EP
6
7
8
9
10
11
12
13
14
EP
Description
Source Terminal of Multiplexer 2. Can be an input or output.
Source Terminal of Multiplexer 2. Can be an input or output.
Source Terminal of Multiplexer 3. Can be an input or output.
Drain Terminal of Multiplexer 3. Can be an input or output.
Source Terminal of Multiplexer 3. Can be an input or output.
Digital Control Input. Disables all multiplexers when set high.
Most Negative Power Supply Terminal. Tie this pin to GND when using the device with single-supply
voltages.
Ground (0 V) Reference.
Digital Control Input.
Digital Control Input.
Digital Control Input.
Source Terminal of Multiplexer 1. Can be an input or output.
Source Terminal of Multiplexer 1. Can be an input or output.
Drain Terminal of Multiplexer 1. Can be an input or output.
Drain Terminal of Multiplexer 2. Can be an input or output.
Most Positive Power Supply Terminal.
Exposed Paddle. The exposed paddle can be left floating or be tied to VDD, VSS, or GND.
Table 6. ADG633 Truth Table
A2
X1
0
0
0
0
1
1
1
1
1
A1
X1
0
0
1
1
0
0
1
1
A0
X1
0
1
0
1
0
1
0
1
EN
1
0
0
0
0
0
0
0
0
Switch S1A-D1
Off
On
Off
On
Off
On
Off
On
Off
Switch S1B-D1
Switch Condition
Switch S2A-D2
Switch S2B-D2
Switch S2A-D3
Switch S3B-D3
Off
Off
On
Off
On
Off
On
Off
On
Off
On
On
Off
Off
On
On
Off
Off
Off
On
On
On
On
Off
Off
Off
Off
Off
Off
Off
Off
Off
On
On
On
On
X = the logic state does not matter; it can be either 0 or 1.
Rev. A | Page 7 of 16
Off
Off
Off
On
On
Off
Off
On
On
ADG633
TYPICAL PERFORMANCE CHARACTERISTICS
100
TA = 25°C
VDD, VSS = ±2.7V
90
VDD, VSS = ±3V
120
VDD, VSS = ±3.3V
70
ON RESISTANCE (Ω)
ON RESISTANCE (Ω)
80
VDD = 5V
VSS = 0V
140
60
50
40
30
100
+125°C
+85°C
80
+25°C
60
–40°C
40
VDD, VSS = ±4.5V
20
VDD, VSS = ±5V
20
10
–1.5
0.5
2.5
0
03275-004
–3.5
4.5
VD, VS (V)
0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
5.0
4.5
VD, VS (V)
Figure 4. On Resistance vs. VD (VS), Dual Supplies
Figure 7. On Resistance vs. VD (VS) for Various Temperatures, Single Supply
250
300
VDD = 3V
VSS = 0V
TA = 25°C
VDD = 2.7V
250
200
+125°C
VDD = 3V
ON RESISTANCE (Ω)
ON RESISTANCE (Ω)
0.5
03275-007
VDD, VSS = ±5.5V
0
–5.5
150
VDD = 3.3V
VDD = 4.5V
100
VDD = 5V
VDD = 5.5V
VDD = 10V
50
+85°C
200
150
+25°C
–40°C
100
50
0
2
4
6
8
12
10
VD, VS (V)
0
03275-005
0
0
1.0
1.5
2.0
3.0
2.5
VD, VS (V)
Figure 5. On Resistance vs. VD (VS), Single Supply
Figure 8. On Resistance vs. VD (VS) for Various Temperatures, Single Supply
100
1.5
VDD = 5V
90 VSS = 5V
VDD = +5V
VSS = –5V
VD = ±4V
1.0 V = 4V
S
LEAKAGE CURRENT (nA)
80
ON RESISTANCE (Ω)
0.5
03275-008
VDD = 12V
70
60
+125°C
50
+85°C
40
+25°C
30
–40°C
20
0.5
ID(OFF)
IS(OFF)
0
IS(ON), ID(ON)
–0.5
–1.0
–4
–3
–2
–1
0
VD, VS (V)
1
2
3
4
5
–1.5
03275-006
0
–5
0
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 6. On Resistance vs. VD (VS) for Various Temperatures, Dual Supplies
Rev. A | Page 8 of 16
Figure 9. Leakage Current vs. Temperature, Dual Supplies
03275-009
10
ADG633
1.5
300
VDD = +3V
VSS = 0V
VD = ±2.4V
VS = 1V
VDD = 3V
0.5
200
IS(OFF), ID(OFF)
0
–0.5
150
tON
IS(ON), ID(ON)
20
40
60
80
100
0
–40
03275-010
0
120
TEMPERATURE (°C)
0
12
ATTENUATION (dB)
8
6
40
60
80
100
120
VDD = +5V
VSS = –5V
TA = 25°C
VDD = +3V
VSS = 0V
VDD = +5V
VSS = –5V
–3
–2
–1
0
1
2
3
4
5
VS (V)
–10
03275-011
–4
–6
–8
VDD = +5V
VSS = 0V
–2
–4
100k
10M
100M
FREQUENCY (Hz)
Figure 11. Charge Injection vs. Source Voltage
Figure 14. On Response vs. Frequency
100
0
VDD = +5V
90 VSS = –5V
–20
80
1M
03275-014
4
–4
–5
20
–2
10
0
0
Figure 13. tON/tOFF Times vs. Temperature, Single Supply
TA = 25°C
2
–20
TEMPERATURE (°C)
Figure 10. Leakage Current vs. Temperature, Single Supply
14
VDD = 3V
tOFF
03275-013
50
–1.5
VDD = +5V
VSS = –5V
TA = 25°C
tON
OFF ISOLATION (dB)
70
60
50
40
30
–40
–60
–80
tOFF
20
–100
10
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
–120
03275-012
0
–40
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 12. tON/tOFF Times vs. Temperature, Dual Supplies
Figure 15. Off Isolation vs. Frequency
Rev. A | Page 9 of 16
03275-015
QINJ (pC)
VDD = 5V
100
–1.0
TIME (ns)
VSS = 0V
250
TIME (ns)
LEAKAGE CURRENT (nA)
VDD = +5V
VSS = 0V
VD = ±4V
1.0 V = 1V
S
ADG633
0
VDD = –5V
–10 VSS = +5V
T = 25°C
–20 A
10k
VSS = 0V
1k
VDD = 12V
–40
100
–50
IDD (µA)
CROSSTALK (dB)
–30
–60
–70
VDD = 5V
10
–80
VDD = 3V
1
–90
–100
0.1
–110
100k
1M
10M
0.01
03275-016
–130
100M
FREQUENCY (Hz)
0
6
8
10
12
10
12
Figure 18. VDD Current vs. Logic Level
3.0
1
0.01
20
100
1k
FREQUENCY (Hz)
10k
20k
03275-017
0.1
Figure 17. THD + Noise vs. Frequency
2.5
2.0
1.5
1.0
0.5
0
0
2
4
6
8
VDD (V)
Figure 19. Logic Threshold Voltage vs. VDD
Rev. A | Page 10 of 16
03275-019
VDD = +5V
VSS = –5V
TA = 25°C
LOGIC THRESHOLD VOLTAGE (V)
600Ω
INPUT AND OUTPUT
10
THD + N (%)
4
V (EN) (V)
Figure 16. Crosstalk vs. Frequency
100
2
03275-018
–120
ADG633
TERMINOLOGY
VDD
Most positive power supply potential.
VINH
Minimum input voltage for Logic 1.
VSS
Most negative power supply potential.
IINL, IINH
Input current of the digital input.
IDD
Positive supply current.
CS(OFF)
Off switch source capacitance. Measured with reference to
ground.
ISS
Negative supply current.
CD(OFF)
Off switch drain capacitance. Measured with reference to
ground.
GND
Ground (0 V) reference.
CD(ON), CS(ON)
On switch capacitance. Measured with reference to ground.
S
Source terminal. Can be an input or output.
CIN
Digital input capacitance.
D
Drain terminal. Can be an input or output.
AX
Logic control input.
tON (EN)
Delay between applying the digital control input and the output
switching on (see Figure 26).
EN
Active low digital input. When EN is high, the device is disabled
and all switches are off. When EN is low, the Ax logic inputs
determine the on switches.
tOFF (EN)
Delay between applying the digital control input and the output
switching off (see Figure 26).
VD, VS
Analog voltage on Terminal D and Terminal S.
RON
Ohmic resistance between Terminal D and Terminal S.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
ΔRON
On-resistance match between any two channels, that is,
RONMAX − RONMIN.
Off Isolation
A measure of unwanted signal coupling through an off switch.
RFLAT(ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance as measured over the specified
analog signal range.
IS(OFF)
Source leakage current with the switch off.
ID(OFF)
Drain leakage current with the switch off.
ID(ON), IS(ON)
Channel leakage current with the switch on.
tBBM
On time, measured between 80% points of both switches when
switching from one address state to another.
Crosstalk
A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.
Bandwidth
The frequency at which the output is attenuated by 3 dB.
On Response
The frequency response of the on switch.
Insertion Loss
The loss due to the on resistance of the switch.
VINL
Maximum input voltage for Logic 0.
Rev. A | Page 11 of 16
ADG633
TEST CIRCUITS
IDS
V1
ID(ON)
D
03275-020
RON = V1/IDS
A
S
VD
Figure 22. Drain Off Leakage
ID(OFF)
S1A
A
S1B
D
A
NC = NO CONNECT
Figure 20. On Resistance
IS(OFF)
D
VDD
VSS
VDD
VSS
D
ID(ON)
A
VD
VS
03275-021
VD
VS
Figure 21. Source Off Leakage
VDD
Figure 23. Channel On Leakage
0.1µF
VDD
A2
3V
ADDRESS
DRIVE (VIN)
VSS
S1A
VS1A
S1B
VS1B
A1
50Ω
A0
GND
VSS
0.1µF
VIN
03275-023
EN
50%
0V
90%
VOUT
ADG633
90%
D
EN
50%
VOUT
RL
300Ω
GND
CL
35pF
tTRANSITION
tTRANSITION
03275-024
VS
S
NC
03275-022
S
Figure 24. Transition Time, tTRANSITION
VDD
VSS
0.1µF
0.1µF
3V
VDD
A2
50Ω
VS
S1A
A1
0V
S1B
A0
ADG633
VOUT
D1
EN
GND
RL
300Ω
CL
35pF
VOUT
80%
80%
tBBM
Figure 25. Break-Before-Make Delay, tBBM
Rev. A | Page 12 of 16
03275-025
VIN
ADDRESS
DRIVE (VIN)
VSS
ADG633
VDD
VSS
0.1µF
0.1µF
VDD
A2
3V
ENABLE
DRIVE (VIN)
VSS
VS
S1A
tOFF (EN)
S1B
VOUT
ADG633
0.9VOUT
0.9VOUT
0V
03275-026
OUTPUT
CL
35pF
RL
300Ω
GND
50Ω
VOUT
D1
EN
VIN
50%
0V
A1
A0
50%
tON (EN)
Figure 26. Enable Delay, tON (EN), tOFF (EN)
VDD
VSS
A2 VDD
VSS
LOGIC INPUT
(VIN)
ADG633
0V
3V
A0
RS
D
S
VS
VOUT
CL
1nF
EN
VIN
VOUT
ΔVOUT
QINJ = CL × ΔVOUT
GND
03275-027
A1
Figure 27. Charge Injection
VDD
0.1µF
0.1µF
0.1µF
VDD
NETWORK
ANALYZER
VSS
A2
A1
S
0.1µF
VDD
A1
50Ω
S
A0
50Ω
VS
VS
D
D
VOUT
EN
RL
50Ω
GND
VOUT
VS
INSERTION LOSS = 20 log
Figure 28. Off Isolation
VDD
A2
VSS
0.1µF
VDD
VSS
A1
A0
VS
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
Figure 29. Bandwidth
0.1µF
50Ω
RL
50Ω
GND
OFF ISOLATION = 20 log
NETWORK
ANALYZER
VOUT
EN
03275-028
LOGIC 1
NETWORK
ANALYZER
VSS
A2
50Ω
A0
VSS
50Ω
NETWORK
ANALYZER
EN
ADG633
DA
SA
VOUT
RL
50Ω
DB
GND
CROSSTALK = 20 log
Figure 30. Channel-to-Channel Crosstalk
Rev. A | Page 13 of 16
VOUT
VS
03275-029
VSS
03275-030
VDD
ADG633
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.30
0.19
0.65
BSC
COPLANARITY
0.10
SEATING
PLANE
0.75
0.60
0.45
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 31. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
4.00
BSC SQ
0.60 MAX
0.60 MAX
3.75
BSC SQ
0.75
0.60
0.50
0.80 MAX
0.65 TYP
12° MAX
1.00
0.85
0.80
0.65 BSC
TOP
VIEW
0.35
0.30
0.25
PIN 1
INDICATOR
1
2.25
2.10 SQ
1.95
9
8
5
4
0.25 MIN
1.95 BSC
0.05 MAX
0.02 NOM
SEATING
PLANE
16
13
12
0.20 REF
COPLANARITY
0.08
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VGGC
072808-A
PIN 1
INDICATOR
(BOTTOM VIEW)
Figure 32. 16-Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(CP-16-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADG633YRU
ADG633YRU-REEL7
ADG633YRUZ 1
ADG633YRUZ-REEL71
ADG633YCP
ADG633YCP-REEL7
ADG633YCPZ1
ADG633YCPZ-REEL71
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
16-Lead Thin Shrink Small Outline Package (TSSOP)
16-Lead Thin Shrink Small Outline Package (TSSOP)
16-Lead Thin Shrink Small Outline Package (TSSOP)
16-Lead Thin Shrink Small Outline Package (TSSOP)
16-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
16-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
16-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
16-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
Z = RoHS Compliant Part.
Rev. A | Page 14 of 16
Package Option
RU-16
RU-16
RU-16
RU-16
CP-16-4
CP-16-4
CP-16-4
CP-16-4
ADG633
NOTES
Rev. A | Page 15 of 16
ADG633
NOTES
©2003–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03275-0-11/09(A)
Rev. A | Page 16 of 16