High Voltage, Latch-Up Proof,
Triple SPDT Switches
ADG5433W
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Qualified for automotive applications
Fully specified at +12 V, +36 V , ±15 V, and ±20 V
Latch-up proof
Low on resistance (13.5 Ω)
9 V to 40 V single-supply operation
±9 V to ±22 V dual-supply operation
VSS to VDD analog signal range
Human body model (HBM) ESD rating: 8 kV
ADG5433W
S1A
D1
S1B
S3B
D3
S2B
S3A
D2
S2A
Relay replacement
Automatic test equipment
Data acquisition
Instrumentation
Avionics
Audio and video switching
Communication systems
IN1 IN2 IN3 EN
SWITCHES SHOWN FOR
A LOGIC 1 INPUT.
Figure 1.
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG5433W is a monolithic industrial CMOS analog
switch comprising three independently selectable single-pole,
double-throw (SPDT) switches.
1.
All channels exhibit break-before-make switching action that
prevents momentary shorting when switching channels. An EN
input on the ADG5433W (TSSOP package) is used to enable or
disable the device. When disabled, all channels are switched off.
2.
3.
The ultralow on resistance and on-resistance flatness of these
switches make them ideal solutions for data acquisition and gain
switching applications, where low distortion is critical.
4.
5.
6.
Rev. A
10656-001
LOGIC
APPLICATIONS
Trench Isolation Guards Against Latch-Up.
A dielectric trench separates the P and N channel transistors
thereby preventing latch-up even under severe overvoltage
conditions.
Low RON.
Dual-Supply Operation.
For applications where the analog signal is bipolar, the
ADG5433W can be operated from dual supplies up
to ±22 V.
Single-Supply Operation.
For applications where the analog signal is unipolar, the
ADG5433W can be operated from a single-rail power
supply up to 40 V.
3 V logic compatible digital inputs: VINH = 2.0 V, VINL = 0.8 V.
No VL logic power supply required.
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Technical Support
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ADG5433W
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ............................................................8
Applications ....................................................................................... 1
ESD Caution...................................................................................8
Functional Block Diagram .............................................................. 1
Pin Configuration and Function Descriptions..............................9
General Description ......................................................................... 1
Typical Performance Characteristics ........................................... 10
Product Highlights ........................................................................... 1
Test Circuits ..................................................................................... 14
Revision History ............................................................................... 2
Terminology .................................................................................... 16
Specifications..................................................................................... 3
Trench Isolation .............................................................................. 17
±15 V Dual Supply ....................................................................... 3
Applications Information .............................................................. 18
±20 V Dual Supply ....................................................................... 4
Outline Dimensions ....................................................................... 19
12 V Single Supply ........................................................................ 5
Ordering Guide .......................................................................... 19
36 V Single Supply ........................................................................ 6
Automotive Products ................................................................. 19
Continuous Current per Channel, Sx or Dx ............................. 7
REVISION HISTORY
4/13—Revision A: Initial Version
Rev. A | Page 2 of 20
Data Sheet
ADG5433W
SPECIFICATIONS
±15 V DUAL SUPPLY
VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between
Channels, ∆RON
On-Resistance Flatness, RFLAT (ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Drain Off Leakage, ID (Off )
Channel On Leakage, ID (On), IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
Min
Typ 1
Max
Unit
13.5
VDD to VSS
22
V
Ω
0.3
1.4
Ω
1.8
3
Ω
±0.05
±0.1
±0.1
±10
±30
±30
nA
nA
nA
2.0
0.8
0.002
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 2
Transition Time, tTRANSITION
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
Charge Injection, QINJ
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion + Noise
6
21
−3 dB Bandwidth
Insertion Loss
CS (Off )
CD (Off )
CD (On), CS (On)
POWER REQUIREMENTS
IDD
1
2
272
274
140
±9
ns
ns
ns
ns
pC
dB
dB
%
VS = ±10 V, IS = −10 mA, VDD = +13.5 V, VSS =
−13.5 V; see Figure 23
VS = ±10 V, IS = −10 mA
VS = ±10 V, IS = −10 mA
VDD = +16.5 V, VSS = −16.5 V
VS = ±10 V, VD =  10 V; see Figure 22
VS = ±10 V, VD =  10 V; see Figure 22
VS = VD = ±10 V; see Figure 22
VIN = VGND or VDD
45
70
µA
RL = 300 Ω, CL = 35 pF, VS = 10 V
RL = 300 Ω, CL = 35 pF, VS = 10 V; see Figure 30
RL = 300 Ω, CL = 35 pF, VS = 10 V; see Figure 30
RL = 300 Ω, CL = 35 p,F VS1 = VS2 = 10 V; see Figure 29
VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 31
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 25
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 24
RL = 1 kΩ, 15 V p-p, f = 20 Hz to 20 kHz;
see Figure 26
RL = 50 Ω, CL = 5 pF; see Figure 27
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 27
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = +16.5 V, VSS = −16.5 V
Digital inputs = 0 V or VDD
0.001
1
µA
Digital inputs = 0 V or VDD
±22
V
GND = 0 V
145
−0.9
14
24
53
ISS
VDD/VSS
157
160
91
45
130
−60
−60
0.01
V
V
µA
µA
pF
Test Conditions/Comments
MHz
dB
pF
pF
pF
Typical specifications represent average readings at 25°C.
Guaranteed by design; not subject to production test.
Rev. A | Page 3 of 20
ADG5433W
Data Sheet
±20 V DUAL SUPPLY
VDD = +20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between Channels,
∆RON
On-Resistance Flatness, RFLAT (ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Drain Off Leakage, ID (Off )
Channel On Leakage, ID (On), IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
Min
Typ 1
Max
Unit
12.5
VDD to VSS
21
V
Ω
0.3
1.4
Ω
2.3
3.5
Ω
±0.05
±0.1
±0.1
±10
±30
±30
nA
nA
nA
2.0
0.8
0.002
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 2
Transition Time, tTRANSITION
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
6
17
Charge Injection, QINJ
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion + Noise
−3 dB Bandwidth
Insertion Loss
CS (Off )
CD (Off )
CD (On), CS (On)
POWER REQUIREMENTS
IDD
1
2
±9
253
253
130
ns
ns
ns
ns
176
−60
−60
0.012
pC
dB
dB
%
140
−0.8
15
23
52
MHz
dB
pF
pF
pF
50
70
0.001
ISS
VDD/VSS
150
152
90
36
V
V
µA
µA
pF
110
1
±22
Typical specifications represent average readings at 25°C.
Guaranteed by design; not subject to production test.
Rev. A | Page 4 of 20
µA
µA
µA
µA
V
Test Conditions/Comments
VS = ±15 V, IS = −10 mA, VDD = +18 V, VSS =
−18 V; see Figure 23
VS = ±15 V, IS = −10 mA
VS = ±15 V, IS = −10 mA
VDD = +22 V, VSS = −22 V
VS = ±15 V, VD =  15 V; see Figure 22
VS = ±15 V, VD =  15 V; see Figure 22
VS = VD = ±15 V; see Figure 22
VIN = VGND or VDD
RL = 300 Ω, CL = 35 pF, VS = 10 V
RL = 300 Ω, CL = 35 pF, VS = 10 V; see Figure 30
RL = 300 Ω, CL = 35 pF, VS = 10 V; see Figure 30
RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 10 V; see
Figure 29
VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 31
RL = 50 Ω, CL = 5 pF, f = 1MHz; see Figure 25
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 24
RL = 1 kΩ, 20 V p-p, f = 20 Hz to 20 kHz; see
Figure 26
RL = 50 Ω, CL = 5 pF; see Figure 27
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 27
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VS = 0 V, f = 1 MHz
VDD = +22 V, VSS = −22 V
Digital inputs = 0 V or VDD
Digital inputs = 0 V or VDD
GND = 0 V
Data Sheet
ADG5433W
12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between Channels,
∆RON
On-Resistance Flatness, RFLAT (ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Drain Off Leakage, ID (Off )
Channel On Leakage, ID (On), IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
Min
Typ 1
Max
Unit
26
0 V to VDD
42
V
Ω
0.3
1.6
Ω
5.5
12
Ω
±0.05
±0.1
±0.1
±10
±30
±30
nA
nA
nA
2.0
0.8
0.002
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 2
Transition Time, tTRANSITION
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
6
54
Charge Injection, QINJ
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion + Noise
−3 dB Bandwidth
Insertion Loss
CS (Off )
CD (Off )
CD (On), CS (On)
POWER REQUIREMENTS
IDD
VDD
1
2
220
228
90
106
ns
ns
ns
ns
60
−60
−60
0.1
pC
dB
dB
%
150
−0.8
18
28
54
MHz
dB
pF
pF
pF
40
50
9
400
426
151
V
V
µA
µA
pF
65
40
Typical specifications represent average readings at 25°C.
Guaranteed by design; not subject to production test.
Rev. A | Page 5 of 20
µA
µA
V
Test Conditions/Comments
VS = 0 V to 10 V, IS = −10 mA, VDD = 10.8 V, VSS
= 0 V; see Figure 23
VS = 0 V to 10 V, IS = −10 mA
VS = 0 V to 10 V, IS = −10 mA
VDD = 13.2 V, VSS = 0 V
VS = 1 V/10 V, VD = 10 V/1 V; see Figure 22
VS = 1 V/10 V, VD = 10 V/1 V; see Figure 22
VS = VD = 1 V/10 V; see Figure 22
VIN = VGND or VDD
RL = 300 Ω, CL = 35 pF, VS = 8 V
RL = 300 Ω, CL = 35 pF, VS = 8 V; see Figure 30
RL = 300 Ω, CL = 35 pF, VS = 8 V; see Figure 30
RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 8 V; see
Figure 29
VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 31
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 25
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 24
RL = 1 kΩ, 6 V p-p, f = 20 Hz to 20 kHz; see
Figure 26
RL = 50 Ω, CL = 5 pF; see Figure 27
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 27
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VS = 6 V, f = 1 MHz
VDD = 13.2 V
Digital inputs = 0 V or VDD
GND = 0 V, VSS = 0 V
ADG5433W
Data Sheet
36 V SINGLE SUPPLY
VDD = 36 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 4.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, RON
On-Resistance Match Between Channels,
∆RON
On-Resistance Flatness, RFLAT (ON)
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Drain Off Leakage, ID (Off )
Channel On Leakage, ID (On), IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
Min
Typ 1
Max
Unit
14.5
0 V to VDD
23
V
Ω
0.3
1.4
Ω
3.5
6.5
Ω
±0.05
±0.1
±0.1
±10
±30
±30
nA
nA
nA
2.0
0.8
0.002
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 2
Transition Time, tTRANSITION
tON (EN)
tOFF (EN)
Break-Before-Make Time Delay, tD
6
21
Charge Injection, QINJ
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion + Noise
−3 dB Bandwidth
Insertion Loss
CS (Off )
CD (Off )
CD (On), CS (On)
POWER REQUIREMENTS
IDD
VDD
1
2
VS = 0 V to 30 V, IS = −10 mA, VDD = 32.4 V,
VSS = 0 V; see Figure 23
VS = 0 V to 30 V, IS = −10 mA
VS = 0 V to 30 V, IS = −10 mA
VDD = 39.6 V, VSS = 0 V
VS = 1 V/30 V, VD = 30 V/1 V; see Figure 22
VS = 1 V/30 V, VD = 30 V/1 V; see Figure 22
VS = VD = 1 V/30 V; see Figure 22
V
V
µA
µA
pF
VIN = VGND or VDD
180
289
ns
RL = 300 Ω, CL = 35 pF, VS = 18 V
176
98
50
268
129
ns
ns
ns
RL = 300 Ω, CL = 35 pF, VS = 18 V; see Figure 30
RL = 300 Ω, CL = 35 pF, VS = 18 V; see Figure 30
RL = 300 Ω, CL = 35 pF, VS1 = VS2 = 18 V; see
Figure 29
VS = 18 V, RS = 0 Ω, CL = 1 nF; see Figure 31
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 25
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 24
RL = 1 kΩ, 18 V p-p, f = 20 Hz to 20 kHz; see
Figure 26
RL = 50 Ω, CL = 5 pF; see Figure 27
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 27
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
VS = 18 V, f = 1 MHz
VDD = 39.6 V
Digital inputs = 0 V or VDD
150
−60
−60
0.4
pC
dB
dB
%
135
−1
18
28
46
MHz
dB
pF
pF
pF
80
100
9
Test Conditions/Comments
130
40
Typical specifications represent average readings at 25°C.
Guaranteed by design; not subject to production test.
Rev. A | Page 6 of 20
µA
µA
V
GND = 0 V, VSS = 0 V
Data Sheet
ADG5433W
CONTINUOUS CURRENT PER CHANNEL, Sx OR Dx
Table 5.
Parameter
CONTINUOUS CURRENT, Sx OR Dx
VDD = +15 V, VSS = −15 V
VDD = +20 V, VSS = −20 V
VDD = 12 V, VSS = 0 V
VDD = 36 V, VSS = 0 V
25°C
85°C
125°C
Unit
80
85
63
83
58
63
45
60
36
39
28
37
mA maximum
mA maximum
mA maximum
mA maximum
Rev. A | Page 7 of 20
ADG5433W
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter
VDD to VSS
VDD to GND
VSS to GND
Analog Inputs1
Digital Inputs1
Peak Current, Sx or Dx Pins
Continuous Current, Sx or Dx2
Temperature Range
Operating
Storage
Junction Temperature
Thermal Impedance, θJA
16-Lead TSSOP (4-Layer Board)
Reflow Soldering Peak
Temperature, Pb Free
Rating
48 V
−0.3 V to +48 V
+0.3 V to −48 V
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs
first
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs
first
280 mA (pulsed at 1 ms,
10% duty cycle maximum)
Data + 15%
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Only one absolute maximum rating can be applied at any
one time.
ESD CAUTION
−40°C to +125°C
−65°C to +150°C
150°C
112.6°C/W
As per JEDEC J-STD-020
Overvoltages at the INx, Sx, and Dx pins are clamped by internal diodes.
Limit current to the maximum ratings given.
2
See Table 5.
1
Rev. A | Page 8 of 20
Data Sheet
ADG5433W
VDD 1
16 GND
S1A 2
15
IN1
D1 3
14
EN
S1B 4
ADG5433W
13
VSS
S2B 5
TOP VIEW
(Not to Scale)
12
S3B
D2 6
11
D3
S2A 7
10
S3A
IN2 8
9
IN3
10656-003
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Mnemonic
VDD
S1A
D1
S1B
S2B
D2
S2A
IN2
IN3
S3A
D3
S3B
VSS
EN
15
16
IN1
GND
Description
Most Positive Power Supply Potential.
Source Terminal 1A. This pin can be an input or an output.
Drain Terminal 1. This pin can be an input or an output.
Source Terminal 1B. This pin can be an input or an output.
Source Terminal 2B. This pin can be an input or an output.
Drain Terminal 2. This pin can be an input or an output.
Source Terminal 2A. This pin can be an input or an output.
Logic Control Input 2.
Logic Control Input 3.
Source Terminal 3A. This pin can be an input or an output.
Drain Terminal 3. This pin can be an input or an output.
Source Terminal 3B. This pin can be an input or an output.
Most Negative Power Supply Potential. In single-supply applications, this pin must be connected to ground.
Active Low Digital Input. When high, the device is disabled and all switches are off. When low, the INx logic
inputs determine the on switches.
Logic Control Input 1.
Ground (0 V) Reference.
Table 8. Truth Table
EN
1
0
0
1
INx
X1
0
1
SxA
Off
Off
On
SxB
Off
On
Off
X = don’t care.
Rev. 0 | Page 9 of 20
ADG5433W
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
16
25
TA = 25°C
TA = 25°C
VDD = +10V
VSS = –10V
VDD = +9V
VSS = –9V
14
20
ON RESISTANCE (Ω)
ON RESISTANCE (Ω)
12
VDD = +11V
VSS = –11V
15
10
VDD = +13.5V
VSS = –13.5V
VDD = +15V
VSS = –15V
VDD = +16.5V
VSS = –16.5V
10
VDD = 32.4V
VSS = 0V
8
VDD = 39.6V
VSS = 0V
VDD = 36V
VSS = 0V
6
4
5
–14
–10
–6
–2
2
6
10
14
18
VS, VD (V)
0
10656-047
0
–18
0
5
10
15
30
25
20
35
40
45
VS, VD (V)
Figure 3. On Resistance as a Function of VS, VD (Dual Supply)
Figure 6. On Resistance as a Function of VS, VD (Single Supply)
16
25
10656-046
2
TA = 25°C
14
ON RESISTANCE (Ω)
ON RESISTANCE (Ω)
20
VDD = +18V
VSS = –18V
12
10
8
VDD = +22V
VSS = –22V
VDD = +20V
VSS = –20V
6
TA = +125°C
15
TA = +85°C
TA = +25°C
10
TA = –40°C
4
–20
–15
–10
–5
0
5
10
15
20
25
VS, VD (V)
VDD = 10V
VSS = 0V
30
VDD = 10.8V
VSS = 0V
5
10
15
VDD = +20V
VSS = –20V
20
ON RESISTANCE (Ω)
25
20
15
VDD = 13.2V
VSS = 0V
VDD = 12V
VSS = 0V
VDD = 11V
VSS = 0V
10
TA = +125°C
15
TA = +85°C
TA = +25°C
10
TA = –40°C
5
0
0
2
4
6
8
VS, VD (V)
10
12
14
Figure 5. On Resistance as a Function of VS, VD (Single Supply)
0
–20
–15
–10
–5
0
VS, VD (V)
5
10
15
20
10656-045
5
10656-044
ON RESISTANCE (Ω)
VDD = 9V
VSS = 0V
0
VS, VD (V)
25
TA = 25°C
–5
Figure 7. On Resistance as a Function of VS (VD) for Different Temperatures,
±15 V Dual Supply
Figure 4. On Resistance as a Function of VS, VD (Dual Supply)
35
VDD = +15V
VSS = –15V
0
–15
–10
10656-048
0
–25
10656-049
5
2
Figure 8. On Resistance as a Function of VS (VD) for Different Temperatures,
±20 V Dual Supply
Rev. A | Page 10 of 20
Data Sheet
ADG5433W
0.4
VDD = +20V
VSS = –20V
VBIAS = +15V/–15V
35
LEAKAGE CURRENT (nA)
TA = +25°C
15
TA = –40°C
10
0
ID, IS (ON) – –
–0.2
IS (OFF) – +
–0.4
5
0
2
4
6
8
10
12
VS, VD (V)
–0.6
10656-050
0
VDD = 12V
VSS = 0V
0.4
VDD = 36V
VSS = 0V
LEAKAGE CURRENT (nA)
ON RESISTANCE (Ω)
15
TA = +85°C
TA = +25°C
10
TA = –40°C
5
5
10
15
20
25
30
35
40
ID, IS (ON) – –
IS (OFF) + –
0.1
0
ID (OFF) – +
IS (OFF) – +
ID (OFF) + –
0
0.4
LEAKAGE CURRENT (nA)
IS (OFF) + –
ID (OFF) – +
ID, IS (ON) – –
0
IS (OFF) – +
–0.2
50
75
100
VDD = 36V
VSS = 0V
VBIAS = 1V/30V
IS (OFF) + –
0
ID (OFF) – +
ID, IS (ON) – –
–0.2
IS (OFF) – +
–0.4
ID (OFF) + –
0
25
50
75
TEMPERATURE (°C)
100
125
10656-041
ID (OFF) + –
–0.4
125
ID, IS (ON) + +
0.2
ID, IS (ON) + +
0.2
25
Figure 13. Leakage Currents as a Function of Temperature,
12 V Single Supply
VDD = +15V
VSS = –15V
VBIAS = +10V/–10V
0.4
125
TEMPERATURE (°C)
Figure 10. On Resistance as a Function of VS (VD) for Different Temperatures,
36 V Single Supply
0.6
100
ID, IS (ON) + +
–0.2
10656-051
0
75
0.2
–0.1
VS, VD (V)
LEAKAGE CURRENT (nA)
50
VDD = 12V
VSS = 0V
VBIAS = 1V/10V
0.3
TA = +125°C
25
Figure 12. Leakage Currents as a Function of Temperature,
±20 V Dual Supply
20
0
0
TEMPERATURE (°C)
Figure 9. On Resistance as a Function of VS (VD) for Different Temperatures,
12 V Single Supply
25
ID (OFF) + –
10656-040
20
ID (OFF) – +
Figure 11. Leakage Currents as a Function of Temperature, ±15 V Dual Supply
Rev. A | Page 11 of 20
–0.6
0
25
50
75
100
125
TEMPERATURE (°C)
Figure 14. Leakage Currents as a Function of Temperature,
36 V Single Supply
10656-043
ON RESISTANCE (Ω)
TA = +85°C
25
IS (OFF) + –
0.2
TA = +125°C
30
ID, IS (ON) + +
10656-042
40
ADG5433W
TA = 25°C
VDD = +15V
VSS = –15V
–10
–20
–30
–30
ACPSRR (dB)
–20
–40
–50
–60
NO DECOUPLING CAPACITORS
–40
–50
–60
DECOUPLING CAPACITORS
–70
–70
–80
–80
–90
–90
–100
1k
–100
1k
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
10656-036
OFF ISOLATION (dB)
–10
0
TA = 25°C
VDD = +15V
VSS = –15V
1M
100k
10M
FREQUENCY (Hz)
Figure 15. Off Isolation vs. Frequency
Figure 18. ACPSRR vs. Frequency
0.12
0
TA = 25°C
–10 VDD = +15V
VSS = –15V
VDD = 12V, V SS = 0V, V S = 6V p-p
0.10
–20
–30
LOAD = 1kΩ
TA = 25°C
0.08
THD + N (%)
CROSSTALK (dB)
10k
10656-037
0
Data Sheet
–40
–50
–60
0.06
VDD = 36V, V SS = 0V, V S = 18V p-p
0.04
–70
–80
VDD = 15V, V SS = 15V, V S = 15V p-p
0.02
–90
1M
10M
100M
1G
FREQUENCY (Hz)
0
10656-039
100k
0
10k
20k
15k
FREQUENCY (Hz)
Figure 16. Crosstalk vs. Frequency
350
5k
10656-038
VDD = 20V, V SS = 20V, V S = 20V p-p
–100
10k
Figure 19. THD + N vs. Frequency
0
TA = 25°C
TA = 25°C
VDD = +15V
VSS = –15V
–0.5
300
200
INSERTION LOSS (dB)
VDD = +15V
VSS = –15V
VDD = +20V
VSS = –20V
VDD = +36V
VSS = 0V
150
100
VDD = +12V
VSS = 0V
50
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
0
–20
10
0
10
20
30
VS (V)
40
–5.0
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 20. Bandwidth
Figure 17. Charge Injection vs. Source Voltage
Rev. A | Page 12 of 20
100M
1G
10656-035
–4.5
10656-033
CHARGE INJECTION (pC)
–1.0
250
Data Sheet
ADG5433W
350
300
VDD = +12V, V SS = 0V
VDD = +36V, V SS = 0V
200
150
VDD = +15V, V SS = –15V
100
VDD = +20V, V SS = –20V
50
0
–40
–20
0
20
40
60
80
100
TEMPERATURE (°C)
120
10656-034
TIME (ns)
250
Figure 21. tTRANSITION Times vs. Temperature
Rev. A | Page 13 of 20
ADG5433W
Data Sheet
TEST CIRCUITS
VDD
VSS
0.1µF
0.1µF
VDD
S1
NC
D
A
S2
NC
SxB
SxA
INx
NETWORK
ANALYZER
VSS
50Ω
50Ω
VS
Dx
ID (ON)
VIN
A
RL
50Ω
GND
VOUT
VD
10656-100
VS
OFF ISOLATION = 20 log
Figure 22. On and Off Leakage
10656-028
IS (OFF)
VOUT
VS
Figure 25. Off Isolation
VDD
VSS
0.1µF
0.1µF
AUDIO PRECISION
VDD
VS
V p-p
INx
Dx
D
VIN
IDS
10656-031
Figure 26. THD + Noise
Figure 23. On Resistance
VDD
VSS
0.1µF
0.1µF
VDD
VSS
0.1µF
0.1µF
NETWORK
ANALYZER
VDD
SxA
VSS
VDD
RL
50Ω
NETWORK
ANALYZER
VSS
NC
Dx
SxB
VS
VOUT
10656-021
RON = V/IDS
RL
1kΩ
GND
R
50Ω
INx
SxA
SxB
50Ω
50Ω
VS
INx
Dx
GND
VIN
RL
50Ω
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
VOUT
VS
10656-030
GND
Figure 24. Channel-to-Channel Crosstalk
INSERTION LOSS = 20 log
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
Figure 27. Bandwidth
Rev. A | Page 14 of 20
VOUT
10656-029
S
VOUT
RS
Sx
V
VS
VSS
Data Sheet
ADG5433W
VDD
VSS
VIN
50%
50%
VIN
50%
50%
VSS
VDD
SxB
VS
0.1µF
Dx
SxA
VOUT
RL
300Ω
INx
CL
35pF
90%
90%
VOUT
GND
VIN
tON
tOFF
10656-024
0.1µF
Figure 28. Switching Timing
0.1µF
VDD
VSS
VDD
VSS
SxB
VS
0.1µF
VIN
Dx
SxA
VOUT
RL
300Ω
INx
VOUT 80%
CL
35pF
tD
tD
10656-025
GND
VIN
Figure 29. Break-Before-Make Delay, tD
VSS
VDD
VSS
0.1µF
3V
ENABLE
DRIVE (VIN)
ADG5433W
IN1
S1A
IN2
S1B
VS
0V
VOUT
D1
RL
300Ω
GND
50Ω
VIN
tOFF (EN)
VOUT
IN3
EN
50%
50%
CL
35pF
0.9VOUT
OUTPUT
0V
0.9VOUT
10656-026
0.1µF
VDD
tON (EN)
Figure 30. Enable Delay, tON (EN), tOFF (EN)
VS
VDD
VSS
VDD
VSS
VIN (NORMALLY
CLOSED SWITCH)
SxB
Dx
NC
SxA
CL
1nF
INx
VIN
0.1µF
GND
VOUT
ON
OFF
VIN (NORMALLY
OPEN SWITCH)
VOUT
∆VOUT
Figure 31. Charge Injection
Rev. A | Page 15 of 20
QINJ = CL × ∆VOUT
10656-027
0.1µF
ADG5433W
Data Sheet
TERMINOLOGY
IDD
IDD represents the positive supply current.
CIN
CIN represents digital input capacitance.
ISS
ISS represents the negative supply current.
tON (EN)
tON (EN) represents the delay time between the 50% and 90%
points of the digital input and switch on condition.
VD, VS
VD and VS represent the analog voltage on Terminal D and
Terminal S, respectively.
tOFF (EN)
tOFF (EN) represents the delay time between the 50% and 90%
points of the digital input and switch off condition.
RON
RON is the ohmic resistance between Terminal D and
Terminal S.
tTRANSITION
Delay time between the 50% and 90% points of the digital
inputs and the switch on condition when switching from one
address state to another.
∆RON
∆RON represents the difference between the RON of any two
channels.
RFLAT (ON)
The difference between the maximum and minimum value of
on resistance as measured over the specified analog signal range
is represented by RFLAT (ON).
IS (Off)
IS (Off) is the source leakage current with the switch off.
tD
tD represents the off time measured between the 80% point of
both switches when switching from one address state to another.
Off Isolation
Off isolation is a measure of unwanted signal coupling through
an off channel.
Charge Injection
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.
ID (Off)
ID (Off) is the drain leakage current with the switch off.
ID (On), IS (On)
ID (On) and IS (On) represent the channel leakage currents with
the switch on.
VINL
VINL is the maximum input voltage for Logic 0.
Crosstalk
Crosstalk is a measure of unwanted signal that is coupled
through from one channel to another as a result of parasitic
capacitance.
Bandwidth
Bandwidth is the frequency at which the output is attenuated
by 3 dB.
VINH
VINH is the minimum input voltage for Logic 1.
On Response
On response is the frequency response of the on switch.
IINL, IINH
IINL and IINH represent the low and high input currents of the
digital inputs.
CD (Off)
CD (Off) represents the off switch drain capacitance, which is
measured with reference to ground.
CS (Off)
CS (Off) represents the off switch source capacitance, which is
measured with reference to ground.
CD (On), CS (On)
CD (On) and CS (On) represent on switch capacitances, which
are measured with reference to ground.
Total Harmonic Distortion + Noise (THD + N)
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental is represented by THD + N.
AC Power Supply Rejection Ratio (ACPSRR)
ACPSRR is a measure of the ability of a part to avoid coupling
noise and spurious signals that appear on the supply voltage pin
to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p. The ratio of the amplitude
of signal on the output to the amplitude of the modulation is
the ACPSRR.
Rev. A | Page 16 of 20
Data Sheet
ADG5433W
TRENCH ISOLATION
In the ADG5433W, an insulating oxide layer (trench) is placed
between the NMOS and the PMOS transistors of each CMOS
switch. Parasitic junctions, which occur between the transistors
in junction isolated switches, are eliminated, and the result is a
completely latch-up proof switch.
PMOS
P-WELL
N-WELL
TRENCH
BURIED OXIDE LAYER
HANDLE WAFER
Figure 32. Trench Isolation
Rev. A | Page 17 of 20
10656-032
In junction isolation, the N and P wells of the PMOS and NMOS
transistors form a diode that is reverse-biased under normal
operation. However, during overvoltage conditions, this diode
can become forward-biased. A silicon controlled rectifier (SCR)
type circuit is formed by the two transistors causing a significant amplification of the current that, in turn, leads to latch-up.
With trench isolation, this diode is removed, and the result is a
latch-up proof switch.
NMOS
ADG5433W
Data Sheet
APPLICATIONS INFORMATION
The ADG54xx family of switches and multiplexers provide a
robust solution for instrumentation, industrial, automotive, aerospace and other harsh environments that are prone to latch-up,
which is an undesirable high current state that can lead to device
failure and persists until the power supply is turned off. The
ADG5433W high voltage switch allows single-supply operation
from 9 V to 40 V and dual supply operation from ±9 V to ±22 V.
The ADG5433W (as well as other select devices within this family)
achieves 8 kV human body model ESD ratings, which provide a
robust solution eliminating the need for separate protect circuitry
designs in some applications.
Rev. A | Page 18 of 20
Data Sheet
ADG5433W
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.30
0.19
0.65
BSC
COPLANARITY
0.10
SEATING
PLANE
8°
0°
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 33. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1, 2
ADG5433WBRUZ
ADG5433WBRUZ-REEL7
1
2
Temperature Range
−40°C to +125°C
−40°C to +125°C
Description
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
Package Option
RU-16
RU-16
Z = RoHS Compliant Part.
W = Qualified for Automotive Applications.
AUTOMOTIVE PRODUCTS
The ADG5433W models are available with controlled manufacturing to support the quality and reliability requirements of automotive
applications. Note that these automotive models may have specifications that differ from the commercial models; therefore, designers
should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for use in
automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to
obtain the specific Automotive Reliability reports for these models.
Rev. A | Page 19 of 20
ADG5433W
Data Sheet
NOTES
©2012–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10656-0-4/13(A)
Rev. A | Page 20 of 20