a
LC2MOS Latchable 4-/8-Channel
High Performance Analog Multiplexers
ADG428/ADG429
FEATURES
44 V Supply Maximum Ratings
V SS to VDD Analog Signal Range
Low On Resistance (60 ⍀ typ)
Low Power Consumption (1.6 mW max)
Low Charge Injection (<4 pC typ)
Fast Switching
Break-Before-Make Switching Action
Plug-In Replacement for DG428/DG429
APPLICATIONS
Automatic Test Equipment
Data Acquisition Systems
Communication Systems
Avionics and Military Systems
Microprocessor Controlled Analog Systems
Medical Instrumentation
FUNCTIONAL BLOCK DIAGRAMS
ADG428
ADG429
S1A
S1
DA
S4A
D
S1B
DB
S4B
S8
DECODERS/DRIVERS
DECODERS/DRIVERS
LATCHES
LATCHES
WR
RS
A2
A1
A0
WR
EN
RS
A1
A0
EN
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG428 and ADG429 are monolithic CMOS analog
multiplexers comprising eight single channels and four differential channels respectively. On-chip address and control latches
facilitate microprocessor interfacing. The ADG428 switches one
of eight inputs to a common output as determined by the 3-bit
binary address lines A0, A1 and A2. The ADG429 switches one
of four differential inputs to a common differential output as
determined by the 2-bit binary address lines A0 and A1. An EN
input on both devices is used to enable or disable the device.
When disabled, all channels are switched OFF. All the control
inputs, address and enable inputs are TTL compatible over the
full specified operating temperature range. This makes the part
suitable for bus-controlled systems such as data acquisition systems, process controls, avionics and ATEs because the TTLcompatible address latches simplify the digital interface design
and reduce the board space required.
1. Extended Signal Range
The ADG428/ADG429 are fabricated on an enhanced
LC2MOS process, giving an increased signal range that extends to the supply rails.
2. Low Power Dissipation
3. Low RON
4. Single/Dual Supply Operation
5. Single Supply Operation
For applications where the analog signal is unipolar, the
ADG428/ADG429 can be operated from a single rail power
supply. The parts are fully specified with a single +12 V
power supply and will remain functional with single supplies
as low as +5 V.
The ADG428/ADG429 are designed on an enhanced LC2MOS
process that provides low power dissipation yet gives high switching
speed and low on resistance. Each channel conducts equally well
in both directions when ON and has an input signal range that
extends to the supplies. In the OFF condition, signal levels up to
the supplies are blocked. All channels exhibit break-before-make
switching action, preventing momentary shorting when switching
channels. Inherent in the design is low charge injection for minimum transients when switching the digital inputs.
The ADG428/ADG429 are improved replacements for the
DG428/DG429 Analog Multiplexers.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
ADG428/ADG429–SPECIFICATIONS
DUAL SUPPLY1 (V
DD
= +15 V, VSS = –15 V, GND = 0 V, WR = 0 V, RS = 2.4 V unless otherwise noted)
Parameter
ANALOG SWITCH
Analog Signal Range
RON
∆RON
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF)
Drain OFF Leakage ID (OFF)
ADG428
ADG429
Channel ON Leakage ID, IS (ON)
ADG428
ADG429
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IINL or I INH
CIN, Digital Input Capacitance
B Version
–40ⴗC to
+25ⴗC +85ⴗC
VSS to VDD
60
100
10
tW, Write Pulsewidth
tS, Address, Enable Setup Time
tH, Address, Enable Hold Time
tRS, Reset Pulsewidth
Charge Injection
OFF Isolation
Channel-to-Channel Crosstalk
CS (OFF)
CD (OFF)
ADG428
ADG429
CD, CS (ON)
ADG428
ADG429
POWER REQUIREMENTS
IDD
ISS
125
V
Ω typ
Ω max
% max
Test Conditions/Comments
VD = ± 10 V, IS = –1 mA
–10 V < VS < 10 V, IS = –1 mA
± 0.03 ± 0.3
± 0.5 ± 50
nA typ
nA max
± 0.07
±1
± 0.05
±1
± 0.7
± 100
± 0.5
± 50
± 0.07
±1
± 0.05
±1
± 0.7
± 100
± 0.5
± 50
nA typ
nA max
nA typ
nA max
±1
±1
± 100
± 50
±1
±1
± 100
± 50
nA max
nA max
2.4
0.8
V min
V max
±1
µA max
pF typ
VIN = 0 or VDD
f = 1 MHz
300
ns typ
ns max
10
ns min
RL = 1 MΩ, CL = 35 pF;
VS1 = ±10 V, VS8 = ⫿10 V;
Test Circuit 5
RL = 1 kΩ, CL = 35 pF;
VS = +5 V; Test Circuit 6
RL = 1 kΩ, CL = 35 pF;
VS = +5 V; Test Circuit 7
RL = 1 kΩ, CL = 35 pF;
VS = +5 V; Test Circuit 7
2.4
0.8
± 0.1
8
±1
300
± 0.1
8
110
250
10
tOPEN
tOFF (EN, RS)
125
VSS to VDD
60
100
10
Units
± 0.03 ± 0.3
± 0.5 ± 50
DYNAMIC CHARACTERISTICS2
tTRANSITION
110
250
tON (EN, WR)
T Version
–55ⴗC to
+25ⴗC +125ⴗC
115
150
105
150
4
4
ns typ
ns max
ns typ
ns max
ns min
ns min
ns min
ns min
pC typ
–75
–60
85
–75
–60
85
dB typ
dB min
dB typ
11
11
pF typ
40
20
40
20
pF typ
pF typ
54
34
54
34
pF typ
pF typ
20
100
0.001
5
20
100
0.001
5
µA typ
µA max
µA typ
µA max
225
300
100
100
10
100
115
150
105
150
225
300
100
100
10
100
VD = ± 10 V, VS = ⫿10 V;
Test Circuit 2
VD = ± 10 V, VS = ⫿10 V;
Test Circuit 3
VS = VD = ± 10 V;
Test Circuit 4
VS = +5 V
VS = 0 V, RS = 0 Ω, CL = 10 nF;
Test Circuit 10
RL = 1 kΩ, CL = 15 pF, f = 100 kHz;
VS = 7 V rms, VEN = 0 V; Test Circuit 11
RL = 1 kΩ, CL = 15 pF, f = 100 kHz;
Test Circuit 12
f = 1 MHz
f = 1 MHz
f = 1 MHz
VIN = 0 V, VEN = 0 V
NOTES
1
Temperature ranges are as follows: B Version: –40°C to +85°C; T Version: –55°C to +125°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2–
REV. C
ADG428/ADG429
SINGLE
SUPPLY1 (VDD = +12 V, VSS = 0 V, GND = 0 V, WR = 0 V, RS = 2.4 V unless otherwise noted)
Parameter
B Version
–40ⴗC to
+25ⴗC +85ⴗC
ANALOG SWITCH
Analog Signal Range
RON
90
∆RON
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF)
Drain OFF Leakage ID (OFF)
ADG428
ADG429
Channel ON Leakage ID, IS (ON)
ADG428
ADG429
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IINL or I INH
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS2
tTRANSITION
T Version
–55ⴗC to
+25ⴗC +125ⴗC
0 to VDD
0 to VDD
90
200
200
10
10
± 0.005
± 0.5
± 50
± 0.005
± 0.5
± 0.015
±1
± 100
± 0.008
±1
± 50
± 0.015
±1
± 0.008
±1
± 0.02
±1
± 0.01
±1
± 0.02
±1
± 0.01
±1
± 100
± 50
2.4
0.8
±1
8
± 50
± 100
± 50
Units
V
Ω typ
Ω max
% max
nA typ
nA max
nA typ
nA max
nA typ
nA max
±1
µA max
pF typ
VIN = 0 or VDD
f = 1 MHz
RL = 1 MΩ, CL = 35 pF;
VS1 = 10 V/0 V, V S8 = 0 V/10 V;
Test Circuit 5
RL = 1 kΩ, CL = 35 pF;
VS = +5 V; Test Circuit 6
RL = 1 kΩ, CL = 35 pF;
VS = +5 V; Test Circuit 7
RL = 1 kΩ, CL = 35 pF;
VS = +5 V; Test Circuit 7
450
ns typ
ns max
tOPEN
25
10
25
10
ns min
tON (EN, WR)
200
300
80
300
OFF Isolation
Channel-to-Channel Crosstalk
CS (OFF)
CD (OFF)
ADG428
ADG429
CD, CS (ON)
ADG428
ADG429
POWER REQUIREMENTS
IDD
4
4
ns typ
ns max
ns typ
ns max
ns min
ns min
ns min
ns min
pC typ
–75
–60
85
–75
–60
85
dB typ
dB min
dB typ
11
11
pF typ
40
20
40
20
pF typ
pF typ
54
34
54
34
pF typ
pF typ
20
100
20
100
µA typ
µA max
400
100
100
10
100
400
400
100
100
10
100
VS = +5 V
VS = 6 V, RS = 0 Ω, CL = 10 nF;
Test Circuit 10
RL = 1 kΩ, CL = 15 pF, f = 100 kHz;
VS = 7 V rms, VEN = 0 V; Test Circuit 11
RL = 1 kΩ, CL = 15 pF, f = 100 kHz;
Test Circuit 12
f = 1 MHz
f = 1 MHz
f = 1 MHz
NOTES
1
Temperature ranges are as follows: B Version: –40°C to +85°C; T Version: –55°C to +125°C.
2
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV. C
VS = VD = 10 V/0 V;
Test Circuit 4
V min
V max
250
350
tW, Write Pulsewidth
tS, Address, Enable Setup Time
tH, Address, Enable Hold Time
tRS, Reset Pulsewidth
Charge Injection
VD = 10 V/0 V, VS = 0 V/10 V;
Test Circuit 2
VD = 10 V/0 V, VS = 0 V/10 V;
Test Circuit 3
2.4
0.8
450
tOFF (EN, RS)
0 V < VS < 10 V, IS = –1 mA
± 50
± 100
250
350
200
300
80
300
VD = +10 V, IS = –500 µA
nA typ
nA max
nA max
nA max
8
400
Test Conditions/Comments
–3–
VIN = 0 V, VEN = 0 V
ADG428/ADG429
ABSOLUTE MAXIMUM RATINGS 1
ADG428 PIN CONFIGURATIONS
A0
2
EN 3
VSS
4
16
ADG428
15
A2
GND
S1 5
TOP VIEW 14 VDD
(Not to Scale)
13 S5
6
S2
3
2
1
EN 4
A1
A1
NC
RS
17
WR
18
A0
WR 1
PLCC
20
19
PIN 1
IDENTIFIER
VSS 5
ADG428
S1 6
TOP VIEW
(Not to Scale)
S2 7
11
S7
D 9
10
S8
9
10
11
12
13
S7
S4 8
S8
S6
NC
12
D
S3 7
S4
S3 8
18
A2
17
GND
16
VDD
15
S5
14
S6
NC = NO CONNECT
ADG429 PIN CONFIGURATIONS
A1
EN 3
16
GND
VSS 4
ADG429
15
VDD
S1A 5
TOP VIEW 14 S1B
(Not to Scale)
13 S2B
S2A 6
A1
RS
17
RS
18
A0 2
NC
WR 1
WR
PLCC
A0
DIP
3
2
1
20
19
EN 4
PIN 1
IDENTIFIER
VSS 5
ADG429
S1A 6
TOP VIEW
(Not to Scale)
S2A 7
S4A 8
11
S4B
DA 9
10
DB
9
10
11
12
13
S4B
S3B
DB
12
NC
S3A 8
S3A 7
DA
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
2
Overvoltages at A, EN, WR, RS, S or D will be clamped by internal diodes. Current
should be limited to the maximum ratings given.
DIP/SOIC
S4A
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+44 V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +25 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –25 V
Analog, Digital Inputs2 . . . . . . . . . . VSS – 2 V to V DD + 2 V or
30 mA, Whichever Occurs First
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
(Pulsed at 1 ms, 10% Duty Cycle Max)
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
Extended (T Version) . . . . . . . . . . . . . . . . –55°C to +125°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . +150°C
Cerdip Package, Power Dissipation . . . . . . . . . . . . . . . 900 mW
θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 73°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +300°C
Plastic Package, Power Dissipation . . . . . . . . . . . . . . . 470 mW
θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 115°C/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . +260°C
SOIC Package, Power Dissipation . . . . . . . . . . . . . . . . 600 mW
θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 77°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
PLCC Package, Power Dissipation . . . . . . . . . . . . . . . 800 mW
θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 90°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
RS
(TA = +25°C unless otherwise noted.)
18
GND
17
VDD
16
S1B
15
S2B
14
S3B
NC = NO CONNECT
ORDERING GUIDE
Model1
Temperature Range
Package Options2
ADG428BN
ADG428BP
ADG428BR
ADG428TQ
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
N-18
P-20A
R-18
Q-18
ADG429BN
ADG429BP
ADG429TQ
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
N-18
P-20A
Q-18
NOTES
1
For availability of MIL-STD-883, Class B processed parts, contact factory.
2
N = Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC); Q = Cerdip;
R = Small Outline IC (SOIC).
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG428/ADG429 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.
–4–
WARNING!
ESD SENSITIVE DEVICE
REV. C
ADG428/ADG429
TERMINOLOGY
VDD
Most positive power supply potential.
VSS
Most negative power supply potential in dual
supplies. In single supply applications, it may
be connected to ground.
ADG428 Truth Table
A2
A0
EN
WR
RS
ON SWITCH
X
X
X
g
1
Maintains Previous
Switch Condition
X
X
X
X
0
NONE
(Latches Cleared)
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
NONE
1
2
3
4
5
6
7
8
A1
Latching
X
GND
Ground (0 V) reference.
RON
Ohmic resistance between D and S.
Reset
∆RON
Difference between the RON of any two
channels.
X
IS (OFF)
Source leakage current when the switch is off.
Transparent Operation
X
0
0
0
0
1
1
1
1
ID (OFF)
Drain leakage current when the switch is off.
ID, IS (ON)
Channel leakage current when the switch is
on.
VD (VS )
Analog voltage on terminals D, S.
CS (OFF)
Channel input capacitance for “OFF”
condition.
CD (OFF)
Channel output capacitance for “OFF”
condition.
CD, CS (ON)
“ON” switch capacitance.
CIN
Digital input capacitance.
tON (EN)
Delay time between the 50% and 90% points
of the digital input and switch “ON”
condition.
tOFF (EN)
tTRANSITlON
A1
X
tOPEN
“OFF” time measured between 80% points of
both switches when switching from one
address state to another.
VINL
Maximum input voltage for Logic “0.”
X
0
0
1
1
VINH
Minimum input voltage for Logic “1.”
Input current of the digital input.
Off Isolation
A measure of unwanted signal coupling
through an “OFF” channel.
Charge
Injection
A measure of the glitch impulse transferred
from the digital input to the analog output
during switching.
IDD
Positive supply current.
ISS
Negative supply current.
REV. C
EN
WR
RS
ON SWITCH PAIR
X
X
g
1
Maintains Previous
Switch Condition
X
X
X
0
NONE
(Latches Cleared)
0
0
0
0
0
1
1
1
1
1
NONE
1
2
3
4
A0
Reset
X
A measure of unwanted signal which is
coupled through from one channel to another
as a result of parasitic capacitance.
0
1
1
1
1
1
1
1
1
Latching
Delay time between the 50% and 90% points
of the digital inputs and the switch “ON”
condition when switching from one address
state to another.
Crosstalk
X
0
1
0
1
0
1
0
1
ADG429 Truth Table
Delay time between the 50% and 90% points
of the digital input and switch “OFF”
condition.
IINL (IINH)
X
0
0
1
1
0
0
1
1
Transparent Operation
–5–
X
0
1
0
1
0
1
1
1
1
ADG428/ADG429
TIMING DIAGRAMS
3V
3V
WR
50%
50%
RS
50%
50%
0V
0V
tRS
tW
tS
tOFF (RS)
tH
VO
3V
2V
A0, A1, (A2)
EN
0.8VO
SWITCH
OUTPUT
0.8V
0V
0V
Figure 1.
Figure 2.
Figure 1 shows the timing sequence for latching the switch
address and enable inputs. The latches are level sensitive; therefore, while WR is held low, the latches are transparent and the
switches respond to the address and enable inputs. This input
data is latched on the rising edge of WR.
Figure 2 shows the Reset Pulsewidth, tRS, and the Reset Turnoff
Time, tOFF, (RS).
Note: All digital input signals rise and fall times are measured
from 10% to 90% of 3 V. tr = tf = 20 ns.
Typical Characteristics
140
600
TA = +258C
500
120
RON – V
RON – V
400
100
90
80
VDD = +15V
70 VSS = –15V
VDD = +12V
VSS = –12V
VDD = +5V
VSS = 0V
450
VDD = +5V
VSS = –5V
110
350
300
VDD = +10V
VSS = 0V
VDD = +15V
VSS = 0V
250
200
VDD = +10V
VSS = –10V
VDD = +12V
VSS = 0V
150
60
100
50
40
–15
TA = +258C
550
130
50
–10
–5
0
VD (VS) – Volts
5
10
0
15
0
3
6
9
12
15
VD (VS) – Volts
Figure 3. RON as a Function of VD (VS ): Dual Supply
Voltage
Figure 5. R ON as a Function of VD (V S): Single Supply
Voltage
80
160
VDD = +15V
VSS = –15V
75
VDD = +12V
VSS = 0V
150
140
70
130
RON – V
RON – V
65
60
55
120
+1258C
110
+1258C
100
+858C
90
+858C
50
+258C
80
+258C
45
40
–15
70
–10
–5
0
VD (VS) – Volts
5
10
60
15
0
Figure 4. RON as a Function of VD (VS ) for Different
Temperatures
2
4
6
VD (VS) – Volts
8
10
15
Figure 6. R ON as a Function of VD (V S) for Different
Temperatures
–6–
REV. C
ADG428/ADG429
6000
1000
VDD = +15V
VSS = –15V
5500
VDD = +15V
VSS = –15V
5000
4500
100
3500
ISS – mA
IDD – mA
4000
3000
2500
10
EN = 2.4V
2000
EN = 0V
1500
1
EN = 2.4V
1000
EN = 0V
500
0
10
100
1k
10k
100k
SWITCHING FREQUENCY – Hz
1M
0.1
10
10M
Figure 7. Positive Supply Current vs. Switching Frequency
10M
200
VDD = +15V
VSS = –15V
120
VDD = +12V
VSS = 0V
180
tTRANSITION
110
tTRANSITION
tON (EN)
160
tON (EN)
140
t – ns
100
t – ns
1M
Figure 10. Negative Supply Current vs. Switching
Frequency
130
90
120
80
100
70
80
tOFF (EN)
60
50
1k
10k
100k
SWITCHING FREQUENCY – Hz
100
1
3
5
tOFF (EN)
60
7
9
VIN – Volts
11
13
40
1
15
Figure 8. Switching Time vs. V IN (Bipolar Supply)
3
5
7
VIN – Volts
9
11
13
Figure 11. Switching Time vs. VIN (Single Supply)
500
300
VIN = +5V
VIN = +5V
275
450
250
400
225
350
200
300
t – ns
t – ns
175
tON (EN)
150
125
250
tON (EN)
200
tTRANSITION
100
150
tTRANSITION
tOFF (EN)
75
100
50
0
65
0
67
69
611
VSUPPLY – Volts
613
5
615
6
7
8
9
10
11
VSUPPLY – Volts
12
13
14
15
Figure 12. Switching Time vs. Single Supply
Figure 9. Switching Time vs. Bipolar Supply
REV. C
tOFF (EN)
50
25
–7–
ADG428/ADG429
100
110
VDD = +15V
VSS = –15V
VDD = +15V
VSS = –15V
105
90
100
85
95
CROSSTALK – dB
OFF ISOLATION – dB
95
80
75
70
65
60
55
90
85
80
75
70
65
50
60
45
55
40
100
1k
10k
100k
FREQUENCY – Hz
1M
50
1k
10M
Figure 13. OFF Isolation vs. Frequency
100k
FREQUENCY – Hz
1M
10M
Figure 15. Crosstalk vs. Frequency
0.04
0.2
VDD = +15V
VSS = –15V
TA = +258C
VDD = +12V
VSS = 0V
TA = +258C
0.03
LEAKAGE CURRENT – nA
LEAKAGE CURRENT – nA
10k
0.1
ID (ON)
IS (OFF)
0
ID (OFF)
ID (ON)
0.02
0.01
ID (OFF)
0
IS (OFF)
–0.01
–0.02
–0.03
–0.1
–15
–10
–5
0
VD (VS) – Volts
5
10
–0.04
15
0
Figure 14. Leakage Currents as a Function of VD (V S)
2
4
6
VD (VS) – Volts
8
10
12
Figure 16. Leakage Currents as a Function of VD (VS)
–8–
REV. C
ADG428/ADG429
TEST CIRCUITS
I DS
V1
VDD
VSS
VDD
VSS
S1
S2
S
D
S8
D
GND
VS
VS
EN
+0.8V
A
ID (OFF)
VD
RON = V1/I DS
Test Circuit 1. On Resistance
S1
Test Circuit 3. I D (OFF)
VDD
VSS
VDD
VSS
VDD
VSS
VDD
VSS
S1
IS (OFF)
S2
A
S8
VS
D
D
EN
GND
VD
S8
+0.8V
GND
VS
EN
ID (ON)
A
2.4V
VD
Test Circuit 4. I D (ON)
Test Circuit 2. IS (OFF)
VDD
VSS
VDD
VSS
3V
ENABLE
DRIVE – VIN
50%
50%
A0
VS1
S1
VIN
0V
50V
A1
S2–S7
A2
tTRANSITION
ADG428*
tTRANSITION
2.4V
90%
VS8
S8
EN
OUTPUT
D
RS
OUTPUT
GND
90%
WR
1MV
35pF
*SIMILAR CONNECTION FOR ADG429
Test Circuit 5. Switching Time of Multiplexer, tTRANSITION
3V
VDD
VSS
VDD
VSS
A0
ADDRESS
DRIVE – VIN
VS
S1
VIN
50V
0V
A1
S2–S7
A2
ADG428*
2.4V
S8
EN
OUTPUT
80%
D
RS
80%
OUTPUT
GND
WR
tOPEN
*SIMILAR CONNECTION FOR ADG429
Test Circuit 6. Break-Before-Make Delay, tOPEN
REV. C
–9–
1kV
35pF
ADG428/ADG429
VDD
VSS
VDD
VSS
3V
ENABLE DRIVE
–VIN
50%
A0
50%
S1
VS
A1
0V
S2–S8
A2
tON (EN)
ADG428*
tOFF (EN)
VO
0.9VO
RS
2.4V
OUTPUT
D
0.9VO
EN
OUTPUT (VO)
VIN
0V
1kV
50V
35pF
WR
GND
*SIMILAR CONNECTION FOR ADG429
Test Circuit 7. Enable Delay, t ON (EN), t OFF (EN)
VDD
VSS
VDD
VSS
3V
WR
50%
A0
S2–S8
A2
2.4V
tON (WR)
VO
VS
S1
A1
0V
ADG428*
EN
OUTPUT
RS
D
WR
OUTPUT
1kV
0.2VO
35pF
GND
VRS
0V
VWR
*SIMILAR CONNECTION FOR ADG429
Test Circuit 8. Write Turn-On Time, tON (WR)
3V
VDD
VSS
VDD
VSS
A0
RS
50%
S1
A1
0V
VS
S2–S8
A2
ADG428*
tOFF (RS)
2.4V
EN
OUTPUT
D
VO
RS
0.8VO
OUTPUT
1kV
GND
VIN
35pF
WR
0V
*SIMILAR CONNECTION FOR ADG429
Test Circuit 9. Reset Turn-Off Time, tOFF (RS )
–10–
REV. C
ADG428/ADG429
3V
VDD
VSS
VDD
VSS
A0
EN
RS
2.4V
A1
A2
S
DVOUT
VOUT
ADG428*
VS
D
RS
QINJ = CL 3 DVOUT
EN
VIN
VOUT
CL
10nF
GND
WR
*SIMILAR CONNECTION FOR ADG429
Test Circuit 10. Charge Injection
VDD
VSS
VDD
VSS
A0
RS
A1
A2
2.4V
ADG428
S1
0V
EN
WR
VSS
EN
A1
A2
RS
1kV
S2
VS
S8
2.4V
ADG428
D
VOUT
1kV
GND
WR
Test Circuit 12. Crosstalk
Test Circuit 11. OFF Isolation
REV. C
VDD
A0
VOUT
1kV
GND
VSS
S1
D
S8
VS
VDD
–11–
ADG428/ADG429
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
0.180 (4.57)
0.165 (4.19)
19
18
PIN 1
IDENTIFIER
4
TOP VIEW
(PINS DOWN)
8
0.020
(0.50)
R
1
0.060 (1.52)
0.015 (0.38)
0.840 (21.34) MAX
0.200 (5.08)
MAX
0.200 (5.08)
0.125 (3.18)
0.022 (0.58)
0.014 (0.36)
0.040 (1.01)
0.025 (0.64)
0.356 (9.04)
SQ
0.350 (8.89)
0.395 (10.02)
SQ
0.385 (9.78)
9
PIN 1
0.021 (0.53)
0.013 (0.33) 0.330 (8.38)
0.032 (0.81) 0.290 (7.37)
0.026 (0.66)
0.050
(1.27)
BSC
14
13
9
0.310 (7.87)
0.220 (5.59)
0.025 (0.63)
0.015 (0.38)
3
10
0.110 (2.79)
0.085 (2.16)
0.320 (8.13)
0.290 (7.37)
0.150
(3.81)
MIN
0.100
(2.54)
BSC
Plastic DIP (N-18)
0.015 (0.381)
0.008 (0.204)
0.070 (1.78) SEATING
0.030 (0.76) PLANE
SOIC (R-18)
0.910 (23.12)
0.890 (22.61)
0.4625 (11.75)
0.4469 (11.35)
10
1
9
0.260 (6.61)
0.240 (6.10)
PIN 1
0.180
(4.48)
MAX
0.175 (4.45)
0.120 (3.05)
0.020 (0.508) 0.105 (2.67) 0.065 (1.66) SEATING
PLANE
0.015 (0.381) 0.095 (2.42) 0.045 (1.15)
18
10
1
9
0.306 (7.78)
0.294 (7.47)
0.140 (3.56)
0.120 (3.05)
0.120 (0.305)
0.008 (0.203)
PIN 1
0.0118 (0.30)
0.0040 (0.10)
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
x 45°
0.0098 (0.25)
8°
0.0500 0.0192 (0.49)
0°
(1.27) 0.0138 (0.35) SEATING 0.0125 (0.32)
PLANE
BSC
0.0091 (0.23)
0.0500 (1.27)
0.0157 (0.40)
PRINTED IN U.S.A.
18
0.4193 (10.65)
0.3937 (10.00)
0.048 (1.21)
0.042 (1.07)
0.056 (1.42)
0.042 (1.07)
18
0.2992 (7.60)
0.2914 (7.40)
0.048 (1.21)
0.042 (1.07)
C1825c–0–5/99
Cerdip (Q-18)
PLCC (P-20A)
–12–
REV. C