Low Capacitance, Triple/Quad SPDT
±15 V/+12 V iCMOS Switches
ADG1233/ADG1234
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
1.5 pF off capacitance
0.5 pC charge injection
33 V supply range
120 Ω on resistance
Fully specified at ±15 V/+12 V
3 V logic-compatible inputs
Rail-to-rail operation
Break-before-make switching action
16-lead TSSOP, 20-lead TSSOP, and 4 mm × 4 mm LFCSP
Typical power consumption (<0.03 μW)
ADG1233
S1A
D1
S3B
S1B
D3
S3A
S2B
D2
S2A
APPLICATIONS
IN1 IN2 IN3 EN
SWITCHES SHOWN FOR A LOGIC 1 INPUT
Audio and video routing
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Communication systems
05743-001
LOGIC
Figure 1.
ADG1234
S1A
S4A
D1
D4
S1B
S4B
S2B
S3B
D2
D3
S2A
S3A
IN1 IN2 IN3 IN4 EN
SWITCHES SHOWN FOR A LOGIC 1 INPUT
05743-038
LOGIC
Figure 2.
GENERAL DESCRIPTION
The ADG1233 and ADG1234 are monolithic iCMOS® analog
switches comprising three independently selectable single-pole,
double throw SPDT switches and four independently selectable
SPDT switches, respectively.
Unlike analog ICs using conventional CMOS processes, iCMOS
components can tolerate high supply voltages while providing
increased performance, dramatically lowered power consumption,
and reduced package size.
All channels exhibit break-before-make switching action
preventing momentary shorting when switching channels. An
EN input on the ADG1233 and ADG1234 enables or disables
the device. When disabled, all channels are switched off.
The ultralow capacitance and charge injection of these multiplexers
make them ideal solutions for data acquisition and sample-andhold applications, where low glitch and fast settling are required.
The iCMOS (industrial-CMOS) modular manufacturing process
combines a high voltage complementary metal-oxide semiconductor (CMOS) and bipolar technologies. It enables the
development of a wide range of high performance analog ICs
capable of 33 V operation in a footprint that no other generation of
high voltage devices has been able to achieve.
Rev. C
Fast switching speed coupled with high signal bandwidth make the
devices suitable for video signal switching. iCMOS construction
ensures ultralow power dissipation, making the devices ideally
suited for portable and battery-powered instruments.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
1.5 pF off capacitance (±15 V supply).
0.5 pC charge injection.
3 V logic-compatible digital input, VIH = 2.0 V, VIL = 0.8 V.
16-lead TSSOP, 20-lead TSSOP, and 4 mm × 4 mm LFCSP.
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ADG1233/ADG1234
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ............................................................7
Applications ....................................................................................... 1
ESD Caution...................................................................................7
General Description ......................................................................... 1
Pin Configurations and Function Descriptions ............................8
Functional Block Diagrams ............................................................. 1
Terminology .................................................................................... 10
Product Highlights ........................................................................... 1
Typical Performance Characteristics ........................................... 11
Revision History ............................................................................... 2
Test Circuits..................................................................................... 14
Specifications..................................................................................... 3
Outline Dimensions ....................................................................... 16
Dual Supply ................................................................................... 3
Ordering Guide .......................................................................... 17
Single Supply ................................................................................. 5
REVISION HISTORY
3/16—Rev. B to Rev. C
Changes to Figure 5 and Figure 6 ................................................... 9
Updated Outline Dimensions ....................................................... 17
Changes to Ordering Guide .......................................................... 17
2/09—Rev. A to Rev. B
Change to IDD Parameter, Table 1 ................................................... 4
Change to IDD Parameter, Table 2 ................................................... 6
Updated Outline Dimensions ....................................................... 16
8/06—Rev. 0 to Rev. A
Updated Format ................................................................ 1Universal
Changes to Table 1.......................................................................... 13
Changes to Table 2.......................................................................... 14
Changes to Figure 11.................................................................... 110
Changes to Figure 12.................................................................... 111
1/06—Revision 0: Initial Version
Rev. C | Page 2 of 17
Data Sheet
ADG1233/ADG1234
SPECIFICATIONS
DUAL SUPPLY
VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
On Resistance Match Between
Channels (∆RON)
On Resistance Flatness (RFLAT (ON))
LEAKAGE CURRENTS
Source Off Leakage IS (Off )
Drain Off Leakage ID (Off )
Channel On Leakage ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
IINL or IINH
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 2
tTRANSITION
tBBM
+25°C
Y Version 1
−40°C to +85°C −40°C to +125°C
VSS to VDD
120
190
3.5
6
20
60
±0.02
±0.1
±0.02
±0.1
±0.02
±0.2
230
260
10
12
72
79
±0.6
±1
V
Ω typ
Ω max
Ω typ
VS = ±10 V, IS = −1 mA; see Figure 24
VDD = +13.5 V, VSS = −13.5 V
VS = ±10 V, IS = −1 mA
Ω max
Ω typ
Ω max
nA typ
nA max
nA typ
VS = 1 V/10 V, VD = 10 V/1 V;
see Figure 25
±0.6
±1
2.0
0.8
V min
V max
µA typ
µA max
pF typ
VIN = VINL or VINH
±0.1
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
pC typ
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 27
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = +10 V; see Figure 28
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 29
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 29
VS = 0 V, RS = 0 Ω, CL = 1 nF;
see Figure 30
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see
Figure 31
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 33
RL = 10 kΩ, 5 V rms, f = 20 Hz to
20 kHz; see Figure 34
RL = 50 Ω, CL = 5 pF; see Figure 32
f = 1 MHz; VS = 0 V
f = 1 MHz; VS = 0 V
f = 1 MHz; VS = 0 V
f = 1 MHz; VS = 0 V
3
150
170
Charge Injection
Off Isolation
−80
dB typ
Channel-to-Channel Crosstalk
−85
dB typ
Total Harmonic Distortion, THD + N
0.14
% typ
−3 dB Bandwidth
CS (Off )
900
1.5
1.7
1.6
1.8
MHz typ
pF typ
pF max
pF typ
pF max
CD (Off )
VDD = +16.5 V, VSS = −16.5 V
VD = ±10 V, VS = −10 V; see Figure 25
nA max
nA typ
nA max
120
140
40
45
0.5
tOFF (EN)
VS = −5 V, 0 V, +5 V; IS = −1 mA
±1
10
tON (EN)
Test Conditions/Comments
±0.6
±0.005
110
130
25
Unit
170
195
55
60
Rev. C | Page 3 of 17
VS = VD = ±10 V; see Figure 26
ADG1233/ADG1234
Parameter
CD, CS (On)
POWER REQUIREMENTS
IDD
Data Sheet
+25°C
3.5
4
Y Version 1
−40°C to +85°C −40°C to +125°C
0.002
1.0
IDD
260
475
ISS
0.002
1.0
ISS
0.002
VDD/VSS
1
2
1.0
±5/±16.5
Temperature range for the Y version: −40°C to +125°C.
Guaranteed by design, not subject to production test.
Rev. C | Page 4 of 17
Unit
pF typ
pF max
µA typ
µA max
µA typ
µA max
µA typ
µA max
µA typ
µA max
V min/max
Test Conditions/Comments
f = 1 MHz; VS = 0 V
f = 1 MHz; VS = 0 V
VDD = +16.5 V, VSS = −16.5 V
Digital inputs = 0 V or VDD
Digital inputs = 5 V
Digital inputs = 0 V or VDD
Digital inputs = 5 V
GND = 0 V
Data Sheet
ADG1233/ADG1234
SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
On Resistance Match Between
Channels (∆RON)
On Resistance Flatness (RFLAT (ON))
LEAKAGE CURRENTS
Source Off Leakage IS (Off )
Drain Off Leakage ID (Off )
Channel On Leakage ID, IS (On)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
+25°C
Y Version 1
−40°C to +85°C −40°C to +125°C
0 to VDD
300
tBBM
567
625
Ω max
Ω typ
16
60
26
27
Ω max
Ω typ
±0.02
nA typ
±0.1
±0.02
±0.6
±1
±0.1
±0.02
±0.2
±0.6
±1
±0.6
±1
2.0
0.8
±0.001
2
135
170
45
nA max
nA typ
nA max
nA typ
nA max
V min
V max
µA typ
µA max
pF typ
ns typ
200
230
10
tON (EN)
V
Ω typ
475
5
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 2
tTRANSITION
Unit
ns typ
ns min
ns typ
Charge Injection
150
195
45
60
−0.3
Off Isolation
−80
dB typ
Channel-to-Channel Crosstalk
−85
dB typ
−3 dB Bandwidth
CS (Off )
600
1.5
1.7
2
2.2
4
4.5
MHz typ
pF typ
pF max
pF typ
pF max
pF typ
pF max
tOFF (EN)
CD (Off )
CD, CS (On)
230
265
70
75
ns typ
pC typ
Rev. C | Page 5 of 17
Test Conditions/Comments
VS = 0 V to 10 V, IS = −1 mA;
see Figure 24
VDD = 10.8 V, VSS = 0 V
VS = 0 V to 10 V, IS = −1 mA
VS = 3 V, 6 V, 9 V, IS = −1 mA
VDD = 13.2 V
VS = 1 V/10 V, VD = 10 V/1 V;
see Figure 25
VS = 1 V/10 V, VD = 10 V/1 V;
see Figure 25
VS = VD = 1 V or 10 V, see Figure 26
VIN = VINL or VINH
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 27
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 8 V; see Figure 28
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 29
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 29
VS = 6 V, RS = 0 Ω, CL = 1 nF; see
Figure 30
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 31
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 33
RL = 50 Ω, CL = 5 pF; see Figure 32
f = 1 MHz; VS = 6 V
f = 1 MHz; VS = 6 V
f = 1 MHz; VS = 6 V
f = 1 MHz; VS = 6 V
f = 1 MHz; VS = 6 V
f = 1 MHz; VS = 6 V
ADG1233/ADG1234
Parameter
POWER REQUIREMENTS
IDD
Data Sheet
+25°C
Y Version 1
−40°C to +85°C −40°C to +125°C
0.002
1.0
IDD
260
VDD
1
2
475
5/16.5
Temperature range for the Y version: −40°C to +125°C
Guaranteed by design, not subject to production test.
Rev. C | Page 6 of 17
Unit
µA typ
µA max
µA typ
µA max
V min/max
Test Conditions/Comments
VDD = 13.2 V
Digital inputs = 0 V or VDD
Digital inputs = 5 V
VSS = 0 V, GND = 0 V
Data Sheet
ADG1233/ADG1234
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VDD to VSS
VDD to GND
VSS to GND
Analog, Digital Inputs1
Continuous Current, S or D
Peak Current, S or D (Pulsed at
1 ms, 10% Duty Cycle Maximum)
Operating Temperature Range
Automotive Temperature Range
(Y Version)
Storage Temperature Range
Junction Temperature
TSSOP, θJA, Thermal Impedance
LFCSP, θJA, Thermal Impedance
Reflow Soldering Peak Temperature,
Pb-Fee
1
Rating
35 V
−0.3 V to +25 V
+0.3 V to −25 V
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs
first
24 mA
100 mA
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Only one absolute maximum rating is applied at any one time.
ESD CAUTION
−40°C to +125°C
−65°C to +150°C
150°C
112°C/W
30.4°C/W
260°C
Overvoltages at A, EN, S, or D are clamped by internal diodes. Current must
be limited to the maximum ratings given.
Rev. C | Page 7 of 17
ADG1233/ADG1234
Data Sheet
VDD
1
16
GND
S1A
2
15
IN1
D1
3
ADG1233
14
EN
S1B
4
TOP VIEW
(Not to Scale)
13
VSS
S1B
4
S2B
5
12
S3B
VSS
5
D2
6
11
D3
GND 6
S2A
7
10
S3A
S2B
IN2
8
9
IN3
IN1 1
20
IN4
2
19
S4A
D1 3
18
D4
17
S4B
16
VDD
15
EN
7
14
S3B
D2
8
13
D3
S2A
9
12
S3A
IN2 10
11
IN3
05743-002
S1A
ADG1234
TOP VIEW
(Not to Scale)
Figure 4. 20-Lead TSSOP Pin Configuration
Figure 3. 16-Lead TSSOP Pin Configuration
Table 4. 16-Lead TSSOP/20-Lead TSSOP Pin Configurations
Pin No. ADG1233 16-Lead TSSOP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Not applicable
Not applicable
Not applicable
Not applicable
05743-003
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Pin No. ADG1234 20-Lead TSSOP
16
2
3
4
7
8
9
10
11
12
13
14
5
15
1
6
17
18
19
20
Rev. C | Page 8 of 17
Mnemonic
VDD
S1A
D1
S1B
S2B
D2
S2A
IN2
IN3
S3A
D3
S3B
VSS
EN
IN1
GND
S4B
D4
S4A
IN4
ADG1233
11 VSS
S2B 3
TOP VIEW
(Not to Scale)
10 S3B
TOP VIEW
(Not to Scale)
15
14
13
12
11
D4
S4B
VDD
S3B
D3
D2
S2A
IN2
IN3
S3A
NOTES
1. NC = NO CONNECT. DO NOT CONNECT
TO THIS PIN.
2. THE EXPOSED PAD MUST BE TIED
TO SUBSTRATE, VSS.
NOTES
1. THE EXPOSED PAD MUST BE TIED
TO SUBSTRATE, VSS.
05743-004
IN3 7
S3A 8
IN2 6
S2A 5
D3
ADG1234
6
7
8
9
10
9
D2 4
S4A
S1A
IN1
EN
IN4
D1 1
S1B 2
VSS 3
GND 4
S2B 5
12 EN
S1B 2
Figure 6. 20-Lead, 4 mm × 4 mm LFCSP Pin Configuration,
Exposed Pad Tied to Substrate, VSS
Figure 5. 16-Lead, 4 mm × 4 mm LFCSP Pin Configuration,
Exposed Pad Tied to Substrate, VSS
Table 5. 16-Lead LFCSP/20-Lead LFCSP Pin Configurations
Pin No. ADG1233 16-Lead LFCSP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Not applicable
Not applicable
Not applicable
Not applicable
Pin No. ADG1234 20-Lead LFCSP
1
2
5
6
7
8
9
10
11
12
3
18
19
4
13
20
14
15
16
17
Mnemonic
D1
S1B
S2B
D2
S2A
IN2
IN3
S3A
D3
S3B
VSS
EN
IN1
GND
VDD
S1A
S4B
D4
S4A
IN4
Table 6. ADG1233/ADG1234 Truth Table
EN
1
0
0
INx
X
0
1
05743-005
D1 1
20
19
18
17
16
13 IN1
14 GND
16 S1A
ADG1233/ADG1234
15 VDD
Data Sheet
Switch xA
Off
Off
On
Switch xB
Off
On
Off
Rev. C | Page 9 of 17
ADG1233/ADG1234
Data Sheet
TERMINOLOGY
VDD
Most positive supply potential.
tOFF (EN)
Delay time between the 50% and 90% points of the digital input
and switch off condition.
VSS
Most negative power supply potential in dual supplies. In
single-supply applications, it can be connected to ground.
tTRANSITION
Delay time between the 50% and 90% points of the digital
inputs and the switch on condition when switching from one
address state to another.
GND
Ground (0 V) reference.
tBBM
RON
Ohmic resistance between D and S.
Off time measured between the 80% point of both switches
when switching from one address state to another.
ΔRON
Difference between the RON of any two channels.
VINL
Maximum input voltage for Logic 0.
IS (Off)
Source leakage current when switch is off.
VINH
Minimum input voltage for Logic 1.
ID (Off)
Drain leakage current when switch is off.
IINL, IINH
Input current of the digital input.
ID, IS (On)
Channel leakage current when switch is on.
IDD
Positive supply current.
VD, VS
Analog voltage on Terminal D, Terminal S.
ISS
Negative supply current.
CS (Off)
Channel input capacitance for off condition.
Off Isolation
A measure of an unwanted signal coupling through an off channel.
CD (Off)
Channel output capacitance for off condition.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
CD, CS (On)
On switch capacitance.
Bandwidth
Frequency at which the output is attenuated by 3 dB.
CIN
Digital input capacitance.
tON (EN)
Delay time between the 50% and 90% points of the digital input
and switch on condition.
On Response
Frequency response of the on switch.
THD + N
Ratio of the harmonic amplitude plus noise of the signal to the
fundamental.
Rev. C | Page 10 of 17
Data Sheet
ADG1233/ADG1234
TYPICAL PERFORMANCE CHARACTERISTICS
200
250
TA = 25°C
180
VDD = +13.5V
VSS = –13.5V
160
200
TA = +125°C
140
ON RESISTANCE (Ω)
120
VDD = +16.5V
VSS = –16.5V
100
80
60
100
TA = –40°C
0
–18 –15 –12
–9 –6 –3
0
3
6
9
SOURCE OR DRAIN VOLTAGE (V)
12
15
0
–15
18
Figure 7. On Resistance as a Function of VD (VS) for Dual Supply
05743-034
05743-031
20
–10
–5
0
5
TEMPERATURE (°C)
10
15
Figure 10. On Resistance as a Function of VD (VS ) for Different Temperatures,
Dual Supply
600
600
TA = 25°C
VDD = 4.5V
VSS = –4.5V
TA = +125°C
500
VDD = 12V
VSS = 0V
500
ON RESISTANCE (Ω)
VDD = 5V
VSS = –5V
400
VDD = 5.5V
VSS = –5.5V
300
200
100
TA = +85°C
400
TA = +25°C
300
TA = –40°C
200
0
–6
05743-032
100
–4
–2
0
2
SOURCE OR DRAIN VOLTAGE (V)
4
05743-035
ON RESISTANCE (W )
TA = +25°C
50
40
0
0
6
2
4
6
8
TEMPERATURE (°C)
10
12
Figure 11. On Resistance as a Function of VD (VS ) for Different Temperatures,
Single Supply
Figure 8. On Resistance as a Function of VD (VS ) for Dual Supply
250
450
TA = 25°C
400
VDD = 10.8V
VSS = 0V
350
150
VDD = 12V
VSS = 0V
300
250
VDD = 13.2V
VSS = 0V
200
VDD = +15V
VSS = –15V
VBIAS = +10V/–10V
200
LEAKAGE CURRENT (pA)
ON RESISTANCE (Ω)
TA = +85°C
150
150
100
100
50
0
–50
IS (OFF) + –
ID (OFF) + –
IS (OFF) – +
ID (OFF) – +
ID, IS (ON) – –
ID, IS (ON) + +
–100
05743-033
–150
50
0
0
2
4
6
8
10
SOURCE OR DRAIN VOLTAGE (V)
12
–200
–250
0
14
Figure 9. On Resistance as a Function of VD (VS ) for Single Supply
05743-017
ON RESISTANCE (Ω)
VDD = +15V
VSS = –15V
VDD = +15V
VSS = –15V
20
40
60
80
TEMPERATURE (°C)
100
120
Figure 12. Leakage Currents as a Function of Temperature, Dual Supply
Rev. C | Page 11 of 17
ADG1233/ADG1234
Data Sheet
130
220
VDD = 12V
VSS = 0V
VBIAS = 1V/10V
180
160
TIME (ns)
30
–20
120
100
80
IS (OFF) + –
ID (OFF) + –
IS (OFF) – +
ID (OFF) – +
ID, IS (ON) – –
ID, IS (ON) + +
20
BOFF AON 12V DS
40
–120
0
BOFF AON 15V DS
60
40
60
80
TEMPERATURE (°C)
100
05743-011
–70
20
0
–40
120
–20
0
20
40
60
TEMPERATURE (°C)
80
100
0
200
IDD PER CHANNEL
TA = 25°C
180
–10
–20
160
OFF ISOLATION (dB)
VDD = +15V
VSS = –15V
140
120
100
80
60
VDD = +15V
VSS = –15V
TA = 25°C
–30
–40
–50
–60
–70
–80
40
0
0
2
4
6
8
10
LOGIC, INX (V)
12
14
05743-036
05743-006
–90
VDD = 12V
VSS = 0V
20
–100
–110
10k
16
100k
1M
10M
FREQUENCY (Hz)
100M
1G
Figure 17. Off Isolation vs. Frequency
Figure 14. IDD vs. Logic Level
–10
6
TA = 25°C
VDD = +15V
VSS = –15V
VDD = +15V
VSS = –15V
TA = 25°C
–20
4
–30
2
0
CROSSTALK (dB)
VDD = +5V
VSS = –5V
VDD = 12V
VSS = 0V
–2
–40
SxA – SxB
–50
–60
–70
S1x – S2x
–80
–6
–15
–10
–5
0
VS (V)
5
10
05743-012
–4
05743-008
CHARGE INJECTION (pC)
120
Figure 16. tTRANSITION vs. Temperature
Figure 13. Leakage Currents as a Function of Temperature, Single Supply
IDD (µA)
AOFF BON 15V DS
140
05743-018
LEAKAGE CURRENT (pA)
80
AOFF BON 12V DS
200
–90
–100
10k
15
100k
1M
10M
FREQUENCY (Hz)
Figure 18. Crosstalk vs. Frequency
Figure 15. Charge Injection vs. Source Voltage
Rev. C | Page 12 of 17
100M
1G
Data Sheet
ADG1233/ADG1234
5.0
0
VDD = +15V
VSS = –15V
TA = 25°C
4.0
CAPACITANCE (pF)
–5
ON RESPONSE (dB)
VDD = 12V
VSS = 0V
TA = 25°C
4.5
–10
–15
SOURCE/DRAIN ON
3.5
3.0
2.5
DRAIN OFF
2.0
1.5
SOURCE OFF
05743-013
–25
10k
100k
1M
10M
100M
FREQUENCY (Hz)
1G
05743-009
1.0
–20
0.5
0
0
10G
Figure 19. On Response vs. Frequency
2
4
8
10
12
Figure 22. Capacitance vs. Source Voltage for Single Supply
10
5.0
LOAD = 10kΩ
TA = 25°C
VDD = +5V
VSS = –5V
TA = 25°C
4.5
SOURCE/DRAIN ON
CAPACITANCE (pF)
4.0
1
THD + N (%)
6
VBIAS (V)
VDD = +5V, VSS = –5V, VS = +3.5V rms
VDD = +15V, VSS = –15V, VS = +5V rms
0.10
3.5
3.0
2.5
DRAIN OFF
2.0
SOURCE OFF
1.5
0.01
10
100
1k
FREQUENCY (Hz)
10k
0.5
100k
Figure 20. THD + N vs. Frequency
VDD = +15V
VSS = –15V
TA = 25°C
SOURCE/DRAIN ON
3.0
2.5
DRAIN OFF
2.0
1.5
SOURCE OFF
1.0
05743-010
CAPACITANCE (pF)
4.0
3.5
0.5
0
–15
–10
–5
0
VBIAS (V)
5
0
–5
–4
–3
–2
–1
0
1
VBIAS (V)
2
3
4
Figure 23. Capacitance vs. Source Voltage for Dual Supply
5.0
4.5
05743-007
05743-037
1.0
10
15
Figure 21. Capacitance vs. Source Voltage for Dual Supply
Rev. C | Page 13 of 17
5
ADG1233/ADG1234
Data Sheet
TEST CIRCUITS
V
S
D
IDS
05743-020
VS
Figure 24. On Resistance
A
S
D
ID (OFF)
A
VS
05743-021
IS (OFF)
VD
Figure 25. Off Leakage
ID (ON)
D
NC = NO CONNECT
A
VD
05743-022
S
NC
Figure 26. On Leakage
VDD
VDD
VS
0.1µF
50%
50%
VIN
50%
50%
VSS
SxB
D
SxA
VOUT
RL
300Ω
INx
VIN
VIN
CL
35pF
90%
VOUT
GND
tON
90%
tOFF
05743-023
0.1µF
VSS
Figure 27. Switching Timing
VS
VDD
VSS
VDD
VSS
SxB
VIN
D
SxA
VOUT
RL
300Ω
INx
VIN
0.1µF
CL
35pF
VOUT
80%
tBBM
GND
tBBM
05743-024
0.1µF
Figure 28. Break-Before-Make Delay
Rev. C | Page 14 of 17
Data Sheet
ADG1233/ADG1234
0.1µF
VDD
VSS
VDD
VSS
0.1µF
3V
VS
S1A
EN
tOFF (EN)
VO
D1
50Ω
50%
0V
S1B
ADG1233
VIN
50%
CL
35pF
RL
300Ω
GND
VO
0.9VO
0.9VO
OUTPUT
0V
05743-025
IN3
IN2
IN1
ENABLE
DRIVE (VIN)
tON (EN)
Figure 29. Enable Delay, tON (EN), tOFF (EN)
VSS
VDD
VSS
0.1µF
VIN (NORMALLY
CLOSED SWITCH)
ON
SxB
NC
D
VS
VOUT
SxA
CL
1nF
INx
VIN
OFF
VIN (NORMALLY
OPEN SWITCH)
VOUT
GND
∆VOUT
QINJ = CL × ∆VOUT
05743-026
0.1µF
VDD
Figure 30. Charge Injection
VDD
VDD
0.1µF
VSS
VDD
VSS
NETWORK
ANALYZER
NC
SxA
INx
SxB
VSS
0.1µF
0.1µF
0.1µF
NETWORK
ANALYZER
50Ω
VOUT
VDD
VSS
SxA
RL
50Ω
50Ω
VS
SxB
D
D
VIN
RL
50Ω
GND
VOUT
INx
VS
VOUT
VS
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
Figure 31. Off Isolation
0.1µF
VDD
VSS
NC
INx
SxA
VSS
0.1µF
0.1µF
NETWORK
ANALYZER
50Ω
VDD
AUDIO PRECISION
VSS
RS
SxB
VS
S
INx
D
VIN
RL
50Ω
GND
VOUT
VIN
INSERTION LOSS = 20 log
VOUT WITHOUT SWITCH
RL
10Ω
05743-028
GND
VOUT WITH SWITCH
VS
V p-p
D
Figure 34. THD + Noise
Figure 32. Bandwidth
Rev. C | Page 15 of 17
VOUT
05743-030
VDD
VOUT
VS
Figure 33. Channel-to-Channel Crosstalk
VSS
0.1µF
05743-029
05743-027
GND
OFF ISOLATION = 20 log
VDD
R
50Ω
ADG1233/ADG1234
Data Sheet
OUTLINE DIMENSIONS
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
8
1
PIN 1
1.20
MAX
0.15
0.05
0.20
0.09
0.30
0.19
0.65
BSC
COPLANARITY
0.10
0.75
0.60
0.45
8°
0°
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 35. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
6.60
6.50
6.40
20
11
4.50
4.40
4.30
6.40 BSC
10
1
PIN 1
0.65
BSC
1.20 MAX
0.15
0.05
COPLANARITY
0.10
0.30
0.19
0.20
0.09
SEATING
PLANE
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AC
Figure 36. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
Rev. C | Page 16 of 17
0.75
0.60
0.45
Data Sheet
ADG1233/ADG1234
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
0.35
0.30
0.25
0.65
BSC
PIN 1
INDICATOR
16
13
1
12
EXPOSED
PAD
2.25
2.10 SQ
1.95
9
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
0.25 MIN
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
111908-A
TOP VIEW
4
5
8
0.70
0.60
0.50
COMPLIANT TO JEDEC STANDARDS MO-220-WGGC.
Figure 37. 16-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-16-23)
Dimensions shown in millimeters
0.30
0.25
0.18
0.50
BSC
PIN 1
INDICATOR
20
16
15
1
EXPOSED
PAD
2.30
2.10 SQ
2.00
11
TOP VIEW
0.80
0.75
0.70
0.65
0.60
0.55
5
10
0.20 MIN
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
6
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-1.
08-16-2010-B
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
Figure 38. 20-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-20-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADG1233YRUZ
ADG1233YRUZ-REEL7
ADG1233YCPZ-REEL7
ADG1234YRUZ
ADG1234YRUZ-REEL7
ADG1234YCPZ-REEL
ADG1234YCPZ-REEL7
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Thin Shrink Small Outline Package [TSSOP]
16-Lead Lead Frame Chip Scale Package [LFCSP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Thin Shrink Small Outline Package [TSSOP]
20-Lead Lead Frame Chip Scale Package [LFCSP]
20-Lead Lead Frame Chip Scale Package [LFCSP]
Z = RoHS Compliant Part.
©2006–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05743-0-3/16(C)
Rev. C | Page 17 of 17
Package Option
RU-16
RU-16
CP-16-23
RU-20
RU-20
CP-20-6
CP-20-6