FEATURES
FUNCTIONAL BLOCK DIAGRAM
1.5 pF off source capacitance
<1 pC charge injection
33 V supply range
120 Ω on resistance
Fully specified at ±15 V, +12 V
No VL supply required
3 V logic-compatible inputs
Rail-to-rail operation
14-lead TSSOP and 12-lead LFCSP
Typical power consumption < 0.03 μW
ADG1204
S1
S2
D
S3
S4
1 OF 4
DECODER
A0
A1
EN
04779-001
Data Sheet
Low Capacitance, Low Charge Injection,
±15 V/+12 V, 4:1 iCMOS Multiplexer
ADG1204
Figure 1.
APPLICATIONS
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Audio signal routing
Video signal routing
Communication systems
GENERAL DESCRIPTION
The ADG1204 is a complementary metal-oxide semiconductor
(CMOS) analog multiplexer, comprising four single channels
designed on an iCMOS (industrial CMOS) process. iCMOS® is a
modular manufacturing process that combines high voltage CMOS
and bipolar technologies. It enables the development of a wide
range of high performance analog ICs capable of 33 V operation
in a footprint that no previous generation of high voltage devices
has been able to achieve. Unlike analog ICs using conventional
CMOS processes, iCMOS components can tolerate high supply
voltages while providing increased performance, dramatically
lower power consumption, and reduced package size.
The ultralow capacitance and charge injection of this multiplexer
makes it an ideal solution for data acquisition and sample-andhold applications, where low glitch and fast settling are required.
Fast switching speed coupled with high signal bandwidth makes
the device suitable for video signal switching. iCMOS construction
ensures ultralow power dissipation, making the device ideally
suited for portable and battery-powered instruments.
Rev. C
The ADG1204 switches one of four inputs to a common output, D,
as determined by the 3-bit binary address lines: A0, A1, and EN.
Logic 0 on the EN pin disables the device. Each switch conducts
equally well in both directions when on and has an input signal
range that extends to the supplies. In the off condition, signal
levels up to the supplies are blocked. All switches exhibit breakbefore-make switching action.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
1.5 pF off capacitance (±15 V supply).
<1 pC charge injection.
3 V logic-compatible digital inputs: VIH = 2.0 V, VIL = 0.8
V.
No VL logic power supply required.
Ultralow power dissipation: <0.03 μW.
14-lead TSSOP and 12-lead, 3 mm × 3 mm LFCSP
packages.
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ADG1204
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................7
Applications ....................................................................................... 1
Pin Configurations and Function Descriptions ............................8
Functional Block Diagram .............................................................. 1
Truth Table .....................................................................................8
General Description ......................................................................... 1
Typical Performance Characteristics ..............................................9
Product Highlights ........................................................................... 1
Test Circuits..................................................................................... 12
Revision History ............................................................................... 2
Terminology .................................................................................... 14
Specifications..................................................................................... 3
Outline Dimensions ....................................................................... 15
Dual Supply ................................................................................... 3
Ordering Guide .......................................................................... 15
Single Supply ................................................................................. 5
Absolute Maximum Ratings ............................................................ 7
REVISION HISTORY
3/16—Rev. B to Rev. C
Changed LFCSP_VQ to LFCSP ................................... Throughout
Changes to Figure 3 .......................................................................... 8
Updated Outline Dimensions ....................................................... 15
Changes to Ordering Guide .......................................................... 15
7/06—Rev. 0 to Rev. A
Updated Format .................................................................. Universal
Changes to Table 1.............................................................................3
Changes to Table 2.............................................................................5
Changes to the Terminology Section ........................................... 14
2/09—Rev. A to Rev. B
Changes to Power Requirements, IDD, Digital Inputs = 5 V
Parameter, Table 1............................................................................. 4
Changes to Power Requirements, IDD, Digital Inputs = 5 V
Parameter, Table 2............................................................................. 6
Updated Outline Dimensions ....................................................... 15
7/05—Revision 0: Initial Version
Rev. C | Page 2 of 16
Data Sheet
ADG1204
SPECIFICATIONS
DUAL SUPPLY
VDD = 15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
On Resistance Match Between
Channels (ΔRON)
On Resistance Flatness (RFLAT(ON))
25°C
Y Version 1
−40°C to
+85°C
VDD to VSS
120
190
3.5
6
20
57
230
260
10
12
72
79
LEAKAGE CURRENTS
Source Off Leakage, IS (OFF)
±0.02
±0.6
Drain Off Leakage, ID (OFF)
±0.1
±0.02
±0.1
±0.02
±0.2
Channel On Leakage, ID, IS (ON)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or INH
−40°C to
+125°C
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
VS = ±10 V, VD = ∓10 V; see Figure 22
nA max
nA typ
VS = ±10 V, VD = ∓10 V; see Figure 22
±0.6
±1
VS = VD = ±10 V; see Figure 23
±0.6
±1
nA max
nA typ
nA max
V min
V max
µA typ
µA max
pF typ
VIN = VINL or VINH
2.0
0.8
0.005
2.5
Break-Before-Make Time Delay, tD
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion + Noise
−0.7
85
80
0.15
Bandwidth −3 dB
CS (OFF)
800
1.2
1.5
3.6
4.2
5.5
6.5
MHz typ
pF typ
pF max
pF typ
pF max
pF typ
pF max
180
200
100
110
135
155
10
CD (OFF)
CD, CS (ON)
VS = −5 V, 0 V, +5 V; IS = −1 mA
±1
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
% typ
tOFF (EN)
VS = ±10 V, IS = −1 mA; see Figure 21
VDD = +13.5 V, VSS = −13.5 V
VS = ±10 V, IS = −1 mA
VDD = +16.5 V, VSS = −16.5 V
120
150
70
85
90
110
25
tON (EN)
Test Conditions/Comments
nA typ
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 2
Transition Time, tTRANS
Unit
Rev. C | Page 3 of 16
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 24
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 26
RL = 300 Ω, CL = 35 pF
VS = 10 V; see Figure 26
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 10 V; see Figure 25
VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 27
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 30
RL = 10 kΩ, 5 V rms, f = 20 Hz to 20 kHz;
see Figure 31
RL = 50 Ω, CL = 5 pF; see Figure 29
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
f = 1 MHz, VS = 0 V
ADG1204
Parameter
POWER REQUIREMENTS
IDD
Data Sheet
25°C
Y Version 1
−40°C to
+85°C
−40°C to
+125°C
0.001
1.0
IDD
170
285
ISS
0.001
1.0
ISS
0.001
1.0
1
2
Y version temperature range is −40°C to +125°C.
Guaranteed by design, not subject to production test.
Rev. C | Page 4 of 16
Unit
µA typ
µA max
µA typ
µA max
µA typ
µA max
µA typ
µA max
Test Conditions/Comments
VDD = +16.5 V, VSS = −16.5 V
Digital inputs = 0 V or VDD
Digital inputs = 5 V
Digital inputs = 0 V or VDD
Digital inputs = 5 V
Data Sheet
ADG1204
SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
On Resistance Match Between Channels
(ΔRON)
On Resistance Flatness (RFLAT(ON))
LEAKAGE CURRENTS
Source Off Leakage, IS (OFF)
Drain Off Leakage, ID (OFF)
Channel On Leakage, ID, IS (ON)
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IINL or IINH
25°C
Y Version 1
−40°C to
−40°C to
+85°C
+125°C
0 V to VDD
300
475
5
16
60
±0.02
±0.1
±0.02
±0.1
±0.02
±0.2
567
625
26
27
±0.6
±1
±0.6
±1
±0.6
±1
2.0
0.8
0.001
±0.1
Digital Input Capacitance, CIN
DYNAMIC CHARACTERISTICS 2
Transition Time, tTRANS
2.5
Unit
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
nA typ
nA max
nA typ
nA max
nA typ
nA max
V min
V max
µA typ
µA max
pF typ
Break-Before-Make Time Delay, tD
150
190
95
120
100
125
50
Charge Injection
−0.4
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
Off Isolation
85
dB typ
Channel-to-Channel Crosstalk
80
dB typ
Bandwidth −3 db
CS (OFF)
550
1.2
1.5
3.6
4.2
5.5
6.5
MHz typ
pF typ
pF max
pF typ
pF max
pF typ
pF max
tON (EN)
tOFF (EN)
240
265
150
170
155
170
10
CD (OFF)
CD, CS (ON)
Rev. C | Page 5 of 16
Test Conditions/Comments
VS = 0 V to 10 V, IS = −1 mA;
see Figure 21
VDD = 10.8 V, VSS = 0 V
VS = 0 V to 10 V, IS = −1 mA
VS = 3 V, 6 V, 9 V; IS = −1 mA
VDD = 13.2 V
VS = 1 V/10 V, VD = 10 V/1 V;
see Figure 22
VS = 1 V/10 V, VD = 10 V/1 V;
see Figure 22
VS = VD = 1 V or 10 V; see Figure 23
VIN = VINL or VINH
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 24
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 26
RL = 300 Ω, CL = 35 pF
VS = 8 V; see Figure 26
RL = 300 Ω, CL = 35 pF
VS1 = VS2 = 8 V; see Figure 25
VS = 6 V, RS = 0 Ω, CL = 1 nF;
see Figure 27
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 28
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 30
RL = 50 Ω, CL = 5 pF; see Figure 29
f = 1 MHz; VS = 6 V
f = 1 MHz; VS = 6 V
f = 1 MHz; VS = 6 V
f = 1 MHz; VS = 6 V
f = 1 MHz; VS = 6 V
f = 1 MHz; VS = 6 V
ADG1204
Parameter
POWER REQUIREMENTS
IDD
Data Sheet
25°C
Y Version 1
−40°C to
−40°C to
+85°C
+125°C
0.001
1.0
IDD
170
285
1
2
Y version temperature range is −40°C to +125°C.
Guaranteed by design, not subject to production test.
Rev. C | Page 6 of 16
Unit
µA typ
µA max
µA typ
µA max
Test Conditions/Comments
VDD = 13.2 V
Digital inputs = 0 V or VDD
Digital inputs = 5 V
Data Sheet
ADG1204
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VDD to VSS
VDD to GND
VSS to GND
Analog Inputs 1
Digital Inputs1
Peak Current, S or D
Continuous Current
Operating Temperature Range
Automotive (Y Version)
Storage Temperature Range
Junction Temperature
14-Lead TSSOP, θJA Thermal
Impedance (4-Layer Board)
12-Lead LFCSP,
θJA Thermal Impedance
Reflow Soldering Peak
Temperature, Pb Free
1
Rating
35 V
−0.3 V to +25 V
+0.3 V to −25 V
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
GND − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
100 mA (pulsed at 1 ms,
10% duty cycle maximum)
45 mA
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Only one absolute maximum rating can be applied at any one time.
ESD CAUTION
−40°C to +125°C
−65°C to +150°C
150°C
112°C/W
80°C/W
260°C
Overvoltages at IN, S, or D are clamped by internal diodes. Current must be
limited to the maximum ratings given.
Rev. C | Page 7 of 16
ADG1204
Data Sheet
3
S1
4
S2
5
D
6
NC
7
ADG1204
TOP VIEW
(Not to Scale)
GND
12
VDD
S2 3
11
S3
10
S4
9
NC
8
NC
NC = NO CONNECT
11 A0
ADG1204
TOP VIEW
(Not to Scale)
9 GND
8 VDD
7 S3
NOTES
1. NC = NO CONNECT. DO NOT CONNECT
TO THIS PIN.
2. THE EXPOSED PAD MUST BE TIED
TO SUBSTRATE, VSS.
Figure 2. TSSOP Pin Configuration
04779-003
VSS
13
S1 2
S4 6
2
VSS 1
A1
NC 5
EN
14
D 4
1
04779-002
A0
10 A1
12 EN
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 3. LFCSP Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
TSSOP
LFCSP
1
11
2
12
Mnemonic
A0
EN
3
4
5
6
7 to 9
10
11
12
13
14
VSS
S1
S2
D
NC
S4
S3
VDD
GND
A1
1
2
3
4
5
6
7
8
9
10
Description
Logic Control Input.
Active High Digital Input. When low, the device is disabled and all switches are off.
When high, Ax logic inputs determine on switches.
Most Negative Power Supply Potential.
Source Terminal. Can be an input or an output.
Source Terminal. Can be an input or an output.
Drain Terminal. Can be an input or an output.
No Connection.
Source Terminal. Can be an input or an output.
Source Terminal. Can be an input or an output.
Most Positive Power Supply Potential.
Ground (0 V) Reference.
Logic Control Input.
TRUTH TABLE
Table 5.
EN
0
1
1
1
1
A1
X
0
0
1
1
A0
X
0
1
0
1
S1
Off
On
Off
Off
Off
Rev. C | Page 8 of 16
S2
Off
Off
On
Off
Off
S3
Off
Off
Off
On
Off
S4
Off
Off
Off
Off
On
Data Sheet
ADG1204
TYPICAL PERFORMANCE CHARACTERISTICS
250
200
180
VDD = +13.5V
VSS = –13.5V
160
200
140
ON RESISTANCE (Ω)
120
100
VDD = +15V
VSS = –15V
80
VDD = +16.5V
VSS = –16.5V
60
40
TA = +125°C
150
TA = +85°C
100
TA = –40°C
04779-010
20
0
–18 –15 –12
–9 –6
–3
0
3
6
9
SOURCE OR DRAIN VOLTAGE (V)
12
15
0
–15
18
Figure 4. On Resistance as a Function of VD (VS), Dual Supply
5
–5
0
SOURCE OR DRAIN VOLTAGE (V)
–10
10
15
Figure 7. On Resistance as a Function of VD (VS) for Different Temperatures,
Dual Supply
450
600
TA = +25°C
VDD = +12V
VSS = 0V
400
TA = +125°C
500
350
TA = +85°C
ON RESISTANCE (Ω)
ON RESISTANCE (Ω)
TA = +25°C
50
04779-006
ON RESISTANCE (Ω)
VDD = +15V
VSS = –15V
TA = +25°C
VDD = +5.5V
VSS = –5.5V
300
250
200
150
400
300
200
TA = –40°C
100
TA = +25°C
50
0
–5
–4
–3
–2
–1
0
1
2
3
SOURCE OR DRAIN VOLTAGE (V)
4
04779-007
04779-004
100
0
5
0
Figure 5. On Resistance as a Function of VD (VS), Dual Supply
4
6
8
SOURCE OR DRAIN VOLTAGE (V)
10
12
Figure 8. On Resistance as a Function of VD (VS) for Different Temperatures,
Single Supply
450
0.30
TA = 25°C
400
0.20
LEAKAGE (nA)
300
250
VDD = 13.2V
VSS = 0V
200
VDD = +16.5V
VSS = –16.5V
VBIAS = +10V/–10V
0.25
VDD = 12V
VSS = 0V
VDD = 10.8V
VSS = 0V
350
ID, IS (ON)
0.15
0.10
IS (OFF)
0.05
150
0
50
–0.05
0
0
2
4
6
8
10
SOURCE OR DRAIN VOLTAGE (V)
12
–0.10
14
Figure 6. On Resistance as a Function of VD (VS), Single Supply
ID (OFF)
04779-008
100
04779-005
ON RESISTANCE (Ω)
2
0
20
40
80
60
TEMPERATURE (°C)
100
120
Figure 9. Leakage Currents as a Function of Temperature, Dual Supply
Rev. C | Page 9 of 16
ADG1204
Data Sheet
0.20
250
VDD = 13.2V
VSS = 0V
VBIAS = 10V/1V
0.15
200
0.10
VDD = +12V, VSS = 0V
0.05
TIME (ns)
LEAKAGE (nA)
ID, IS (ON)
ID (OFF)
0
–0.05
150
VDD = +15V, VSS = –15V
100
IS (OFF)
–0.10
04779-009
–0.20
0
20
40
60
80
TEMPERATURE (°C)
100
0
–40
120
Figure 10. Leakage Currents as a Function of Temperature, Single Supply
0
–20
60
20
40
TEMPERATURE (°C)
100
80
120
Figure 13. Transition Times vs. Temperature
60
0
IDD PER CHANNEL
TA = +25°C
–10
50
OFF ISOLATION (dB)
–20
VDD = +15V, VSS = –15V
40
IDD (µA)
04779-015
50
–0.15
30
20
VDD = +15V
VSS = –15V
TA = +25°C
–30
–40
–50
–60
–70
–80
VDD = +12V, VSS = 0V
0
0
2
8
10
6
LOGIC, INX (V)
4
12
–100
–110
10k
14
Figure 11. IDD vs. Logic Level
1M
10M
FREQUENCY (Hz)
100M
1G
0
SOURCE TO DRAIN
DRAIN TO SOURCE
TA = +25°C
–10
–20
VDD = +15V
VSS = –15V
TA = +25°C
–30
0
CROSSTALK (dB)
2
VDD = +5V, VSS = –5V
VDD = +12V, VSS = 0V
–2
–40
S1 TO S2
–50
–60
–70
S2 TO S4
–80
–90
–6
–15
VDD = +15V, VSS = –15V
–10
–5
0
VS (V)
–100
5
10
04779-017
–4
04779-014
CHARGE INJECTION (pC)
100k
Figure 14. Off Isolation vs. Frequency
6
4
04779-016
–90
04779-011
10
–110
–120
10k
15
100k
1M
10M
FREQUENCY (Hz)
Figure 15. Crosstalk vs. Frequency
Figure 12. Charge Injection vs. Source Voltage
Rev. C | Page 10 of 16
100M
1G
Data Sheet
ADG1204
6.5
0
VDD = +15V
VSS = –15V
TA = +25°C
6.3
6.1
CAPACITANCE (pF)
–10
–15
–20
5.9
S1
5.7
S3
5.5
S4
5.3
S2
5.1
4.9
04779-018
–25
–30
10k
100k
1M
10M
100M
FREQUENCY (Hz)
1G
04779-032
ON RESPONSE (dB)
–5
VDD = +15V
VSS = –15V
TA = +25°C
4.7
4.5
–10
10G
Figure 16. On Response vs. Frequency
–8
–6
–4
–2
0
2
VBIAS (V)
4
6
8
10
Figure 19. On Capacitance vs. Source Voltage
9
VDD = 12V
VSS = 0V
TA = 25°C
10.00
8
LOAD = +10kΩ
TA = +25°C
CAPACITANCE (pF)
1.00
THD + N (%)
SOURCE/DRAIN ON
7
VDD = +5V, VSS = –5V, VS = +3.5Vrms
VDD = +15V, VSS = –15V, VS = +5Vrms
0.10
6
5
4
DRAIN OFF
3
04779-019
1
0.01
10
100
1k
FREQUENCY (Hz)
10k
0
100k
D
VDD = +15V
VSS = –15V
TA = +25°C
2.5
2.0
S1
1.5
S3
1.0
S2
0.5
0
–10
04779-031
CAPACITANCE (pF)
3.0
S4
–8
–6
–4
–2
0
2
VBIAS (V)
4
2
4
6
VBIAS (V)
8
10
Figure 20. Capacitance vs. Source Voltage, Single Supply
4.5
3.5
SOURCE OFF
0
Figure 17. THD + N vs. Frequency
4.0
04779-033
2
6
8
10
Figure 18. Off Capacitance vs. Source Voltage
Rev. C | Page 11 of 16
12
ADG1204
Data Sheet
TEST CIRCUITS
V
S
D
IDS
04779-020
VS
Figure 21. On Resistance
S
A
D
ID (OFF)
A
VS
04779-021
IS (OFF)
VD
Figure 22. Off Leakage
ID (ON)
S
D
A
VD
NC = NO CONNECT
04779-022
NC
Figure 23. On Leakage
A1
VDD VSS
A0
VS
2.4V
EN
0.1µF
S1
S2
S3
S4
ADDRESS
DRIVE (VIN)
VS1
VS4
3V
50%
VOUT
RL
300Ω
90%
90%
VOUT
D
GND
50%
0V
tTRANSITION
CL
35pF
tTRANSITION
04779-023
0.1µF
VDD VSS
Figure 24. Address to Output Switching Times
VS
50Ω
2.4V
A1
A0
VDD VSS
EN
0.1µF
S1
S2
S3
S4
VOUT
D
GND
ADDRESS
DRIVE (VIN)
VS1
0V
VOUT
CL
35pF
RL
300Ω
3V
80%
80%
04779-024
0.1µF
VDD VSS
tBBM
Figure 25. Break-Before-Make Time Delay
A1
VDD VSS
VDD VSS
A0
EN
VS
50Ω
0.1µF
S1
S2
S3
S4
ENABLE
DRIVE (VIN)
VS
50%
VO
RL
300Ω
CL
35pF
VOUT
0.9VO
0.9VO
0V
Figure 26. Enable-to-Output Switching Delay
Rev. C | Page 12 of 16
50%
0V
OUTPUT
D
GND
3V
tON (EN)
tOFF (EN)
04779-025
0.1µF
Data Sheet
ADG1204
VDD
VSS
VDD
VSS
S
D
VOUT
RS
ΔVOUT
QINJ = CL × ΔVOUT
VOUT
VIN
CL
1nF
VS
SW OFF
SW OFF
SW ON
DECODER
GND
SW ON
VIN
SW OFF
SW OFF
04779-026
A1 A2
EN
Figure 27. Charge Injection
VDD
VSS
VDD
NETWORK
ANALYZER
NETWORK
ANALYZER
VSS
VOUT
S
VDD
S2
GND
VOUT
GND
OFF ISOLATION = 20 log
VOUT
VS
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
Figure 28. Off Isolation
VDD
0.1µF
VSS
0.1µF
0.1µF
NETWORK
ANALYZER
VSS
VOUT
VS
Figure 30. Channel-to-Channel Crosstalk
VSS
VDD
R
50Ω
VS
04779-027
RL
50Ω
VSS
D
VS
D
0.1µF
0.1µF
S1
RL
50Ω
50Ω
50Ω
VDD
VSS
0.1µF
0.1µF
0.1µF
04779-029
VDD
AUDIO PRECISION
VDD
VSS
RS
50Ω
S
IN
VS
D
RL
50Ω
GND
VOUT
VIN
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
04779-028
GND
INSERTION LOSS = 20 log
VS
V p-p
D
Figure 29. Bandwidth
Rev. C | Page 13 of 16
RL
10kΩ
VOUT
04779-030
S
Figure 31. THD + Noise
ADG1204
Data Sheet
TERMINOLOGY
IDD
The positive supply current.
CD, CS (On)
The on switch capacitance, measured with reference to ground.
ISS
The negative supply current.
CIN
The digital input capacitance.
VD (VS)
The analog voltage on Terminal D and Terminal S.
tON (EN)
The delay between applying the digital control input and the
output switching on.
RON
The ohmic resistance between D and S.
RFLAT(ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance, as measured over the specified
analog signal range.
IS (OFF)
The source leakage current with the switch off.
ID (OFF)
The drain leakage current with the switch off.
ID, IS (ON)
The channel leakage current with the switch on.
VINL
The maximum input voltage for Logic 0.
VINH
The minimum input voltage for Logic 1.
IINL (IINH)
The input current of the digital input.
CS (OFF)
The off switch source capacitance, which is measured with
reference to ground.
CD (OFF)
The off switch drain capacitance, which is measured with
reference to ground.
tOFF (EN)
The delay between applying the digital control input and the
output switching off.
tTRANS
The delay time between the 50% and 90% points of the digital
input and switch on condition when switching from one
address state to another.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
Off Isolation
A measure of unwanted signal coupling through an off switch.
Crosstalk
A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.
Bandwidth
The frequency at which the output is attenuated by −3 dB.
On Response
The frequency response of the on switch.
Insertion Loss
The loss due to the on resistance of the switch.
Total Harmonic Distortion + Noise (THD + N)
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.
Rev. C | Page 14 of 16
Data Sheet
ADG1204
OUTLINE DIMENSIONS
5.10
5.00
4.90
14
8
4.50
4.40
4.30
6.40
BSC
1
7
PIN 1
0.65 BSC
1.20
MAX
0.15
0.05
COPLANARITY
0.10
0.30
0.19
0.20
0.09
0.75
0.60
0.45
8°
0°
SEATING
PLANE
061908-A
1.05
1.00
0.80
COMPLIANT TO JEDEC STANDARDS MO-153-AB-1
Figure 32. 14-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-14)
Dimensions shown in millimeters
0.30
0.23
0.18
0.50
BSC
10
PIN 1
INDICATOR
12
1
9
EXPOSED
PAD
1.45
1.30 SQ
1.15
3
7
TOP VIEW
0.80
0.75
0.70
0.70
0.60
0.50
6
0.25 MIN
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
4
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WEED.
111808-A
PIN 1
INDICATOR
3.10
3.00 SQ
2.90
Figure 33. 12-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 mm Package Height
(CP-12-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
ADG1204YRUZ
ADG1204YRUZ-REEL
ADG1204YRUZ-REEL7
ADG1204YCPZ-500RL7
ADG1204YCPZ-REEL7
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
14-Lead Thin Shrink Small Outline Package [TSSOP]
14-Lead Thin Shrink Small Outline Package [TSSOP]
14-Lead Thin Shrink Small Outline Package [TSSOP]
12-Lead Lead Frame Chip Scale Package [LFCSP]
12-Lead Lead Frame Chip Scale Package [LFCSP]
Z = RoHS Compliant Part.
Rev. C | Page 15 of 16
Package Option
RU-14
RU-14
RU-14
CP-12-4
CP-12-4
ADG1204
Data Sheet
NOTES
©2005–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04779-0-3/16(C)
Rev. C | Page 16 of 16