AN-698
APPLICATION NOTE
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Configuration Registers of the
ADM1062/ADM1063/ADM1064/ADM1065/ADM1066/ ADM1067/ADM1166
by Peter Canty and Michael Bradley
INTRODUCTION
AUX1 AUX2
This application note briefly outlines the functions of the
devices and provides details of the registers required to set up
device configuration.
ADM1066
EEPROM
CLOSED LOOP
MARGINING SYSTEM
VX1
CONFIGURABLE
OUTPUT
DRIVERS
DUAL
FUNCTION
INPUTS
VX2
VX3
VX5
VP3
PROGRAMMABLE
RESET
GENERATORS
VP4
(SFDs)
CONFIGURABLE
OUTPUT
DRIVERS
(LV-CAPABLE
OF DRIVING
LOGIC
SIGNALS)
VH
PDO4
PDO5
PDO6
PDO7
PDO8
PDO9
PDO10
PDOGND
VOUT
DAC
VOUT
DAC
VOUT
DAC
VOUT
DAC
VOUT
DAC
AGND
DAC1 DAC2 DAC3 DAC4 DAC5 DAC6
VDD
ARBITRATOR
VCCP GND
Figure 1. ADM1066 Functional Block Diagram
Rev. C | Page 1 of 36
PDO2
SEQUENCING
ENGINE
VP1
VP2
PDO1
PDO3
(HV-CAPABLE
OF DRIVING
GATE OF
N-CHANNEL
FET)
(LOGIC
INPUTS
OR SFDs)
VX4
VOUT
DAC
For more information on the features and functions of the
ADM1062/ADM1063/ADM1064/ADM1065/ADM1066/
ADM1067/ADM1166, see the relevant data sheets.
12-BIT
SAR ADC
VDDCAP
04615-001
All features of the ADM1062/ADM1063/ADM1064/ADM1065/
ADM1066/ADM1067/ADM1166 are programmable through an
SMBus interface. The devices also contain nonvolatile memory
(EEPROM) so that the configuration of these features can be
stored on-chip and downloaded on each power-up.
SMBus
INTERFACE
VREF
MUX
The ADM1062/ADM1063/ADM1064/ADM1065/ADM1066/
ADM1067/ADM1166 family of fully programmable supply
sequencers and supervisors can be used as complete supply
management solutions in systems using multiple voltage
supplies. Such applications include line cards in telecommunications infrastructure equipment (central office, base stations)
and blade cards in servers.
REFIN REFOUT REFGND SDA SCL A1 A0
AN-698
Application Note
TABLE OF CONTENTS
Introduction ...................................................................................... 1
Revision History ............................................................................... 2
ADM1062/ADM1063/ADM1064/ADM1066/ADM1166
ADC ................................................................................................. 25
Updating Memory, Enabling Block Erase, and Downloading
EEPROM............................................................................................ 3
ADM1062/ADM1066/ADM1067/ADM1166 DACs................. 29
Inputs .................................................................................................. 4
Warnings...................................................................................... 32
Outputs ............................................................................................ 12
Fault/Status Reporting ............................................................... 32
Sequencing Engine ......................................................................... 18
Black Box Status Registers and Fault Records on the
ADM1166 .................................................................................... 33
Configuring Sequence Engine States to Write into the Black
Box EEPROM on the ADM1166 .............................................. 23
Warnings, Faults, and Status ......................................................... 32
Use of the REVID Register ........................................................ 33
REVISION HISTORY
7/13—Rev. B to Rev. C
Changes to Table 3, PDO Status Columns and PDO
Pull-Up Columns ............................................................................ 13
11/10—Rev. A to Rev. B
Added the ADM1166 ................................................... Throughout
Changes to Introduction .................................................................. 1
Deleted Figure 2 Through Figure 5 and Figure 7 Through
Figure 10 ......................................................................... Throughout
Renumbered Figures Sequentially ............................... Throughout
Separated Table 6 into Table 6 and Table 7 ................................. 20
Renumbered Tables Sequentially................................. Throughout
Added Table 9 Through Table 11, Table 20, and
Table 21 ........................................................................... Throughout
Added the Configuring Sequence Engine States to Write into the
Black Box EEPROM on the ADM1166 Section ......................... 22
Changes to Table 13 ........................................................................ 24
Added the Black Box Status Registers and Fault Records on the
ADM1166 Section .......................................................................... 32
Added the Use of the REVID Section .......................................... 32
Changes to Table 22 ........................................................................ 34
2/07—Rev. 0 to Rev. A
Rev. C | Page 2 of 36
Application Note
AN-698
UPDATING MEMORY, ENABLING BLOCK ERASE, AND DOWNLOADING EEPROM
The register/bit map detail in Figure 2 shows the configuration
required to
This application note contains all of the register information
required to configure the many features of the ADM1062/
ADM1063/ADM1064/ADM1065/ADM1066/ADM1067/
ADM1166. The devices contain both volatile and nonvolatile
memory, which must be set up correctly if any alterations to
the configuration are to be updated properly in the device.
The volatile memory of the devices is constructed with double
buffered latches. For information on this construction, see the
relevant device data sheet.
•
•
•
•
Update volatile memory in real time.
Update volatile memory offline, then update all at once.
Enable block erase.
Download EEPROM contents to RAM.
There are also a number of configuration bits that are used to
update the sequencing engine. These bits are detailed in Table 1
SMBus
DEVICE
CONTROLLER
EEPROM
D
A
T
A
E
E
P
R
O
M
L
D
R
A
M
L
D
U
P
D
LATCH A
LATCH B
FUNCTION,
FOR EXAMPLE,
OV THRESHOLD
ON VP 1
04615-003
POWER-UP
VCC > 2.5V
Figure 2. Configuration Update Flow Diagram
Table 1.
Reg.
0x90
0xD8
0xF4
Reg. Name
UPDCFG
UDOWNLD
MANID
Bit No.
7:3
2
1
0
7:1
0
Mnemonic
N/A
EEBLKERS
CFGUPD
CONTUPD
N/A
EEDWNLD
R/W
7:0
MANID
R
R/W
W
R/W
W
Description
Cannot be used.
Enable configuration EEPROM block erase.
Update configuration registers from holding registers (self-clears).
Enable continuous update of configuration registers.
Cannot be used.
Download configuration data from EEPROM. This also happens automatically at
power-up. Self-clears on completion.
Manufacturer’s ID, returns 0x41. Can be used to verify communication with the
device.
Rev. C | Page 3 of 36
AN-698
Application Note
INPUTS
The ADM1062/ADM1063/ADM1064/ADM1065/ADM1066/
ADM1067/ADM1166 devices have 10 inputs. Five of these are
dedicated supply fault detectors, highly programmable reset
generators whose inputs can detect overvoltage, undervoltage,
or out-of-window faults. With these five inputs, voltages from
0.573 V to 14.4 V can be supervised. The undervoltage and
overvoltage thresholds can all be programmed to an 8-bit
resolution. The comparators used to detect faults on the inputs
have digitally programmable hysteresis to provide immunity
to supply bounce. Each of these inputs also has a glitch filter
whose timeout is programmable up to 100 μs.
The other five inputs have dual functionality. They can be
used as analog inputs, like the first five channels described
earlier in this section, or as general-purpose logic inputs. As
analog inputs, these channels function exactly the same as those
described earlier in this section. The major difference is that
these inputs do not have internal potentiometer resistors and
present a true high impedance to the input pin. Their input
range is thus limited to 0.573 V to 1.375 V, but the high
impedance means that an external resistor divide network can
be used to divide down any out-of-range supply to a value
within range. Thus, +48 V, +24 V, −5 V, and −12 V can all be
supervised by these channels with the appropriate external
resistor divide network.
As digital inputs, these pins can be used to detect enable signals
(such as PWRGD and POWRON) and are TTL and CMOS
compatible. When used in this mode, the analog circuitry of
these pins can be mapped to their sister input pins (one of the
first five inputs previously described). Thus, VX1 can be used as
a second detector on VP1, VX2 can be used with VP2, and so
on. VX5 is mapped to VH. With a second detector available, the
user can program warnings as well as fault functions.
Table 2 details all of the registers used to configure the inputs to
perform the functions described in this section.
Rev. C | Page 4 of 36
Application Note
AN-698
Table 2. Registers Used to Configure Inputs
Input
VP1
Reg.
0x00
0x01
Reg. Name
PS1OVTH
PS1OVHYST
0x02
0x03
PS1UVTH
PS1UVHYST
0x04
SFDV1CFG
0x05
VP2
SFDV1SEL
0x08
0x09
PS2OVTH
PS2OVHYST
0x0A
0x0B
PS2UVTH
PS2UVHYST
0x0C
SFDV2CFG
0x0D
SFDV2SEL
Bits
7:0
7:5
4:0
7:0
7:5
4:0
7:5
4:2
GF2 to GF0
R/W
1:0
RS1 to RS0
R/W
7:2
1:0
SEL1 to SEL0
R/W
OV7 to OV0
R/W
HY4 to HY0
UV7 to UV0
R/W
R/W
7:0
7:5
4:0
7:0
7:5
4:0
7:5
4:2
Mnemonic
OV7 to OV0
R/W
R/W
HY4 to HY0
UV7 to UV0
R/W
R/W
HY4 to HY0
HY4 to HY0
GF2 to GF0
R/W
1:0
RS1 to RS0
R/W
7:2
1:0
SEL1 to SEL0
R/W
Rev. C | Page 5 of 36
Description
8-bit digital value for the OV threshold on PS1 SFD.
Cannot be used.
5-bit hysteresis to be subtracted from PS1OVTH when OV is true.
8-bit digital value for the UV threshold on PS1 SFD.
Cannot be used.
5-bit hysteresis to be added from PS1UVTH when UV is true.
Cannot be used.
GF2
GF1
GF0
Delay (µs)
0
0
0
0
0
0
1
5
0
1
0
10
0
1
1
20
1
0
0
30
1
0
1
50
1
1
0
75
1
1
1
100
RS1
RS0
Fault Type Select
0
0
OV
0
1
UV or OV
1
0
UV
1
1
Off
Cannot be used.
SEL1
SEL0
Range Select
0
0
Midrange (2.5 V to 6 V)
0
1
Low range (1.25 V to 3 V)
1
0
Ultralow range (0.573 V to 1.375 V)
1
1
Ultralow range (0.573 V to 1.375 V)
8-bit digital value for the OV threshold on PS2 SFD.
Cannot be used.
5-bit hysteresis to be subtracted from PS2OVTH when OV is true.
8-bit digital value for the UV threshold on PS2 SFD.
Cannot be used.
5-bit hysteresis to be added from PS2UVTH when UV is true.
Cannot be used.
GF2
GF1
GF0
Delay (μs)
0
0
0
0
0
0
1
5
0
1
0
10
0
1
1
20
1
0
0
30
1
0
1
50
1
1
0
75
1
1
1
100
RS1
RS0
Fault Type Select
0
0
OV
0
1
UV or OV
1
0
UV
1
1
Off
Cannot be used.
SEL1
SEL0
Range Select
0
0
Mid range (2.5 V to 6 V)
0
1
Low range (1.25 V to 3 V)
1
0
Ultralow range (0.573 V to 1.375 V)
1
1
Ultralow range (0.573 V to 1.375 V)
AN-698
Input
VP3
Application Note
Reg.
0x10
0x11
Reg. Name
PS3OVTH
PS3OVHYST
0x12
0x13
PS3UVTH
PS3UVHYST
0x14
SFDV3CFG
0x15
VP4
SFDV3SEL
0x18
0x19
PS4OVTH
PS4OVHYST
0x1A
0x1B
PS4UVTH
PS4UVHYST
0x1C
SFDV4CFG
0x1D
SFDV4SEL
Bits
7:0
7:5
4:0
7:0
7:5
4:0
7:5
4:2
Mnemonic
OV7 to OV0
R/W
R/W
HY4 to HY0
UV7 to UV0
R/W
R/W
HY4 to HY0
GF2 to GF0
R/W
1:0
RS1 to RS0
R/W
7:2
1:0
SEL1 to SEL0
R/W
OV7 to OV0
R/W
HY4 to HY0
UV7 to UV0
R/W
R/W
7:0
7:5
4:0
7:0
7:5
4:0
7:5
4:2
HY4 to HY0
GF2 to GF0
R/W
1:0
RS1 to RS0
R/W
7:2
1:0
SEL1 to SEL0
R/W
Rev. C | Page 6 of 36
Description
8-bit digital value for the OV threshold on PS3 SFD.
Cannot be used.
5-bit hysteresis to be subtracted from PS3OVTH when OV is true.
8-bit digital value for the UV threshold on PS3 SFD.
Cannot be used.
5-bit hysteresis to be added from PS3UVTH when UV is true.
Cannot be used.
GF2
GF1
GF0
Delay (μs)
0
0
0
0
0
0
1
5
0
1
0
10
0
1
1
20
1
0
0
30
1
0
1
50
1
1
0
75
1
1
1
100
RS1
RS0
Fault Type Select
0
0
OV
0
1
UV or OV
1
0
UV
1
1
Off
Cannot be used.
SEL1
SEL0
Range Select
0
0
Midrange (2.5 V to 6 V)
0
1
Low range (1.25 V to 3 V)
1
0
Ultralow range (0.573 V to 1.375 V)
1
1
Ultralow range (0.573 V to 1.375 V)
8-bit digital value for the OV threshold on PS4 SFD.
Cannot be used.
5-bit hysteresis to be subtracted from PS4OVTH when OV is true.
8-bit digital value for the UV threshold on PS4 SFD.
Cannot be used.
5-bit hysteresis to be added from PS4UVTH when UV is true.
Cannot be used.
GF2
GF1
GF0
Delay (μs)
0
0
0
0
0
0
1
5
0
1
0
10
0
1
1
20
1
0
0
30
1
0
1
50
1
1
0
75
1
1
1
100
RS1
RS0
Fault Type Select
0
0
OV
0
1
UV or OV
1
0
UV
1
1
Off
Cannot be used.
SEL1
SEL0
Range Select
0
0
Midrange (2.5 V to 6 V)
0
1
Low range (1.25 V to 3 V)
1
0
Ultralow range (0.573 V to 1.375 V)
1
1
Ultralow range (0.573 V to 1.375 V)
Application Note
Input
VH
Reg.
0x20
0x21
Reg. Name
PSVHOVTH
PSVHOVHYST
0x22
PSVHUVTH
0x24
SFDVHCFG
0x25
VX1
SFDVHSEL
0x28
0x29
X1OVTH
X1OVHYST
0x2A
0x2B
X1UVTH
X1UVHYST
0x2C
SFDX1CFG
0x2D
0x2E
SFDVX1SEL
GPIX1CFG
AN-698
Bits
7:0
7:5
4:0
7:0
4:0
7:5
4:2
Mnemonic
OV7 to OV0
R/W
R/W
HY4 to HY0
UV7 to UV0
HY4 to HY0
R/W
R/W
GF2 to GF0
R/W
1:0
RS1 to RS0
R/W
7:1
0
SEL0
R/W
OV7 to OV0
R/W
HY4 to HY0
UV7 to UV0
R/W
R/W
7:0
7:5
4:0
7:0
7:5
4:0
7:5
4:2
HY4 to HY0
GF2 to GF0
R/W
1:0
RS1 to RS0
R/W
7:2
1:0
SEL1 to SEL0
R/W
7
6
5
INVIN
INTYP
R/W
R/W
Rev. C | Page 7 of 36
Description
8-bit digital value for the OV threshold on PSVH SFD.
Cannot be used.
5-bit hysteresis to be subtracted from PSVHOVTH when OV is true.
8-bit digital value for the UV threshold on PSVH SFD.
5-bit hysteresis to be added from PSVHUVTH when UV is true.
Cannot be used.
GF2
GF1
GF0
Delay (μs)
0
0
0
0
0
0
1
5
0
1
0
10
0
1
1
20
1
0
0
30
1
0
1
50
1
1
0
75
1
1
1
100
RS1
RS0
Fault Type Select
0
0
OV
0
1
UV or OV
1
0
UV
1
1
Off
Cannot be used.
SEL0
Range Select
0
Low range (2.5 V to 6.0 V)
1
High range (6.0 V to 14.4 V)
8-bit digital value for the OV threshold on X1 SFD.
Cannot be used.
5-bit hysteresis to be subtracted from X1OVTH when OV is true.
8-bit digital value for the UV threshold on X1 SFD.
Cannot be used.
5-bit hysteresis to be added from X1UVTH when UV is true.
Cannot be used.
GF2
GF1
GF0
Delay (μs)
0
0
0
0
0
0
1
5
0
1
0
10
0
1
1
20
1
0
0
30
1
0
1
50
1
1
0
75
1
1
1
100
RS1
RS0
Fault Type Select
0
0
OV
0
1
UV or OV
1
0
UV
1
1
Off
Cannot be used.
SEL1
SEL0
Function Select
0
0
SFD (fault) only
0
1
GPI (fault) only
1
0
GPI (fault) + SFD (warning)
No function (input can still be used as
1
1
ADC input)
Cannot be used.
If high, invert input.
Determines whether a level or an edge is detected on the pin.
INTYP
Level/Edge
0
Detect level
1
Detect edge
AN-698
Input
VX2
Application Note
Reg.
Reg. Name
0x30
0x31
X2OVTH
X2OVHYST
0x32
0x33
X2UVTH
X2UVHYST
0x34
SFDX2CFG
0x35
0x36
SFDVX2SEL
GPIX2CFG
Bits
4:3
Mnemonic
PULS1 to PULS0
R/W
R/W
2:0
GF2 to GF0
R/W
7:0
7:5
4:0
7:0
7:5
4:0
7:5
4:2
OV7 to OV0
R/W
HY4 to HY0
UV7 to UV0
R/W
R/W
HY4 to HY0
GF2 to GF0
R/W
1:0
RS1 to RS0
R/W
7:2
1:0
SEL1 to SEL0
R/W
7
6
5
INVIN
INTYP
R/W
R/W
4:3
PULS1 to PULS0
R/W
Rev. C | Page 8 of 36
Description
Length of pulse output once an edge has been detected on input.
PULS1
PULS0
Pulse Length (μs)
0
0
10
0
1
100
1
0
1000
1
1
10,000
Glitch filter. Length of time for which a pulse is ignored.
GF2
GF1
GF0
Delay (μs)
0
0
0
0
0
0
1
5
0
1
0
10
0
1
1
20
1
0
0
30
1
0
1
50
1
1
0
75
1
1
1
100
8-bit digital value for the OV threshold on X2 SFD.
Cannot be used.
5-bit hysteresis to be subtracted from X2OVTH when OV is true.
8-bit digital value for the UV threshold on X2 SFD.
Cannot be used.
5-bit hysteresis to be added from X2UVTH when UV is true.
Cannot be used.
GF2
GF1
GF0
Delay (μs)
0
0
0
0
0
0
1
5
0
1
0
10
0
1
1
20
1
0
0
30
1
0
1
50
1
1
0
75
1
1
1
100
RS1
RS0
Fault Type Select
0
0
OV
0
1
UV or OV
1
0
UV
1
1
Off
Cannot be used.
SEL1
SEL0
Function Select
0
0
SFD (fault) only
0
1
GPI (fault) only
1
0
GPI (fault) + SFD (warning)
No function (input can still be used as
1
1
ADC input)
Cannot be used.
If high, invert input.
Determines whether a level or an edge is detected on the pin.
INTYP
Level/Edge
0
Detect level
1
Detect edge
Length of pulse output once an edge has been detected on input.
PULS1
PULS0
Pulse Length (μs)
0
0
10
0
1
100
1
0
1000
1
1
10,000
Application Note
AN-698
Input
Reg.
Reg. Name
Bits
2:0
Mnemonic
GF2 to GF0
R/W
R/W
VX3
0x38
0x39
X3OVTH
X3OVHYST
OV7 to OV0
R/W
0x3A
0x3B
X3UVTH
X3UVHYST 7
HY4 to HY0
UV7 to UV0
R/W
R/W
0x3C
SFDX3CFG
7:0
7:5
4:0
7:0
7:5
4:0
7:5
4:2
GF2 to GF0
R/W
1:0
RS1 to RS0
R/W
7:2
1:0
SEL1 to SEL0
R/W
7
6
5
INVIN
INTYP
R/W
R/W
4:3
PULS1 to PULS0
R/W
2:0
GF2 to GF0
R/W
0x3D
0x3E
SFDVX3SEL
GPIX3CFG
HY4 to HY0
Rev. C | Page 9 of 36
Description
Glitch filter. Length of time for which a pulse is ignored.
GF2
GF1
GF0
Delay (μs)
0
0
0
0
0
0
1
5
0
1
0
10
0
1
1
20
1
0
0
30
1
0
1
50
1
1
0
75
1
1
1
100
8-bit digital value for the OV threshold on X3 SFD.
Cannot be used.
5-bit hysteresis to be subtracted from X3OVTH when OV is true.
8-bit digital value for the UV threshold on X3 SFD.
Cannot be used.
5-bit hysteresis to be added from X3UVTH when UV is true.
Cannot be used.
GF2
GF1
GF0
Delay (µs)
0
0
0
0
0
0
1
5
0
1
0
10
0
1
1
20
1
0
0
30
1
0
1
50
1
1
0
75
1
1
1
100
RS1
RS0
Fault Type Select
0
0
OV
0
1
UV or OV
1
0
UV
1
1
Off
Cannot be used.
SEL1
SEL0
Function Select
0
0
SFD (fault) only
0
1
GPI (fault) only
1
0
GPI (fault) + SFD (warning)
Cannot be used.
If high, invert input.
Determines whether a level or an edge is detected on the pin.
INTYP Level/Edge
0
Detect level
1
Detect edge
Length of pulse output once an edge has been detected on input.
PULS1
PULS0
Pulse Length (μs)
0
0
10
0
1
100
1
0
1000
1
1
10000
Glitch filter. Length of time for which a pulse is ignored.
GF2
GF1
GF0
Delay (μs)
0
0
0
0
0
0
1
5
0
1
0
10
0
1
1
20
1
0
0
30
1
0
1
50
1
1
0
75
1
1
1
100
AN-698
Input
VX4
Application Note
Reg.
0x40
0x41
Reg. Name
X4OVTH
X4OVHYST
0x42
0x43
X4UVTH
X4UVHYST
0x44
SFDX4CFG
0x45
0x46
SFDVX4SEL
GPIX4CFG
Bits
7:0
7:5
4:0
7:0
7:5
4:0
7:5
4:2
Mnemonic
OV7 to OVO
R/W
R/W
HY4 to HY0
UV7 to UV0
R/W
R/W
HY4 to HY0
GF2 to GF0
R/W
1:0
RS1 to RS0
R/W
7:2
1:0
SEL1 to SEL0
R/W
7
6
5
INVIN
INTYP
R/W
R/W
4:3
PULS1 to PULS0
R/W
2:0
GF2–GF0
R/W
Rev. C | Page 10 of 36
Description
8-bit digital value for the OV threshold on X4 SFD.
Cannot be used.
5-bit hysteresis to be subtracted from X4OVTH when OV is true.
8-bit digital value for the UV threshold on X4 SFD.
Cannot be used.
5-bit hysteresis to be added from X4UVTH when UV is true.
Cannot be used.
GF2
GF1
GF0
Delay (μs)
0
0
0
0
0
0
1
5
0
1
0
10
0
1
1
20
1
0
0
30
1
0
1
50
1
1
0
75
1
1
1
100
RS1
RS0
Fault Type Select
0
0
OV
0
1
UV or OV
1
0
UV
1
1
Off
Cannot be used.
SEL1
SEL0
Function Select
0
0
SFD (fault) only
0
1
GPI (fault) only
1
0
GPI (fault) + SFD (warning)
No function (input can still be used as
1
1
ADC input)
Cannot be used.
If high, invert input.
Determines whether a level or an edge is detected on the pin.
INTYP Level/Edge
0
Detect level
1
Detect edge
Length of pulse output once an edge has been detected on input.
PULS1
PULS0
Pulse Length (μs)
0
0
0
0
1
100
1
0
1000
1
1
10000
Glitch filter. Length of time for which a pulse is ignored.
GF2
GF1
GF0
Delay (μs)
0
0
0
0
0
0
1
5
0
1
0
10
0
1
1
20
1
0
0
30
1
0
1
50
1
1
0
75
1
1
1
100
Application Note
Input
VX5
Reg.
0x48
0x49
Reg. Name
X5OVTH
5OVHYST
0x4A
0x4B
X5UVTH
X5UVHYST
0x4C
SFDX5CFG
0x4D
0x4E
SFDVX5SEL
GPIX5CFG
AN-698
Bits
7:0
7:5
4:0
7:0
7:5
4:0
7:5
4:2
Mnemonic
OV7 to OV0
R/W
R/W
HY4 to HY0
UV7 to UV0
R/W
R/W
HY4 to HY0
GF2 to GF0
R/W
1:0
RS1 to RS0
R/W
7:2
1:0
SEL1 to SEL0
R/W
7
6
5
INVIN
INTYP
R/W
R/W
4:3
PULS1 to PULS0
R/W
2:0
GF2 to GF0
R/W
Rev. C | Page 11 of 36
Description
8-bit digital value for the OV threshold on X5 SFD.
Cannot be used.
5-bit hysteresis to be subtracted from X5OVTH when OV is true.
8-bit digital value for the UV threshold on X5 SFD.
Cannot be used.
5-bit hysteresis to be added from X5UVTH when UV is true.
Cannot be used.
GF2
GF1
GF0
Delay (μs)
0
0
0
0
0
0
1
5
0
1
0
10
0
1
1
20
1
0
0
30
1
0
1
50
1
1
0
75
1
1
1
100
RS1
RS0
Fault Type Select
0
0
OV
0
1
UV or OV
1
0
UV
1
1
Off
Cannot be used.
SEL1
SEL0
Function Select
0
0
SFD (fault) only
0
1
GPI (fault) only
1
0
GPI (fault) + SFD (warning)
No function (input can still be used as
1
1
ADC input)
Cannot be used.
If high, invert input.
Determines whether a level or an edge is detected on the pin.
INTYP Level/Edge
0
Detect level
1
Detect edge
Length of pulse output once an edge has been detected on input.
PULS1
PULS0
Pulse Length (μs)
0
0
0
0
1
100
1
0
1000
1
1
10000
Glitch filter. Length of time for which a pulse is ignored.
GF2
GF1
GF0
Delay (μs)
0
0
0
0
0
0
1
5
0
1
0
10
0
1
1
20
1
0
0
30
1
0
1
50
1
1
0
75
1
1
1
100
AN-698
Application Note
OUTPUTS
The ADM1062/ADM1063/ADM1064/ADM1065/ADM1066/
ADM1067/ADM1166 devices have 10 programmable driver
outputs. Supply sequencing is achieved with the devices by
using the PDOx pins as control signals for supplies. The output
drivers can be used either as logic enables or FET drivers.
The PDOx pins can be used for a number of functions; the
primary function is to provide enable signals for LDOs or dcto-dc converters, which generate supplies locally on a board.
The PDOx can also be used to provide a POWER_GOOD
signal when all of the SFDs are in tolerance or to provide a reset
output if one of the SFDs goes out of spec (this can be used as a
status signal for a DSP, FPGA, or other microcontroller).
The PDOs can be programmed to pull up to a number of
different options. The outputs can be programmed as
•
•
•
•
•
•
•
Open drain (allowing the user to connect an external pullup resistor)
Open drain, with weak pull-up to VDDCAP
Push-pull to VDDCAP
Open drain, with weak pull-up to VPx
Push-pull to VPx
Strong pull-down to GND
Internally charge-pumped high drive (12 V, PDO1 to PDO6)
The last option (available only on PDO1 to PDO6) allows the
user to directly drive a voltage high enough to fully enhance an
external N-FET, which is used to isolate, for example, a cardside voltage from a backplane supply (a PDO sustains greater
than 10.5 V into a 1 μA load). The pull-down switches can be
used to drive status LEDs.
The data driving each of the PDOx can come from one of three
sources. The source can be enabled for a particular output, that
is, PDO1, in the PDOCFG configuration register. The data
sources are
•
•
•
An output from the SE.
Directly from the SMBus. A PDO can be configured so
that the SMBus has direct control over it. This enables
software control of the PDOs. Thus, a microcontroller can
be used to initiate a software power-up/power-down
sequence.
An on-chip clock. A 100 kHz clock is generated on the
device. This clock can be made available on any of the
PDOs. It could be used to clock an external device such as
an LED, for example.
Table 3 details all of the registers used to configure the outputs
to perform the functions described in this section.
Rev. C | Page 12 of 36
Application Note
AN-698
Table 3. Registers Used to Configure Outputs
Output
PDO1
PDO2
PDO3
Reg.
0x07
0x0F
0x17
Reg. Name
PDO1CFG
PDO2CFG
PDO3CFG
Bits
7
6:4
Mnemonic
R/W
CFG6 to CFG4
R/W
3:0
CFG3 to CFG0
R/W
7
6:4
CFG6 to CFG4
R/W
3:0
CFG3 to CFG0
R/W
7
6:4
CFG6 to CFG4
R/W
Description
Cannot be used.
Controls the logic source driving the PDO, that is, the SE, the internal clock, or the
SMBus, directly.
CFG6
CFG5
CFG4
PDO Status
0
0
0
Disabled, with weak pull-down
0
0
1
Enabled, follows the logic driven by the SE
0
1
0
Enables SMBus data, drive low
0
1
1
Enables SMBus data, drive high
1
X
X
Enables 100 kHz clock out onto pin
Determines the format of the pull-up on the PDO.
CFG3
CFG2
CFG1
CFG0
PDO Pull-Up
0
0
0
X
None
0
0
1
X
Pull-up to 12 V charge pump voltage
0
1
0
0
Weak open-drain pull-up to VP1
0
1
0
1
Push-pull pull-up to VP1
0
1
1
0
Weak open-drain pull-up to VP2
0
1
1
1
Push-pull pull-up to VP2
1
0
0
0
Weak open-drain pull-up to VP3
1
0
0
1
Push-pull pull-up to VP3
1
0
1
0
Weak open-drain pull-up to VP4
1
0
1
1
Push-pull pull-up to VP4
1
1
1
0
Weak open-drain pull-up to VDDCAP
1
1
1
1
Push-pull pull-up to VDDCAP
Cannot be used.
Controls the logic source driving the PDO, that is, the SE, the internal clock, or the
SMBus, directly.
CFG6
CFG5
CFG4
PDO Status
0
0
0
Disabled, with weak pull-down
0
0
1
Enabled, follows the logic driven by the SE
0
1
0
Enables SMBus data, drive low
0
1
1
Enables SMBus data, drive high
1
X
X
Enables 100 kHz clock out onto pin
Determines the format of the pull-up on the PDO.
CFG3
CFG2
CFG1
CFG0
PDO Pull-Up
0
0
0
X
None
0
0
1
X
Pull-up to 12 V charge pump voltage
0
1
0
0
Weak open-drain pull-up to VP1
0
1
0
1
Push-pull pull-up to VP1
0
1
1
0
Weak open-drain pull-up to VP2
0
1
1
1
Push-pull pull-up to VP2
1
0
0
0
Weak open-drain pull-up to VP3
1
0
0
1
Push-pull pull-up to VP3
1
0
1
0
Weak open-drain pull-up to VP4
1
0
1
1
Push-pull pull-up to VP4
1
1
1
0
Weak open-drain pull-up to VDDCAP
1
1
1
1
Push-pull pull-up to VDDCAP
Cannot be used.
Controls the logic source driving the PDO, that is, the SE, the internal clock, or the
SMBus, directly.
CFG6
CFG5
CFG4
PDO Status
0
0
0
Disabled, with weak pull-down
0
0
1
Enabled, follows the logic driven by the SE
0
1
0
Enables SMBus data, drive low
0
1
1
Enables SMBus data, drive high
1
X
X
Enables 100 kHz clock out onto pin
Rev. C | Page 13 of 36
AN-698
Application Note
Output
Reg.
Reg. Name
Bits
3:0
Mnemonic
CFG3 to CFG0
R/W
R/W
PDO4
0x1F
PDO4CFG
7
6:4
CFG6 to CFG4
R/W
3:0
CFG3 to CFG0
R/W
7
6:4
CFG6 to CFG4
R/W
3:0
CFG3 to CFG0
R/W
PDO5
0x27
PDO5CFG
Description
Determines the format of the pull-up on the PDO.
CFG3
CFG2
CFG1
CFG0
PDO Pull-Up
0
0
0
X
None
0
0
1
X
Pull-up to 12 V charge pump voltage
0
1
0
0
Weak open-drain pull-up to VP1
0
1
0
1
Push-pull pull-up to VP1
0
1
1
0
Weak open-drain pull-up to VP2
0
1
1
1
Push-pull pull-up to VP2
1
0
0
0
Weak open-drain pull-up to VP3
1
0
0
1
Push-pull pull-up to VP3
1
0
1
0
Weak open-drain pull-up to VP4
1
0
1
1
Push-pull pull-up to VP4
1
1
1
0
Weak open-drain pull-up to VDDCAP
1
1
1
1
Push-pull pull-up to VDDCAP
Cannot be used.
Controls the logic source driving the PDO, that is, the SE, the internal clock, or the
SMBus, directly.
CFG6
CFG5
CFG4
PDO Status
0
0
0
Disabled, with weak pull-down
0
0
1
Enabled, follows the logic driven by the SE
0
1
0
Enables SMBus data, drive low
0
1
1
Enables SMBus data, drive high
1
X
X
Enables 100 kHz clock out onto pin
Determines the format of the pull-up on the PDO.
CFG3
CFG2
CFG1
CFG0
PDO Pull-Up
0
0
0
X
None
0
0
1
X
Pull-up to 12 V charge pump voltage
0
1
0
0
Weak open-drain pull-up to VP1
0
1
0
1
Push-pull pull-up to VP1
0
1
1
0
Weak open-drain pull-up to VP2
0
1
1
1
Push-pull pull-up to VP2
1
0
0
0
Weak open-drain pull-up to VP3
1
0
0
1
Push-pull pull-up to VP3
1
0
1
0
Weak open-drain pull-up to VP4
1
0
1
1
Push-pull pull-up to VP4
1
1
1
0
Weak open-drain pull-up to VDDCAP
Cannot be used.
Controls the logic source driving the PDO, that is, the SE, the internal clock, or the
SMBus, directly.
CFG6
CFG5
CFG4
PDO Status
0
0
0
Disabled, with weak pull-down
0
0
1
Enabled, follows the logic driven by the SE
0
1
0
Enables SMBus data, drive low
0
1
1
Enables SMBus data, drive high
1
X
X
Enables 100 kHz clock out onto pin
Determines the format of the pull-up on the PDO.
CFG3
CFG2
CFG1
CFG0
PDO Pull-Up
0
0
0
X
None
0
0
1
X
Pull-up to 12 V charge pump voltage
0
1
0
0
Weak open-drain pull-up to VP1
0
1
0
1
Push-pull pull-up to VP1
0
1
1
0
Weak open-drain pull-up to VP2
0
1
1
1
Push-pull pull-up to VP2
1
0
0
0
Weak open-drain pull-up to VP3
1
0
0
1
Push-pull pull-up to VP3
1
0
1
0
Weak open-drain pull-up to VP4
1
0
1
1
Push-pull pull-up to VP4
1
1
1
0
Weak open-drain pull-up to VDDCAP
Rev. C | Page 14 of 36
Application Note
Output
PDO6
PDO7
PDO8
Reg.
0x2F
0x37
0x3F
Reg. Name
PDO6CFG
PDO7CFG
PDO8CFG
AN-698
Bits
7
6:4
Mnemonic
R/W
CFG6 to CFG4
R/W
3:0
CFG3 to CFG0
R/W
7
6:4
CFG6 to CFG4
R/W
3:0
CFG3 to CFG0
R/W
7
6:4
CFG6 to CFG4
R/W
Description
Cannot be used.
Controls the logic source driving the PDO, that is, the SE, the internal clock, or the
SMBus, directly.
CFG6
CFG5
CFG4
PDO Status
0
0
0
Disabled, with weak pull-down
0
0
1
Enabled, follows the logic driven by the SE
0
1
0
Enables SMBus data, drive low
0
1
1
Enables SMBus data, drive high
1
X
X
Enables 100 kHz clock out onto pin
Determines the format of the pull-up on the PDO.
CFG3
CFG2
CFG1
CFG0
PDO Pull-Up
0
0
0
X
None
0
0
1
X
Pull-up to 12 V charge pump voltage
0
1
0
0
Weak open-drain pull-up to VP1
0
1
0
1
Push-pull pull-up to VP1
0
1
1
0
Weak open-drain pull-up to VP2
0
1
1
1
Push-pull pull-up to VP2
1
0
0
0
Weak open-drain pull-up to VP3
1
0
0
1
Push-pull pull-up to VP3
1
0
1
0
Weak open-drain pull-up to VP4
1
0
1
1
Push-pull pull-up to VP4
1
1
1
0
Weak open-drain pull-up to VDDCAP
1
1
1
1
Push-pull pull-up to VDDCAP
Cannot be used.
Controls the logic source driving the PDO, that is, the SE, the internal clock, or the
SMBus, directly.
CFG6
CFG5
CFG4
PDO Status
0
0
0
Disabled, with weak pull-down
0
0
1
Enabled, follows the logic driven by the SE
0
1
0
Enables SMBus data, drive low
0
1
1
Enables SMBus data, drive high
1
X
X
Enables 100 kHz clock out onto pin
Determines the format of the pull-up on the PDO.
CFG3
CFG2
CFG1
CFG0
PDO Pull-Up
0
0
0
X
None
0
0
1
X
Do not use
0
1
0
0
Weak open-drain pull-up to VP1
0
1
0
1
Push-pull pull-up to VP1
0
1
1
0
Weak open-drain pull-up to VP2
0
1
1
1
Push-pull pull-up to VP2
1
0
0
0
Weak open-drain pull-up to VP3
1
0
0
1
Push-pull pull-up to VP3
1
0
1
0
Weak open-drain pull-up to VP4
1
0
1
1
Push-pull pull-up to VP4
1
1
1
0
Weak open-drain pull-up to VDDCAP
1
1
1
1
Push-pull pull-up to VDDCAP
Cannot be used.
Controls the logic source driving the PDO, that is, the SE, the internal clock, or the
SMBus, directly.
CFG6
CFG5
CFG4
PDO Status
0
0
0
Disabled, with weak pull-down
0
0
1
Enabled, follows the logic driven by the SE
0
1
0
Enables SMBus data, drive low
0
1
1
Enables SMBus data, drive high
1
X
X
Enables 100 kHz clock out onto pin
Rev. C | Page 15 of 36
AN-698
Application Note
Output
Reg.
Reg. Name
Bits
3:0
Mnemonic
CFG3 to CFG0
R/W
R/W
PDO9
0x47
PDO9CFG
7
6:4
CFG6 to CFG4
R/W
3:0
CFG3 to CFG0
R/W
7
6:4
CFG6 to CFG4
R/W
PDO10
0x4F
PDO10CFG
Description
Determines the format of the pull-up on the PDO.
CFG3
CFG2
CFG1
CFG0
PDO Pull-Up
0
0
0
X
None
0
0
1
X
Do not use
0
1
0
0
Weak open-drain pull-up to VP1
0
1
0
1
Push-pull pull-up to VP1
0
1
1
0
Weak open-drain pull-up to VP2
0
1
1
1
Push-pull pull-up to VP2
1
0
0
0
Weak open-drain pull-up to VP3
1
0
0
1
Push-pull pull-up to VP3
1
0
1
0
Weak open-drain pull-up to VP4
1
0
1
1
Push-pull pull-up to VP4
1
1
1
0
Weak open-drain pull-up to VDDCAP
1
1
1
1
Push-pull pull-up to VDDCAP
Cannot be used.
Controls the logic source driving the PDO, that is, the SE, the internal clock, or the
SMBus, directly.
CFG6
CFG5
CFG4
PDO Status
0
0
0
Disabled, with weak pull-down
0
0
1
Enabled, follows the logic driven by the SE
0
1
0
Enables SMBus data, drive low
0
1
1
Enables SMBus data, drive high
1
X
X
Enables 100 kHz clock out onto pin
Determines the format of the pull-up on the PDO.
CFG3
CFG2
CFG1
CFG0
PDO Pull-Up
0
0
0
X
None
0
0
1
X
Do not use
0
1
0
0
Weak open-drain pull-up to VP1
0
1
0
1
Push-pull pull-up to VP1
0
1
1
0
Weak open-drain pull-up to VP2
0
1
1
1
Push-pull pull-up to VP2
1
0
0
0
Weak open-drain pull-up to VP3
1
0
0
1
Push-pull pull-up to VP3
1
0
1
0
Weak open-drain pull-up to VP4
1
0
1
1
Push-pull pull-up to VP4
1
1
1
0
Weak open-drain pull-up to VDDCAP
1
1
1
1
Push-pull pull-up to VDDCAP
Cannot be used.
Controls the logic source driving the PDO, that is, the SE, the internal clock, or the
SMBus, directly.
CFG6
CFG5
CFG4
PDO Status
0
0
0
Disabled, with weak pull-down
0
0
1
Enabled, follows the logic driven by the SE
0
1
0
Enables SMBus data, drive low
0
1
1
Enables SMBus data, drive high
1
X
X
Enables 100 kHz clock out onto pin
Rev. C | Page 16 of 36
Application Note
Output
Reg.
Reg. Name
AN-698
Bits
3:0
Mnemonic
CFG3 to CFG0
R/W
R/W
Description
Determines the format of the pull-up on the PDO.
CFG3
CFG2
CFG1
CFG0
0
0
0
X
0
0
1
X
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
1
0
1
1
1
1
Rev. C | Page 17 of 36
PDO Pull-Up
None
Do not use
Weak open-drain pull-up to VP1
Push-pull pull-up to VP1
Weak open-drain pull-up to VP2
Push-pull pull-up to VP2
Weak open-drain pull-up to VP3
Push-pull pull-up to VP3
Weak open-drain pull-up to VP4
Push-pull pull-up to VP4
Weak open-drain pull-up to VDDCAP
Push-pull pull-up to VDDCAP
AN-698
Application Note
SEQUENCING ENGINE
Considering the function of the SE from an applications
viewpoint, it is best to think of the SE as providing a state for a
state machine. This state has the following attributes:
•
•
•
It is used to monitor signals indicating the status of the 10
input pins, VP1 to VP4, VH, and VX1 to VX5.
It can be entered from any other state.
There are three exit routes that move the state machine to
the next state: end-of-step detection, monitoring fault, and
timeout.
•
•
•
Delay timers for the end-of-step and timeout blocks can be
programmed independently and change with each state
change. The range of timeouts is from 0 ms to 400 ms.
The output condition of the 10 PDO pins is defined and
fixed within a state.
The transition from one state to the next is made in less
than 20 μs, the time taken to download a state definition
from EEPROM to the SE.
STATE
MONITOR
FAULT
TIMEOUT
END-OF-STEP
04615-006
The ADM1062/ADM1063/ADM1064/ADM1065/
ADM1066/ADM1067/ADM1166 incorporate a sequencing
engine (SE) that provides the user with powerful and flexible
control of sequencing. The SE implements state machine
control of the PDO outputs, with state changes conditional
on input events. SE programs can enable complex control of
boards, such as power-up and power-down sequence control,
fault event handling, and interrupt generation on warnings.
A watchdog function to verify the continued operation of a
processor clock can be integrated into the SE program. The
SE can also be controlled via the SMBus, giving software or
firmware control of the board sequencing.
Figure 3. State Cell
The ADM1062/ADM1063/ADM1064/ADM1065/ADM1066/
ADM1067/ADM1166 offer up to 63 such state definitions. Each
state is defined by a 64-bit word.
Table 4 shows the details of the 64 bits that define a state. Table 8
details how to communicate with the SE in the ADM1062/
ADM1063/ADM1064/ADM1065/ADM1066/ADM1067/
ADM1166. Table 9 provides details of additional sequence
engine control registers present in the ADM1166 that allow
the sequence engine to be restarted.
Rev. C | Page 18 of 36
Application Note
AN-698
Table 4. Starting Address for Each State in SE
State
Reserved State
State 1
State 2
State 3
State 4
State 5
State 6
State 7
State 8
State 9
State 10
State 11
State 12
State 13
State 14
State 15
State 16
State 17
State 18
State 19
State 20
State 21
State 22
State 23
State 24
State 25
State 26
State 27
State 28
State 29
State 30
State 31
Start Address
FA00
FA08
FA10
FA18
FA20
FA28
FA30
FA38
FA40
FA48
FA50
FA58
FA60
FA68
FA70
FA78
FA80
FA88
FA90
FA98
FAA0
FAA8
FAB0
FAB8
FAC0
FAC8
FAD0
FAD8
FAE0
FAE8
FAF0
FAF8
State
State 32
State 33
State 34
State 35
State 36
State 37
State 38
State 39
State 40
State 41
State 42
State 43
State 44
State 45
State 46
State 47
State 48
State 49
State 50
State 51
State 52
State 53
State 54
State 55
State 56
State 57
State 58
State 59
State 60
State 61
State 62
State 63
Rev. C | Page 19 of 36
Start Address
FB00
FB08
FB10
FB18
FB20
FB28
FB30
FB38
FB40
FB48
FB50
FB58
FB60
FB68
FB70
FB78
FB80
FB88
FB90
FB98
FBA0
FBA8
FBB0
FBB8
FBC0
FBC8
FBD0
FBD8
FBE0
FBE8
FBF0
FBF8
AN-698
Application Note
Table 5. Bitmap for Definition of Each State in SE
Bit No.
0
1
2
3
4
5
6
7
8
9
10
Operation, or If Set to 0
PDO1 output data
PDO2 output data
PDO3 output data
PDO4 output data
PDO5 output data
PDO6 output data
PDO7 output data
PDO8 output data
PDO9 output data
PDO10 output data
Monitor fault if VP1 = 0
If Set to 1
Description
Monitor fault if VP1 = 1
11
12
Mask VP1 monitoring
Monitor fault if VP2 = 0
Unmask VP1 monitoring
Monitor fault if VP2 = 1
13
14
Mask VP2 monitoring
Monitor Fault if VP3 = 0
Unmask VP2 monitoring
Monitor fault if VP3 = 1
15
16
Mask VP3 monitoring
Monitor fault if VP4 = 0
Unmask VP3 monitoring
Monitor fault if VP4 = 1
17
18
Mask VP4 monitoring
Monitor fault if VH = 0
Unmask VP4 monitoring
Monitor fault if VH = 1
19
20
Mask VH monitoring
Monitor fault if VX1 = 0
Unmask VH monitoring
Monitor fault if VX1 = 1
21
22
Mask VX1 monitoring
Monitor fault if VX2 = 0
Unmask VX1 monitoring
Monitor fault if VX2 = 1
23
24
Mask VX2 monitoring
Monitor fault if VX3 = 0
Unmask VX2 monitoring
Monitor fault if VX3 = 1
25
26
Mask VX3 monitoring
Monitor fault if VX4 = 0
Unmask VX3 monitoring
Monitor fault if VX4 = 1
27
28
Mask VX4 monitoring
Monitor fault if VX5 = 0
Unmask VX4 monitoring
Monitor fault if VX5 = 1
29
30
31
32
33
34
35
36
37
38
39
Mask VX5 monitoring
Mask WARNING monitoring
TIMEOUT<0>
TIMEOUT<1>
TIMEOUT<2>
TIMEOUT<3>
SEQCOND<0>
SEQCOND<1>
SEQCOND<2>
SEQCOND<3>
Sequence on selected
input = high
SEQDELAY<0>
SEQDELAY<1>
SEQDELAY<2>
Unmask VX5 monitoring
Unmask WARNING monitoring
Monitoring of faults on VP1 must be unmasked for this
function to execute (next bit).
Bit 11 = 1; turns on monitoring on the VP1 channel.
Monitoring of faults on VP2 must be unmasked for this
function to execute (next bit).
Bit 13 = 1; turns on monitoring on the VP2 channel.
Monitoring of faults on VP3 must be unmasked for this
function to execute (next bit).
Bit 15 = 1; turns on monitoring on the VP3 channel.
Monitoring of faults on VP4 must be unmasked for this
function to execute (next bit).
Bit 17 = 1; turns on monitoring on the VP4 channel.
Monitoring of faults on VH must be unmasked for this
function to execute (next bit).
Bit 19 = 1; turns on monitoring on the VH channel.
Monitoring of faults on VX1 must be unmasked for this
function to execute (next bit).
Bit 21 = 1; turns on monitoring on the VX1 channel.
Monitoring of faults on VX2 must be unmasked for this
function to execute (next bit).
Bit 23 = 1; turns on monitoring on the VX2 channel.
Monitoring of faults on VX3 must be unmasked for this
function to execute (next bit).
Bit 25 = 1; turns on monitoring on the VX3 channel.
Monitoring of faults on VX4 must be unmasked for this
function to execute (next bit).
Bit 27 = 1; turns on monitoring on the VX4 channel.
Monitoring of faults on VX5 must be unmasked for this
function to execute (next bit).
Bit 29 = 1; turns on monitoring on the VX5 channel.
Can only generate a monitor fault on WARNING = 1. Is unmasked.
Timeout length (see Table 6).
40
41
42
Sequence condition (see Table 6).
Sequence on selected
input = low
SEQSENSE
Sequence delay (see Table 6).
Rev. C | Page 20 of 36
Application Note
Bit No.
43
44
Operation, or If Set to 0
SEQDELAY<3>
MONADDR<0>
45
46
47
48
49
50
MONADDR<1>
MONADDR<2>
MONADDR<3>
MONADDR<4>
MONADDR<5>
TIMADDR<0>
51
52
53
54
55
56
TIMADDR<1>
TIMADDR<2>
TIMADDR<3>
TIMADDR<4>
TIMADDR<5>
SEQADDR<0>
57
58
59
60
61
62
63
SEQADDR<1>
SEQADDR<2>
SEQADDR<3>
SEQADDR<4>
SEQADDR<5>
Round robin disable
Fault latch closed
AN-698
If Set to 1
Description
MONADDR<5:0> is the state number to jump to if a monitor
function fault occurs.
TIMADDR<5:0> is the state number to jump to if a timeout
fault occurs.
SEQADDR<5:0> is the state number to jump to if a sequence
fault occurs.
Round robin enable
Fault latch open
This is OR’ed with enable (Address 0x82[1]).
Table 6. Timeouts and Delays for Functions in the SE
TIMEOUT<3:0>
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SEQDELAY<3:0>Delay (ms)
Cannot be used
0.1
0.2
0.4
0.7
1
2
4
7
10
20
40
70
100
200
400
Rev. C | Page 21 of 36
AN-698
Application Note
Table 7. SEQCOND and Sequence on Signal From in the SE
SEQCOND<3:0>
0
Sequence On Signal From
Never sequence; set SEQSENSE = 0 always to ensure no sequence
(Bit 39).
VP1.
VP2.
VP3.
VP4.
VH.
VX1.
VX2.
VX3.
VX4.
VX5.
WARNING.
SMBus jump. Wait for the SMBus command before jumping to the
next state. Set SEQSENSE = 0 to ensure proper operation.
1
2
3
4
5
6
7
8
9
10
11
12
Table 8. Communicating with the SE
Reg.
0x93
0xE9
Reg. Name
SECTRL
SEADDR
Bits
7:3
2
Mnemonic
N/A
SMBus
jump
R/W
1
SWSTEP
R/W
0
Halt
R/W
7:6
5:0
N/A
ADDR
R
W
Description
Cannot be used.
Allows software control of SE state changes. Can force an unconditional jump to the
next state. The bit can be set as the condition for an end-of-step change. This enables
the user to clear external interrupts by moving forward a state. The bit self-clears to 0
after the state change has occurred.
Step the SE forward to the next state. Use in conjunction with the halt bit to step
through a sequence. Can be used as a tool for debugging sequences.
Halt the SE. State changes will not happen. Must be set to allow read, erase, or write
access to the SE EEPROM.
SE current state used in conjunction with the halt bit (Address 0x93[0]).
Table 9. Additional ADM1166 Sequence Engine Control Registers
Reg.
0xDA
Reg. Name
UNLOCKSE
Bits
7:0
Mnemonic
Unlock Key
R/W
W
0xDB
SEDOWNLD
7:1
0
N/A
Restart
W
Description
Writing 0x27 and then 0x10 to this register in consecutive writes unlocks the
SEDOWNLD register so that it can be written to. To reset the lock, write 0x00 into the
unlock key. Writing to SEDOWNLD does not reset the lock.
Cannot be used.
1 causes the sequence engine to restart from the reserved state.
Rev. C | Page 22 of 36
Application Note
AN-698
CONFIGURING SEQUENCE ENGINE STATES TO
WRITE INTO THE BLACK BOX EEPROM ON THE
ADM1166
EEPROM when the sequence engine enters a state that has its
corresponding BBWRTRGx bit set to 1.
The ADM1166 can use a section of EEPROM to store fault
records when the sequence engine enters a user defined trigger
state. These states are defined in EEPROM and downloaded to
registers along with the other configuration data when the
ADM1166 is being initialized. The register locations of the
black box write triggers are shown in Table 10. These are loaded
from the same locations in the 0xF8xx EEPROM block. The
BBWRTRGx registers are read/write and, therefore, can be
modified by software if required after the download.
When the black box is enabled, all access to the configuration,
user, and black box EEPROM sections is inhibited unless the
BBCTRL.HALT bit is written to 1 to stop the black box.
When an ADM1166 powers up, the black box automatically
searches the black box section of EEPROM to find the first
unused location for the next fault record to be written. After
this section of EEPROM is erased, the black box may be
instructed to perform this search again so that it uses the
correct location for the next fault record write. The
BBSEARCH.RESET bit is used to initiate this action.
When one or more of the bits in the BBWRTRx registers are set
to 1, the black box is enabled, and fault records are written into
Table 10. ADM1166 Bitmap for Definition of Black Box Write Triggers for Each SE State 1
Reg.
0x94
Reg. Name
BBWRTRG1
0x95
BBWRTRG2
0x96
BBWRTRG3
0x97
BBWRTRG4
0x98
BBWRTRG5
Bits
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
Mnemonic
STATE7
STATE6
STATE5
STATE4
STATE3
STATE2
STATE1
Reserved
STATE15
STATE14
STATE13
STATE12
STATE11
STATE10
STATE9
STATE8
STATE23
STATE22
STATE21
STATE20
STATE19
STATE18
STATE17
STATE16
STATE31
STATE30
STATE29
STATE28
STATE27
STATE26
STATE25
STATE24
STATE39
STATE38
STATE37
STATE36
STATE35
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
State 7 write trigger.
State 6 write trigger.
State 5 write trigger.
State 4 write trigger.
State 3 write trigger.
State 2 write trigger.
State 1 write trigger.
Reserved state black box trigger; must always be set to 0.
State 15 write trigger.
State 14 write trigger.
State 13 write trigger.
State 12 write trigger.
State 11 write trigger.
State 10 write trigger.
State 9 write trigger.
State 8 write trigger.
State 23 write trigger.
State 22 write trigger.
State 21 write trigger.
State 20 write trigger.
State 19 write trigger.
State 18 write trigger.
State 17 write trigger.
State 16 write trigger.
State 31 write trigger.
State 30 write trigger.
State 29 write trigger.
State 28 write trigger.
State 27 write trigger.
State 26 write trigger.
State 25 write trigger.
State 24 write trigger.
State 39 write trigger.
State 38 write trigger.
State 37 write trigger.
State 36 write trigger.
State 35 write trigger.
Rev. C | Page 23 of 36
AN-698
Reg.
Reg. Name
0x99
BBWRTRG6
0x9A
BBWRTRG7
0x9B
BBWRTRG8
1
Application Note
Bits
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Mnemonic
STATE34
STATE33
STATE32
STATE47
STATE46
STATE45
STATE44
STATE43
STATE42
STATE41
STATE40
STATE55
STATE54
STATE53
STATE52
STATE51
STATE50
STATE49
STATE48
STATE63
STATE62
STATE61
STATE60
STATE59
STATE58
STATE57
STATE56
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
State 34 write trigger.
State 33 write trigger.
State 32 write trigger.
State 47 write trigger.
State 46 write trigger.
State 45 write trigger.
State 44 write trigger.
State 43 write trigger.
State 42 write trigger.
State 41 write trigger.
State 40 write trigger.
State 55 write trigger.
State 54 write trigger.
State 53 write trigger.
State 52 write trigger.
State 51 write trigger.
State 50 write trigger.
State 49 write trigger.
State 48 write trigger.
State 63 write trigger.
State 62 write trigger.
State 61 write trigger.
State 60 write trigger.
State 59 write trigger.
State 58 write trigger.
State 57 write trigger.
State 56 write trigger.
When the trigger bit for a given state is set to 1, a fault record is written into the next free location in the black box section of EEPROM when the sequence engine
enters that state. When the trigger bit is set to 0, no fault record is written.
Table 11. ADM1166 Black Box Control Registers
Reg.
0x9C
0XD9
Reg. Name
BBCTRL
BBSEARCH
Bits
7:1
0
Mnemonic
N/A
HALT
7:1
0
N/A
RESET
R/W
R/W
R
Description
Cannot be used.
The black box function is enabled when one or more of the BBWRTRGx register
bits are set to 1. When the black box is enabled, it is no longer possible to read or
write to the configuration, user, and black box sections of EEPROM.
Writing this bit to 1 disables the black box and enables read and write access to
the configuration, user, and black box sections of EEPROM.
This bit cannot be set while a fault record is being written into the EEPROM;
therefore, this bit should always be read after a write to ensure that the bit is set
correctly.
Cannot be used.
When written to 1, the black box searches from Address 0xF980 to find the first
unused fault record. After erasing the section of EEPROM holding the black box
fault records, and for the black box to start writing records from the first location,
this bit should be written to 1.
Rev. C | Page 24 of 36
Application Note
AN-698
ADM1062/ADM1063/ADM1064/ADM1066/ADM1166 ADC
ADM1063/ADM1064/ADM1066/ADM1166, which can be
programmed to a maximum or minimum allowable threshold.
Only one register is provided for each input channel; therefore,
a UV or OV threshold, but not both, can be set for a given
channel. Exceeding the threshold generates a warning that can
be read back from the status registers or input into the SE via an
OR gate. The round robin can be enabled via an SMBus write or
can be programmed to turn on at a particular point in the SE
program; for instance, it can be set to start once a power-up
sequence is complete and all supplies are known to be within
expected fault limits.
The ADM1062, ADM1063, ADM1064, ADM1066, and
ADM1166 all feature an on-chip 12-bit ADC. The ADC has a
12-channel (13-channel on the ADM1063) analog mux on the
front end. Any or all of these inputs can be selected to be read
by the ADC. Thus the ADC can be set up to continuously read
the selected channels. The circuit controlling this operation is
called the round robin (RR). The user selects the channels to
operate on, and the ADC performs a conversion on each in
turn. Averaging can be turned on, setting the round robin to
take 16 conversions on each channel; otherwise, a single
conversion is made on each channel. At the end of this cycle,
the results are written to the output registers and, at the same
time, compared with preset thresholds provided on the ADM1062/
Table 12 through Table 17 show the details of the registers
required to set up the ADC and its inputs.
ADC Readback Configuration Registers
Table 12. Limit Registers—An ADC Reading Above or Below This Limit Generates a Warning
Input
VP1
VP2
VP3
VP4
VH
VX1
VX2
VX3
VX4
VX5
INTS
Reg.
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x78
0x79
0x7A
Reg. Name
ADCVP1LIM
ADCVP2LIM
ADCVP3LIM
ADCVP4LIM
ADCVHLIM
ADCVX1LIM
ADCVX2LIM
ADCVX3LIM
ADCVX4LIM
ADCVX5LIM
ADCITLIM
Bits
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
7:0
Mnemonic
LIM7 to LIM0
LIM7 to LIM0
LIM7 to LIM0
LIM7 to LIM0
LIM7 to LIM0
LIM7 to LIM0
LIM7 to LIM0
LIM7 to LIM0
LIM7 to LIM0
LIM7 to LIM0
LIM7 to LIM0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
AUX1
0x7A
ADCAUX1LIM
7:0
LIM7 to LIM0
R/W
EXTS1
0x7B
ADCXTS1LIM
7:0
LIM7 to LIM0
R/W
AUX2
0x7B
ADCAUX2LIM
7:0
LIM7 to LIM0
R/W
EXTS2
0x7C
ADCXTS2LIM
7:0
LIM7 to LIM0
R/W
Description
Limit register for ADC conversion on VP1 input.
Limit register for ADC conversion on VP2 input.
Limit register for ADC conversion on VP3 input.
Limit register for ADC conversion on VP4 input.
Limit register for ADC conversion on VH input.
Limit register for ADC conversion on VX1 input.
Limit register for ADC conversion on VX2 input.
Limit register for ADC conversion on VX3 input.
Limit register for ADC conversion on VX4 input.
Limit register for ADC conversion on VX5 input.
Limit register for ADC conversion on internal temp sensor
(ADM1062, ADM1063 only).
Limit register for ADC conversion on the AUX1 channel
(ADM1064, ADM1066 only).
Limit register for ADC conversion on External Temp Sensor 1
(ADM1062, ADM1063 only).
Limit register for ADC conversion on the AUX2 channel.
(ADM1064, ADM1066 only).
Limit register for ADC conversion on External Temp Sensor 2 (ADM1063 only).
Table 13. Sense Registers—Determine When a Warning Is Generated
Input
VX3
Reg.
0x7D
Reg. Name
LSENSE1
Bits Mnemonic
7
SENS7
R/W
R/W
VX2
6
SENS6
R/W
VX1
5
SENS5
R/W
VH
4
SENS4
R/W
VP4
3
SENS3
R/W
VP3
2
SENS2
R/W
Description
Limit sense for VX3. (0 = ADC > ADCVX3LIM gives a warning, that is,
overvoltage; 1 = ADC < ADCVX3LIM gives a warning, that is, undervoltage)
Limit sense for VX2. (0 = ADC > ADCVX2LIM gives a warning, that is,
overvoltage; 1 = ADC < ADCVX2LIM gives a warning, that is, undervoltage)
Limit sense for VX1. (0 = ADC > ADCVX1LIM gives a warning, that is,
overvoltage; 1 = ADC < ADCVX1LIM gives a warning, that is, undervoltage)
Limit sense for VH. (0 = ADC > ADCVHLIM gives a warning, that is,
overvoltage; 1 = ADC < ADCVHLIM gives a warning, that is, undervoltage)
Limit sense for VP4. (0 = ADC > ADCVP4LIM gives a warning, that is,
overvoltage; 1 = ADC < ADCVP4LIM gives a warning, that is, undervoltage)
Limit sense for VP3 (0 = ADC > ADCVP3LIM gives a warning, that is,
overvoltage; 1 = ADC < ADCVP3LIM gives a warning, that is, undervoltage)
Rev. C | Page 25 of 36
AN-698
Input
VP2
Reg.
Application Note
Reg. Name
Bits Mnemonic
1
SENS1
R/W
R/W
0
SENS0
R/W
EXTS2
7
6
5
4
SENS7
SENS6
SENS5
SENS4
R/W
AUX2
3
SENS3
R/W
EXTS1
3
SENS3
R/W
AUX1
2
SENS2
R/W
INTS
2
SENS2
R/W
VX5
1
SENS1
R/W
VX4
0
SENS0
R/W
VP1
0x7E
LSENSE2
Description
Limit sense for VP2. (0 = ADC > ADCVP2LIM gives a warning, that is,
overvoltage; 1 = ADC < ADCVP2LIM gives a warning, that is, undervoltage)
Limit sense for VP1. (0 = ADC > ADCVP1LIM gives a warning, that is,
overvoltage; 1= ADC < ADCVP1LIM gives a warning, that is, undervoltage)
Cannot be used.
Cannot be used.
Cannot be used.
Limit sense for External Temp Sensor 2 (ADM1063 only). (0 = ADC >
ACXTS2LIM gives a warning, that is, overvoltage; 1 = ADC < ACXTS2LIM
gives a warning, that is, undervoltage)
Limit sense for AUX2 (ADM1064, ADM1066 only). (0 = ADC > ADCAUX2LIM
gives a warning, that is, overvoltage; 1 = ADC < ADCAUX2LIM gives a
warning, that is, undervoltage)
Limit sense for External Temp Sensor 1 (ADM1062, ADM1063 only).
(0 = ADC > ACXTS1LIM gives a warning, that is, overvoltage; 1 = ADC <
ACXTS1LIM gives a warning, that is, undervoltage)
Limit sense for AUX1 (ADM1064, ADM1066 only). (0 = ADC > ADCAUX1LIM
gives a warning, that is, overvoltage; 1 = ADC < ADCAUX1LIM gives a
warning, that is, undervoltage)
Limit sense for internal temp sensor (ADM1062, ADM1063 only).
(0 = ADC > ADCITLIM gives a warning, that is, overvoltage; 1 = ADC <
ADCITLIM gives a warning, that is, undervoltage)
Limit sense for VX5. (0 = ADC > ADCVX5LIM gives a warning, that is,
overvoltage; 1 = ADC < ADCVX5LIM gives a warning, that is, undervoltage)
Limit sense for VX4. (0 = ADC > ADCVX4LIM gives a warning, that is,
overvoltage; 1 = ADC < ADCVX4LIM gives a warning, that is, undervoltage)
Table 14. Round Robin Select Registers—Determine Which Inputs Are Actually Read by the ADC As It Cycles
Input
VX3
VX2
VX1
VH
VP4
VP3
VP2
VP1
Reg.
0x80
Reg. Name
RRSEL1
Mnemonic
VX3CHAN
VX2CHAN
VX1CHAN
VHCHAN
VP4CHAN
VP3CHAN
VP2CHAN
VP1CHAN
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EXTS2
Bits
7
6
5
4
3
2
1
0
7
6
5
4
0x81
RRSEL2
EXTCH2
R/W
AUX2
3
AUX2CHAN
R/W
EXTS1
3
EXTCH1
R/W
AUX1
2
AUX1CHAN
R/W
INTS
2
INTSCHAN
R/W
VX5
VX4
1
0
VX5CHAN
VX4CHAN
R/W
R/W
Description
0 = VX3 is included in RR. 1 = VX3 is excluded from RR.
0 = VX2 is included in RR. 1 = VX2 is excluded from RR.
0 = VX1 is included in RR. 1 = VX1 is excluded from RR.
0 = VH is included in RR. 1 = VH is excluded from RR.
0 = VP4 is included in RR. 1 = VP4 is excluded from RR.
0 = VP3 is included in RR. 1 = VP3 is excluded from RR.
0 = VP2 is included in RR. 1 = VP2 is excluded from RR.
0 = VP1 is included in RR. 1 = VP1 is excluded from RR.
Cannot be used.
Cannot be used.
Cannot be used.
0 = External Temp Sensor 2 is included in RR.
1 = External Temp Sensor 2 is excluded from RR (ADM1063 only).
0 = Auxiliary Channel 2 is included in RR.
1 = Auxiliary Channel 2 is excluded from RR (ADM1064, ADM1066 only).
0 = External Temp Sensor 1 is included in RR.
1 = External Temp Sensor 1 is excluded from RR (ADM1062, ADM1063
only).
0 = Auxiliary Channel 1 is included in RR.
1 = Auxiliary Channel 1 is excluded from RR (ADM1064, ADM1066 only).
0 = Internal Temp Sensor 1 is included in RR.
1 = Internal Temp Sensor 1 is excluded from RR (ADM1062, ADM1063
only).
0 = VX5 is included in RR. 1= VX5 is excluded from RR.
0 = VX4 is included in RR. 1= VX4 is excluded from RR.
Rev. C | Page 26 of 36
Application Note
AN-698
Table 15. Round Robin Control Register—Activates ADC Read and Determines Whether Averaging Is Used and Whether There Is
a Continuous Read
Reg.
0x82
Reg. Name
RRCTRL
Bits
7:5
4
3
2
1
0
Mnemonic
R/W
ClearLIM
StopWrite
Average
Enable
Go
R/W
R/W
R/W
R/W
R/W
Description
Cannot be used.
Write this bit high to clear limit warnings. This bit then self-clears.
Inhibits the RR from writing the results to the output registers.
Turn on 16× averaging.
Turn on the RR for continuous operation.
Start the RR.
Table 16. Temperature Sensor Configuration Register
Reg.
0x83
Reg. Name
TSCTRL
Bits
7:3
2
1
0
Mnemonic
N/A
LOWDN2
LOWDN1
DIODE_CK
R/W
R/W
R/W
R/W
Description
Cannot be used.
Turn off VBE biasing for DN2 (ADM1063 only).
Turn off VBE biasing for DN1.
Set this bit to perform a diode check. If set, this causes the ADC result for the two
external channels to limit at full-scale positive if a diode is present. Used for board
checking.
Table 17. ADC Value Registers
Input
VP1
VP2
VP3
VP4
VH
VX1
VX2
VX3
Reg.
0xA0
0xA1
0xA2
0xA3
0xA4
0xA5
0xA6
0xA7
0xA8
0xA9
0xAA
0xAB
0xAC
0xAD
0xAE
0xAF
Reg. Name
ADCHVP1
ADCLVP1
ADCHVP2
ADCLVP2
ADCHVP3
ADCLVP3
ADCHVP4
ADCLVP4
ADCHVH
ADCLVH
ADCHVX1
ADCLVX1
ADCHVX2
ADCLVX2
ADCHVX3
ADCLVX3
Bits
7:4
3:0
7:0
7:0
7:4
3:0
7:0
7:0
7:4
3:0
7:0
7:0
7:4
3:0
7:0
7:0
7:4
3:0
7:0
7:0
7:4
3:0
7:0
7:0
7:4
3:0
7:0
7:0
7:4
3:0
7:0
7:0
Mnemonic
N/A
OUT3 to OUT0
OUT7 to OUT0
OUT7 to OUT0
N/A
OUT3 to OUT0
OUT7 to OUT0
OUT7 to OUT0
N/A
OUT3 to OUT0
OUT7 to OUT0
OUT7 to OUT0
N/A
OUT3 to OUT0
OUT7 to OUT0
OUT7 to OUT0
N/A
OUT3 to OUT0
OUT7 to OUT0
OUT7 to OUT0
N/A
OUT3 to OUT0
OUT7 to OUT0
OUT7 to OUT0
N/A
OUT3 to OUT0
OUT7 to OUT0
OUT7 to OUT0
N/A
OUT3 to OUT0
OUT7 to OUT0
OUT7 to OUT0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Not used if 0x82[2] (average) = 0.
4 MSBs of 12-bit result of ADC conversions on VP1 when 0x82[2] (average) = 0.
8 MSBs of 16-bit result of ADC conversions on VP1 when 0x82[2] (average) = 1.
8 LSBs of 12- or 16-bit result of the ADC conversions on VP1 input.
Not used if 0x82[2] (average) = 0.
4 MSBs of 12-bit result of ADC conversions on VP2 when 0x82[2] (average) = 0.
8 MSBs of 16-bit result of ADC conversions on VP2 when 0x82[2] (average) = 1.
8 LSBs of 12- or 16-bit result of the ADC conversions on VP2 input.
Not used if 0x82[2] (average) = 0.
4 MSBs of 12-bit result of ADC conversions on VP3 when 0x82[2] (average) = 0.
8 MSBs of 16-bit result of ADC conversions on VP3 when 0x82[2] (average) = 1.
8 LSBs of 12- or 16-bit result of the ADC conversions on VP3 input.
Not used if 0x82[2] (average) = 0.
4 MSBs of 12-bit result of ADC conversions on VP4 when 0x82[2] (average) = 0.
8 MSBs of 16-bit result of ADC conversions on VP4 when 0x82[2] (average) = 1.
8 LSBs of 12- or 16-bit result of the ADC conversions on VP4 input.
Not used if 0x82[2] (average) = 0.
4 MSBs of 12-bit result of ADC conversions on VH when 0x82[2] (average) = 0.
8 MSBs of 16-bit result of ADC conversions on VH when 0x82[2] (average) = 1.
8 LSBs of 12- or 16-bit result of the ADC conversions on VH input.
Not used if 0x82[2] (average) = 0.
4 MSBs of 12-bit result of ADC conversions on VX1 when 0x82[2] (average) = 0.
8 MSBs of 16-bit result of ADC conversions on VX1 when 0x82[2] (average) = 1.
8 LSBs of 12- or 16-bit result of the ADC conversions on VX1 input.
Not used if 0x82[2] (average) = 0.
4 MSBs of 12-bit result of ADC conversions on VX2 when 0x82[2] (average) = 0.
8 MSBs of 16-bit result of ADC conversions on VX2 when 0x82[2] (average) = 1.
8 LSBs of 12- or 16-bit result of the ADC conversions on VX2 input.
Not used if 0x82[2] (average) = 0.
4 MSBs of 12-bit result of ADC conversions on VX3 when 0x82[2] (average) = 0.
8 MSBs of 16-bit result of ADC conversions on VX3 when 0x82[2] (average) = 1.
8 LSBs of 12- or 16-bit result of the ADC conversions on VX3 input.
Rev. C | Page 27 of 36
AN-698
Input
VX4
VX5
INTS
AUX1
EXTS1
AUX2
EXTS2
Reg.
0xB0
0xB1
0xB2
0xB3
0xB4
0xB5
0xB4
0xB5
0xB6
0xB7
0xB6
0xB7
0xB8
0xB9
Application Note
Reg. Name
ADCHVX4
ADCLVX4
ADCHVX5
ADCLVX5
ADCHITS
ADCLITS
ADCHAUX1
ADCLAUX1
ADCHXTS1
ADCLXTS1
ADCHAUX2
ADCLAUX2
ADCHXTS2
ADCLXTS2
Bits
7:4
3:0
7:0
7:0
7:4
3:0
7:0
7:0
7:4
3:0
Mnemonic
N/A
OUT3 to OUT0
OUT7 to OUT0
OUT7 to OUT0
N/A
OUT3 to OUT0
OUT7 to OUT0
OUT7 to OUT0
N/A
OUT3 to OUT0
R/W
7:0
OUT7 to OUT0
R/W
7:0
7:4
3:0
7:0
7:0
7:4
3:0
OUT7 to OUT0
N/A
OUT3 to OUT0
OUT7 to OUT0
OUT7 to OUT0
N/A
OUT3 to OUT0
R/W
7:0
OUT7 to OUT0
R/W
7:0
7:4
3:0
7:0
7:0
7:4
3:0
OUT7 to OUT0
R/W
OUT3 to OUT0
OUT7 to OUT0
OUT7 to OUT0
N/A
OUT3 to OUT0
R/W
R/W
R/W
7:0
OUT7 to OUT0
R/W
7:0
OUT7 to OUT0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Not used if 0x82[2] (average) = 0.
4 MSBs of 12-bit result of ADC conversions on VX4 when 0x82[2] (average) = 0.
8 MSBs of 16-bit result of ADC conversions on VX4 when 0x82[2] (average) = 1.
8 LSBs of 12- or 16-bit result of the ADC conversions on VX4 input.
Not used if 0x82[2] (average) = 0.
4 MSBs of 12-bit result of ADC conversions on VX5 when 0x82[2] (average) = 0.
8 MSBs of 16-bit result of ADC conversions on VX5 when 0x82[2] (average) = 1.
8 LSBs of 12- or 16-bit result of the ADC conversions on VX5 input.
Not used if 0x82[2] (average) = 0.
4 MSBs of 12-bit result of internal temp sensor conversion
(ADM1062, ADM1063 only).
8 MSBs of 16-bit result of internal temp sensor conversion
(ADM1062, ADM1063 only).
Low byte of internal temp sensor conversion (ADM1062, ADM1063 only).
Not used if 0x82[2] (average) = 0.
4 MSBs of 12-bit result of AUX1 conversion (ADM1064, ADM1066 only).
8 MSBs of 16-bit result of AUX1 conversion (ADM1064, ADM1066 only).
Low byte of AUX1 conversion (ADM1064, ADM1066 only).
Not used if 0x82[2] (average) = 0.
4 MSBs of 12-bit result of External Temp Sensor 1 conversion
(ADM1062, ADM1063 only).
8 MSBs of 16-bit result of External Temp Sensor 1 conversion
(ADM1062, ADM1063 only).
Low byte of External Temp Sensor 1 conversion (ADM1062, ADM1063 only).
Not used if 0x82[2] (average) = 0.
4 MSBs of 12-bit result of AUX2 conversion (ADM1064, ADM1066 only).
8 MSBs of 16-bit result of AUX2 conversion (ADM1064, ADM1066 only).
Low byte of AUX2 conversion (ADM1064, ADM1066 only).
Not used if 0x82[2] (average) = 0.
4 MSBs of 12-bit result of External Temp Sensor 2 conversion
(ADM1063 only).
8 MSBs of 16-bit result of External Temp Sensor 2 conversion
(ADM1063 only).
Low byte of External Temp Sensor 2 conversion (ADM1063 only).
Rev. C | Page 28 of 36
Application Note
AN-698
ADM1062/ADM1066/ADM1067/ADM1166 DACS
The ADM1062, ADM1066, and ADM1067 feature six voltage
output DACs. These DACs are primarily used to adjust the
output voltage of a dc-to-dc converter by altering the current at
its feedback node. These DACs, therefore, provide an open-loop
margining system. The ADC on the ADM1062 and ADM1066
closes this loop. For more information on margining, see the
relevant data sheets.
the unsigned binary number in this register. Code 0x7F is
placed at the midcode voltage. The output voltage is given by
the following equation:
When the DACx output buffer is turned on, it has very little
effect on the dc-to-dc output. The DAC output buffer has been
designed to power up without glitching. It does this by first
powering up the buffer to follow the pin voltage and does not
drive out onto the pin at this time. Once the output buffer is
properly enabled, the buffer input is switched over to the DAC,
and the output stage of the buffer is turned on. Output glitching
is negligible.
Limit registers (called DPLIMx and DNLIMx) on the device
offer the user some protection from firmware bugs that can
cause catastrophic board problems by forcing supplies beyond
their allowable output ranges. Essentially, the DAC code written
into the DACx register is clipped so that the code used to set the
DAC voltage is actually given by
Four DAC ranges are offered, and these are placed with
midcode (Code 0x7F) at 0.6 V, 0.8 V, 1.0 V, and 1.25 V to
correspond to the most common feedback voltages. Centering
the DAC outputs in this way provides the best use of the DAC
resolution; that is, for most supplies it is possible to place the
DAC midcode at the point where the dc-to-dc output is not
modified, thus giving each of the DACs one half of the full
range to margin up and down. The DAC output voltage is set by
the code written to the DACx register. The voltage is linear with
DACoutput = (DACx − 0x7F)/255 × 0.6015 + VOFF
where VOFF is one of the four offset voltages described earlier in
this section.
DACCode
= DACx, DNLIMx ≤ DACx ≤ DPLIMx
= DNLIMx, DACx < DPLIMx
= DPLIMx, DACx > DPLIMx
The DAC output buffer is three-stated if DNLIMx > DPLIMx.
It is possible for the user to make it difficult for the DAC output
buffers to be turned on at all in normal system operation by
programming the limit registers in this way (these are among
the registers downloaded from EEPROM at startup).
Table 18 shows the detail of the registers required to set up
the DACs.
Rev. C | Page 29 of 36
AN-698
Application Note
Table 18. DAC Configuration Registers
Output
DAC1
DAC2
DAC3
Reg.
0x50
Reg. Name
DACCTRL1
Bits
7:3
2
1:0
Mnemonic
N/A
ENDAC
OFFSEL1 to OFFSEL0
R/W
R/W
R/W
0x58
0x60
DAC1
DPLIM1
7:0
7:0
DAC7 to DAC0
LIM7 to LIM0
R/W
R/W
0x68
DNLIM1
7:0
LIM7 to LIM0
R/W
0x51
DACCTRL2
7:3
2
1:0
N/A
ENDAC
OFFSEL1 to OFFSEL0
R/W
R/W
0x59
0x61
DAC2
DPLIM2
7:0
7:0
DAC7 to DAC0
LIM7 to LIM0
R/W
R/W
0x69
DNLIM2
7:0
LIM7 to LIM0
R/W
0x52
DACCTRL3
7:3
2
1:0
N/A
ENDAC
OFFSEL1 to OFFSEL0
R/W
R/W
0x5A
0x62
DAC3
DPLIM3
7:0
7:0
DAC7 to DAC0
LIM7 to LIM0
R/W
R/W
0x6A
DNLIM3
7:0
LIM7 to LIM0
R/W
Description
Cannot be used.
Enables DAC1.
Selects the center voltage (midcode) output of DAC1.
OFFSEL1
OFFSEL0
(Midcode) Output Voltage
0
0
1.25 V
0
1
1.0 V
1
0
0.8 V
1
1
0.6 V
8-bit DAC code (0x7F is midcode).
8-bit DAC positive limit code. If DAC1 is set to a higher code, the
DAC code limits to the contents of this register.
8-bit DAC negative limit code. If DAC1 is set to a lower code, the
DAC code limits to the contents of this register.
Note: if DNLIM1 is set to be greater than DPLIM1, the DAC output
is always disabled (this is a safety feature).
Cannot be used.
Enables DAC2.
Selects the center voltage (midcode) output of DAC2.
OFFSEL1
OFFSEL0
(Midcode) Output Voltage
0
0
1.25 V
0
1
1.0 V
1
0
0.8 V
1
1
0.6 V
8-bit DAC code (0x7F is midcode).
8-bit DAC positive limit code. If DAC2 is set to a higher code, the
DAC code limits to the contents of this register.
8-bit DAC negative limit code. If DAC2 is set to a lower code, the
DAC code limits to the contents of this register. Note: if DNLIM2 is
set to be greater than DPLIM2, the DAC output is always disabled
(this is a safety feature).
Cannot be used.
Enables DAC3.
Selects the center voltage (midcode) output of DAC3.
OFFSEL1
OFFSEL0
(Midcode) Output Voltage
0
0
1.25 V
0
1
1.0 V
1
0
0.8 V
1
1
0.6 V
8-bit DAC code (0x7F is midcode).
8-bit DAC positive limit code. If DAC3 is set to a code higher than
this, the DAC code limits to the contents of this register.
8-bit DAC negative limit code. If DAC3 is set to a code lower than
this, the DAC code limits to the contents of this register. Note: if
DNLIM3 is set to be greater than DPLIM3, the DAC output is always
disabled (this is a safety feature).
Rev. C | Page 30 of 36
Application Note
Output
DAC4
DAC5
DAC6
Reg.
0x53
Reg. Name
DACCTRL4
AN-698
Bits
7:3
2
1:0
Mnemonic
N/A
ENDAC
OFFSEL1 to OFFSEL0
R/W
R/W
R/W
0x5B
0x63
DAC4
DPLIM4
7:0
7:0
DAC7 to DAC0
LIM7 to LIM0
R/W
R/W
0x6B
DNLIM4
7:0
LIM7 to LIM0
R/W
0x54
DACCTRL5
7:3
2
1:0
N/A
ENDAC
OFFSEL1 to OFFSEL0
R/W
R/W
0x5C
0x64
DAC5
DPLIM5
7:0
7:0
DAC7 to DAC0
LIM7 to LIM0
R/W
R/W
0x6C
DNLIM5
7:0
LIM7 to LIM0
R/W
0x55
DACCTRL6
7:3
2
1:0
N/A
ENDAC
OFFSEL1 to OFFSEL0
R/W
R/W
0x5D
0x65
DAC6
DPLIM6
7:0
7:0
DAC7 to DAC0
LIM7 to LIM0
R/W
R/W
0x6D
DNLIM6
7:0
LIM7 to LIM0
R/W
Description
Cannot be used.
Enables DAC4.
Selects the center voltage (midcode) output of DAC4.
OFFSEL1
OFFSEL0
(Midcode) Output Voltage
0
0
1.25 V
0
1
1.0 V
1
0
0.8 V
1
1
0.6 V
8-bit DAC code (0x7F is midcode).
8-bit DAC positive limit code. If DAC4 is set to a higher code, the
DAC code limits to the contents of this register.
8-bit DAC negative limit code. If DAC4 is set to a lower code, the
DAC code limits to the contents of this register. Note: if DNLIM4 is
set to be greater than DPLIM4, the DAC output is always disabled
(this is a safety feature).
Cannot be used.
Enables DAC5.
Selects the center voltage (midcode) output of DAC5.
OFFSEL1
OFFSEL0
(Midcode) Output Voltage
0
0
1.25 V
0
1
1.0 V
1
0
0.8 V
1
1
0.6 V
8-bit DAC code (0x7F Is midcode).
8-bit DAC positive limit code. If DAC5 is set to a higher code, the
DAC code limits to the contents of this register.
8-bit DAC negative limit code. If DAC5 is set to a lower code, the
DAC code limits to the contents of this register. Note: if DNLIM5 is
set to be greater than DPLIM5, the DAC output is always disabled
(this is a safety feature).
Cannot be used.
Enables DAC6.
Selects the center voltage (midcode) output of DAC5.
OFFSEL1
OFFSEL0
(Midcode) Output Voltage
0
0
1.25 V
0
1
1.0 V
1
0
0.8 V
1
1
0.6 V
8-bit DAC code (0x7F is midcode).
8-bit DAC positive limit code. If DAC6 is set to a higher code, the
DAC code limits to the contents of this register.
8-bit DAC negative limit code. If DAC6 is set to a lower code, the
DAC code limits to the contents of this register. Note: if DNLIM6 is
set to be greater than DPLIM6, the DAC output is always disabled
(this is a safety feature).
Rev. C | Page 31 of 36
AN-698
Application Note
WARNINGS, FAULTS, AND STATUS
WARNINGS
The ADM1062/ADM1063/ADM1064/ADM1065/ADM1066/
ADM1067/ADM1166 devices feature a lower level of fault
detection that can be used in conjunction with the fault
detection provided on the inputs. These lower level fault reports
are provided by the ADC limit registers and by the secondary
SFDs on the VP1 to VP4 and VH inputs. (The secondary SFDs
are available on these pins when VX1 to VX5 are used as digital
inputs; see the Inputs section.)
WARNING is provided as a single input to the SE. It consists of
a wide OR of the ADC limit registers and the secondary SFD
outputs. Selecting WARNING as an input to the SE is shown in
the Sequencing Engine section.
FAULT/STATUS REPORTING
If a fault occurs on one of the inputs being monitored by the
ADM1062/ADM1063/ADM1064/ADM1065/ADM1066/
ADM1067/ADM1166 (that is, a supply on one of the
VXx/VPx/VH pins moves outside its threshold window), a logic
level is deasserted, or an ADC input violates the limit set in its
limit register, it is possible to identify exactly on which input the
fault occurred. This is done by reading back the fault plane over
the SMBus.
The fault plane is simply two registers, FSTAT1 and FSTAT2,
where each bit represents a function, for example, a VPx pin or
an ADC channel. By reading the contents of these registers and
determining which bits are set to 1, the user can identify the
inputs on which faults have occurred. A 1 is defined as a fault.
The exception to this is when a VXx pin is used as a digital
input. In that case, 1 is the true logic value of the input on
the pin.
The fault data is reported to the fault plane only if explicitly
enabled. This is done by setting the fault latch bit high in each
individual state. To do this, set Bit 63 in the relevant state
configuration to 1 (see Table 5). If this bit is not set, a fault that
occurs in this state is not latched in the fault plane. The
ADM1062/ADM1063/ADM1064/ADM1065/ADM1066/
ADM1067/ADM1166 also feature a number of status registers
that can be read at any time to determine the status of the
inputs. The contents of these registers can change at any time;
that is, the data is not latched in these registers as is the case
with FSTAT1 and FSTAT2. Table 19 shows the details of the
fault and status registers.
Table 19. Fault and Status Registers
Reg.
0xE0
Reg. Name
FSTAT1
0xE1
FSTAT2
0xE2
OVSTAT1
0xE3
OVSTAT2
0xE4
UVSTAT1
Bits
7
6
5
4
3
2
1
0
7:2
1
0
7
6
5
4
3
2
1
0
7:2
1
0
7
6
5
4
3
2
Mnemonic
FLT_VX3
FLT_VX2
FLT_VX1
FLT_VH
FLT_VP4
FLT_VP3
FLT_VP2
FLT_VP1
R/W
R
R
R
R
R
FLT_VX5
FLT_VX4
OV_VX3
OV_VX2
OV_VX1
OV_VH
OV_VP4
OV_VP3
OV_VP2
OV_VP1
R
R
R
R
R
R
R
R
R
R
OV_VX5
OV_VX4
UV_VX3
UV_VX2
UV_VX1
UV_VH
UV_VP4
UV_VP3
R
R
R
R
R
R
R
R
Description
Fault output from the VX3 pin (either as a GPI or as an SFD).
Fault output from the VX2 pin (either as a GPI or as an SFD).
Fault output from the VX1 pin (either as a GPI or as an SFD).
Fault output from the VH SFD.
Fault output from the VP4 SFD.
Fault output from the VP3 SFD.
Fault output from the VP2 SFD.
Fault output from the VP1 SFD.
Cannot be used.
Fault output from the VX5 pin (either as a GPI or as an SFD).
Fault output from the VX4 pin (either as a GPI or as an SFD).
OV threshold exceeded on VX3 (SFD) or VP3 (warning).
OV threshold exceeded on VX2 (SFD) or VP2 (warning).
OV threshold exceeded on VX1 (SFD) or VP1 (warning).
OV threshold exceeded on the VH SFD.
OV threshold exceeded on the VP4 SFD.
OV threshold exceeded on the VP3 SFD.
OV threshold exceeded on the VP2 SFD.
OV threshold exceeded on the VP1 SFD.
Cannot be used.
OV threshold exceeded on VX5 (SFD) or VH (warning).
OV threshold exceeded on VX4 (SFD) or VP4 (warning).
UV threshold exceeded on VX3 (SFD) or VP3 (warning).
UV threshold exceeded on VX2 (SFD) or VP2 (warning).
UV threshold exceeded on VX1 (SFD) or VP1 (warning).
UV threshold exceeded on the VH SFD.
UV threshold exceeded on the VP4 SFD.
UV threshold exceeded on the VP3 SFD.
Rev. C | Page 32 of 36
Application Note
Reg.
Reg. Name
0xE5
UVSTAT2
0xE6
LIMSTAT1
0xE7
LIMSTAT2
0xE8
GPISTAT
AN-698
Bits
1
0
7:2
1
0
7
6
5
4
3
2
1
0
4
3
3
2
2
1
0
7:5
4
3
2
1
0
Mnemonic
UV_VP2
UV_VP1
R/W
R
R
UV_VX5
UV_VX4
VX3 CH
VX2 CH
VX1 CH
VH CH
VP4 CH
VP3 CH
VP2 CH
VP1 CH
EXTS2
AUX2
EXTS1
AUX1
IN TS
VX5 CH
VX4 CH
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
VX5_STAT
VX4_STAT
VX3_STAT
VX2_STAT
VX1_STAT
R
R
R
R
R
Description
UV threshold exceeded on the VP2 SFD.
UV threshold exceeded on the VP1 SFD.
Cannot be used.
UV threshold exceeded on VX5 (SFD) or VH (warning).
UV threshold exceeded on VX4 (SFD) or VP4 (warning).
VX3 limit status – used with LSENSE 1.
VX2 limit status – used with LSENSE 1.
VX1 limit status – used with LSENSE 1.
VH limit status – used with LSENSE 1.
VP4 limit status – used with LSENSE 1.
VP3 limit status – used with LSENSE 1.
VP2 limit status – used with LSENSE 1.
VP1 limit status – used with LSENSE 1.
EXTS2 limit status – used with LSENSE 2. ADM1063 only.
AUX2 limit status – used with LSENSE 2. ADM1064 and ADM1066 only.
EXTS1 limit status – used with LSENSE 2. ADM1062 and ADM1063 only.
AUX1 limit status – used with LSENSE 2. ADM1064 and ADM1066 only.
IN TS limit status – used with LSENSE 2. ADM1062 and ADM1063 only.
VX5 CH limit status – used with LSENSE 2.
VX4 CH limit status – used with LSENSE 2.
Cannot be used.
VX5 GPI input status (after signal conditioning).
VX4 GPI input status (after signal conditioning).
VX3 GPI input status (after signal conditioning).
VX2 GPI input status (after signal conditioning).
VX1 GPI input status (after signal conditioning).
BLACK BOX STATUS REGISTERS AND FAULT
RECORDS ON THE ADM1166
Each time the ADM1166 sequence engine changes state, the
contents of UVSTATx, OVSTATx, LIMSTATx, and GPISTATx,
along with some other pieces of information relating to the
sequence engine state and the cause of the last state transition,
are latched into seven black box status registers.
These registers provide a snapshot of the state of the inputs
being monitored by the ADM1166, what the last state was, and
what caused the last state change.
After the sequence engine changes state, if the new state it
enters has its corresponding BBWRTRGx.STATEy bit set, the
seven black box status registers are written sequentially into the
next available location in the black box EEPROM section.
After the seven bytes are written, an eighth checksum byte is
written to provide a method to check data integrity. This can be
important if only a partial record is written because all the
supplies powering the part have failed.
•
•
•
•
•
•
•
•
PREVSTEXT
PREVSEQST
BBSTAT1
BBSTAT2
BBSTAT3
BBSTAT4
BBSTAT5
CHECKSUM
The bytes are stored from lowest EEPROM address to highest;
therefore, for the first fault record location in the black box
EEPROM, PREVSTEXT would be stored at 0xF980 and
CHECKSUM at 0xF987.
USE OF THE REVID REGISTER
The ADM1066 and ADM1166 have the same I2C addresses
range, and both return the value of 0x41 when the MANID
register is read. REVID is a read-only register that can be used
to determine whether a device at a given address is an ADM1066
or an ADM1166. This is detailed in Table 21.
The order of the bytes in a fault record stored in EEPROM is as
follows:
Rev. C | Page 33 of 36
AN-698
Application Note
Table 20. ADM1166 Black Box Fault and Status Registers
Reg.
0xEA
Reg. Name
PREVSTEXT
0xEB
PREVSEQST
0xEC
BBSTAT 1
0xED
BBSTAT2
0xEE
BBSTAT3
0xEF
BBSTAT4
Bits
7
Mnemonic
BBUSED
R/W
6
5
Reserved
SMBJUMP
R
4
LIMWARN
R
3
SFDCMP
R
2
Timeout
R
1
Monitor
R
0
Sequence
R
7:6
5:0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
PREVADDR
UV_VX3
UV_VX2
UV_VX1
UV_VH
UV_VP4
UV_VP3
UV_VP2
UV_VP1
OV_VX1
OV_VH
OV_VP4
OV_VP3
OV_VP2
OV_VP1
UV_VX5
UV_VX4
VX4_STAT
VX3_STAT
VX2_STAT
VX1_STAT
OV_VX5
OV_VX4
OV_VX3
OV_VX2
VX2 CH
VX1 CH
VH CH
VP4 CH
VP3 CH
VP2 CH
VP1 CH
VX5_STAT
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Description
Always reads as 0.
When this bit is written to the first byte of a fault record in EEPROM, it marks all
eight bytes in use. When the black box is searching for the next free location to
use, this bit is examined. If this bit is 0, then even if the previous fault record was
only partially written to EEPROM, the eight bytes of the fault record are ignored.
Always reads as 0.
Indicates that the previous state transition was due to an SMBJump being
received.
Indicates that the previous state transition was due to one or more ADC
warning limits being exceeded.
Indicates that the previous state transition was due to one or more supply fault
detector limits being exceeded.
Indicates that the previous state transition was due to the timeout condition
becoming true.
Indicates that the previous state transition was due to the monitor condition
becoming true.
Indicates that the previous state transition was due to the sequence condition
becoming true.
Cannot be used.
State number of the state that was active immediately prior to the current state.
UV threshold exceeded on VX3 (SFD) or VP3 (warning).
UV threshold exceeded on VX2 (SFD) or VP2 (warning).
UV threshold exceeded on VX1 (SFD) or VP1 (warning).
UV threshold exceeded on the VH SFD.
UV threshold exceeded on the VP4 SFD.
UV threshold exceeded on the VP3 SFD.
UV threshold exceeded on the VP2 SFD.
UV threshold exceeded on the VP1 SFD.
OV threshold exceeded on VX1 (SFD) or VP1 (warning).
OV threshold exceeded on the VH SFD.
OV threshold exceeded on the VP4 SFD.
OV threshold exceeded on the VP3 SFD.
OV threshold exceeded on the VP2 SFD.
OV threshold exceeded on the VP1 SFD.
UV threshold exceeded on VX5 (SFD) or VH (warning).
UV threshold exceeded on VX4 (SFD) or VP4 (warning).
VX4 GPI input status (after signal conditioning).
VX3 GPI input status (after signal conditioning).
VX2 GPI input status (after signal conditioning).
VX1 GPI input status (after signal conditioning).
OV threshold exceeded on VX5 (SFD) or VH (warning).
OV threshold exceeded on VX4 (SFD) or VP4 (warning).
OV threshold exceeded on VX3 (SFD) or VP3 (warning).
OV threshold exceeded on VX2 (SFD) or VP2 (warning).
VX2 limit status – used with LSENSE 1.
VX1 limit status – used with LSENSE 1.
VH limit status – used with LSENSE 1.
VP4 limit status – used with LSENSE 1.
VP3 limit status – used with LSENSE 1.
VP2 limit status – used with LSENSE 1.
VP1 limit status – used with LSENSE 1.
VX5 GPI input status (after signal conditioning).
Rev. C | Page 34 of 36
Application Note
Reg.
0x F0
Reg. Name
BBSTAT5
0x F1
AN-698
Bits
7:5
4
3
2
1
0
7:0
BBADDR
Mnemonic
R/W
AUX2
AUX1
VX5 CH
VX4 CH
VX3 CH
ADDR
R
R
R
R
R
R
Description
Cannot be used.
AUX2 limit status – used with LSENSE 2. ADM1064 and ADM1066 only.
AUX1 limit status – used with LSENSE 2. ADM1064 and ADM1066 only.
VX5 CH limit status – used with LSENSE 2.
VX4 CH limit status – used with LSENSE 2.
VX3 limit status – used with LSENSE 1.
Low byte of the address location in the 0xF980 to 0xF9FF range that the next
fault record is written to. When no fault records have been written, the value is
0x80, and increments by 8 each time a fault record is written. The value is 0x F8
when there is only one fault record not written. When all locations have been
written to, and the black box EEPROM is full, the value is 0x00.
Table 21. Decoding the REVID Register.
Reg.
0xF5
Reg. Name
REVID
Bits
7:4
Mnemonic
Family
R/W
R
3:0
HWVER
R
Description
When the value 0x0 is read, the device is an ADM1062/ADM1063/ADM1064/
ADM1065/ADM1066/ADM1067.
When the value 0x1 is read, the device is an ADM1166.
This value is the hardware revision number.
Table 22. Register Map Quick Reference 1
Base
(Hex)
Function
0
1
2
3
4
5
6
7
00
08
10
18
20
VP1
VP2
VP3
VP4
VH
PS1OVTH
PS2OVTH
PS3OVTH
PS4OVTH
PSVHOVTH
PS1UVTH
PS2UVTH
PS3UVTH
PS4UVTH
PSVHUVTH
PS1UVHYST
PS2UVHYST
PS3UVHYST
PS4UVHYST
PSVHUVHYST
SFDV1CFG
SFDV2CFG
SFDV3CFG
SFDV4CFG
PSVHDVHCFG
SFDV1SEL
SFDV2SEL
SFDV3SEL
SFDV4SEL
SFDVHSEL
x
x
x
x
x
PDO1CFG
PDO2CFG
PDO3CFG
PDO4CFG
PDO5CFG
28
30
38
40
48
50
58
60
68
70
78
80
88
90
VX1
VX2
VX3
VX4
VX5
DAC control
DAC code
DAC upper limit
DAC lower limit
ADCLIM
ADCLIM
ADC setup
X1OVTH
X2OVTH
X3OVTH
X4OVTH
X5OVTH
DACCTRL1
DAC1
DPLIM1
DNLIM1
ADCVP1LIM
ADCVX4LIM
RRSEL1
x
UPDCFG
PS1OVHYST
PS2OVHYST
PS3OVHYST
PS4OVHYST
PSVHOVHYS
T
X1OVHYST
X2OVHYST
X3OVHYST
X4OVHYST
X5OVHYST
DACCTRL2
DAC2
DPLIM2
DNLIM2
ADCVP2LIM
ADCVX5LIM
RRSEL2
x
PDEN1
X1UVTH
X2UVTH
X3UVTH
X4UVTH
X5UVTH
DACCTRL3
DAC3
DPLIM3
DNLIM3
ADCVP3LIM
ADCITLIM
RRCTRL
x
PDEN2
X1UVHYST
X2UVHYST
X3UVHYST
X4UVHYST
X5UVHYST
DACCTRL4
DAC4
DPLIM4
DNLIM4
ADCVP4LIM
ADCXTS1LIM
TSCTRL
x
SECTRL
SFDX1CFG
SFDX2CFG
SFDX3CFG
SFDX4CFG
SFDX5CFG
DACCTRL5
DAC5
DPLIM5
DNLIM5
ADCVHLIM
ADCXTS2LIM
x
x
BBWRTRG1 2
BBWRTRG72
ADCHVP2
ADCHVX1
ADCHVX5
x
x
x
x
UNLOCKSE2
OVSTAT1
PREVSTEXT2
x
BBWRTRG82
ADCLVP2
ADCLVX1
ADCLVX5
x
x
x
x
SEDOWNLD2
OVSTAT2
PREVSEQST2
x
BBCTRL2
ADCHVP3
ADCHVX2
ADCHITS
x
x
x
x
x
SFDX1SEL
SFDX2SEL
SFDX3SEL
SFDX4SEL
SFDX5SEL
DACCTRL6
DAC6
DPLIM6
DNLIM6
ADCVX1LIM
LSENSE1
x
x
BBWRTRG22
x
XGPI1CFG
XGPI2CFG
XGPI3CFG
XGPI4CFG
XGPI5CFG
x
x
x
x
ADCVX2LIM
LSENSE2
x
x
BBWRTRG32
x
PDO6CFG
PDO7CFG
PDO8CFG
PDO9CFG
PDO10CFG
x
x
x
x
ADCVX3LIM
x
x
x
BBWRTRG42
x
ADCLVP3
ADCLVX2
ADCLITS
x
x
x
x
x
ADCHVP4
ADCHVX3
ADCHXTS1
x
x
x
x
x
ADCLVP4
ADCLVX3
ADCLXTS1
x
x
x
x
x
UVSTAT1
BBSTAT12
MANID
UVSTAT2
BBSTAT22
REVID
LIMSTAT1
BBSTAT42
MARK1
LIMSTAT2
BBSTAT42
MARK2
EEBLOW
EEBHIGH
BLKWR
BLKRD
BLKER
x
Miscellaneous
98
Miscellaneous
A0
A8
B0
B8
C0
C8
D0
D8
ADC readback
ADC readback
ADC readback
ADC readback
E0
E8
Fault (read-only) FSTAT1
Fault (read-only) GPISTAT
F0
Miscellaneous
F8
Commands
1
2
Miscellaneous
BBWRTRG52
ADCHVP1
ADCHVH
ADCHVX4
ADCHXTS2
x
x
x
UDOWNLD
BBSTAT52
EEALOW
BBWRTRG62
ADCLVP1
ADCLVH
ADCLVX4
ADCLXTS2
x
x
x
BBSEARCH2
FSTAT2
SEADDR
BBADDR2
EEAHIGH
x indicates that register locations do not exist.
Available only on the ADM1166.
Rev. C | Page 35 of 36
AN-698
Application Note
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2007-2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
AN04615-0-7/13(C)
Rev. C | Page 36 of 36