AN-1139
APPLICATION NOTE
One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com
Understanding the Parallel Programming Protocol
by Eckart Hartmann
INTRODUCTION
The main method of programming the ADuC8xx family of parts is
via serial programming as described in the relevant data sheets,
which are available at www.analog.com, in conjunction with
Application Note AN-1074.
However, for some users, it may be more convenient to program
the parts via a standard device programmer. The ADuC8xx family
allows for parallel programming so that suppliers of standardized
programmers can support this family of devices.
This application note describes this parallel programming
protocol. The protocol is essentially the same as that used for
many standalone EPROM and EEPROM devices available in
the market; however, some additional considerations must be
taken into account.
The information in this application note applies to all ADuC83x
and ADuC84x devices.
Rev. 0 | Page 1 of 12
AN-1139
Application Note
TABLE OF CONTENTS
Introduction ...................................................................................... 1 Erase All..........................................................................................8 Memory Map..................................................................................... 3 Program Byte .................................................................................9 Pin Configuration............................................................................. 4 Page Programming..................................................................... 10 Entry into Parallel Programming Mode........................................ 5 Read Byte..................................................................................... 11 Command Functions ....................................................................... 6 Byte Program/Byte Read Program flow .................................. 12 Programming the Address Register ........................................... 6 Reading the Address Register ..................................................... 7 1/12—Revision 0: Initial Version
Rev. 0 | Page 2 of 12
Application Note
AN-1139
MEMORY MAP
ADuC842/ADuC843/ADuC845/ADuC847/ADuC848. The
MS bit as described in the Command Functions section selects
addressing of program memory (MS = 1) vs. data memory
(MS = 0).
In parallel programming mode, the various areas of memory
are mapped into portions of the available addressable space.
Figure 1 shows this mapping for the small memory devices,
ADuC834/ADuC836. Figure 2 shows this mapping for the
larger memory devices, ADuC831/ADuC832/ADuC841/
EMBEDDED DOWNLOAD/DEBUG KERNEL
PERMANENTLY EMBEDDED FIRMWARE ALLOWS CODE TO
BE DOWNLOADED TO ANY OF THE 8kB OF ON-CHIP
MEMORY VIA SERIAL DOWNLOAD MODE.
THE KERNEL SPACE APPEARS AS NOP
INSTRUCTIONS TO USER CODE.
0x27FF
2kB
0x2000
0x1FFF
6kB OF CODE MEMORY ADDRESSABLE
IN PARALLEL PROGRAMMING MODE.
8kB
0x27F
0x0000
MS = 1
0x000
MS = 0
10457-001
640B
ON-CHIP
FLASH/EE
DATA MEMORY
Figure 1. Parallel Programming Memory Map for Small Memory Devices
EMBEDDED DOWNLOAD/DEBUG KERNAL
PERMANENTLY EMBEDDED FIRMWARE ALLOWS CODE TO
BE DOWNLOADED TO ANY OF THE 62kB OF ON-CHIP
MEMORY VIA SERIAL DOWNLOAD MODE.
THE KERNAL SPACE APPEARS AS NOP
INSTRUCTIONS TO USER CODE.
0xFFFF
2kB
0xF800
0xF7FF
32 BYTES OR 62kB OF CODE MEMORY
ADDRESSABLE IN PARALLEL PROGRAMMING MODE.
62kB
0xFFF
0x0000
MS = 1
Figure 2. Parallel Programming Memory Map for Large Memory Devices
Rev. 0 | Page 3 of 12
0x000
MS = 0
10457-002
4kB
ON-CHIP
FLASH/EE
DATA MEMORY
AN-1139
Application Note
PIN CONFIGURATION
•
•
Parallel programming is achieved by sending a sequence of
commands to the device using the signals shown in Figure 3.
There is a special entry sequence followed by the different
commands that are described in the Command Functions
section.
•
•
Port 3 is the 8-bit bidirectional data bus for programming
and reading bytes.
P1.1 to P1.4 is the 4-bit command input for specifying erase,
program, and read.
For entry into parallel programming mode, PSEN must be
connected to ground via a 1 kΩ resister at the base of the
transistor shown.
VDD
ADuC83x/ADuC84x
P3.0 TO P3.7
COMMAND
DATA
P1.1 TO P1.4
EA
TIMING
ENABLE
P1.5 TO P1.7
P1.0
RESET
PSEN
1kΩ
10457-003
•
•
P1.5 to P1.7 supply the timing for the parallel programming.
P1.0 is the active-low enable input for strobing a command
on P1.1 to P1.4.
EA is used for entry to parallel programming mode.
Figure 3. Pin Configuration for Parallel Programming
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Application Note
AN-1139
ENTRY INTO PARALLEL PROGRAMMING MODE
Note the following about the power supply:
For entry into parallel programming, mode (P3.1 to P3.4) =
0b1101.
•
To ensure a safe command is placed on Port 1 when entering
parallel mode, use the 0xCD command because this corresponds
to a read address register command.
•
PSEN must be driven by a 1 kΩ resistor, as shown in Figure 3.
•
The ground pins (DGND and AGND) must be treated as a
single node.
The VDD pins (AVDD and DVDD) must be treated as a single
node.
The voltage applied to any pin must never be greater than
VDD or less than ground.
VDD must remain stable and within specification throughout
the entire programming process.
•
150ms MIN
VDD (I)
1µs MIN
0µs MIN
RESET (I)
PSEN (I)
50µs + 10µs
EA (I)
0µs MIN
P3.4 TO P3.1(I) (I)
0b1101
0µs MIN
P1.7 TO P1.0 (I)
0xCD
100µs MIN
100µs MIN
Figure 4. Entrance Sequence for Parallel Programming
Rev. 0 | Page 5 of 12
10457-004
P3.0 (I)
AN-1139
Application Note
COMMAND FUNCTIONS
Table 1 lists the commands that carry out the various parallel
programming functions.
PROGRAMMING THE ADDRESS REGISTER
Table 1. Parallel Programming Commands
P1.4
0
P1.3
0
P1.2
0
P1.1
0
MS
MS
0
1
1
0
0
1
1
1
1
1
1
1
1
0
1
0
0
1
Function
Erase all (code/data plus security
bits)
Program byte
Read byte
Read address register
Program address register
Default pull-ups, do nothing
In the program byte function and read byte function, the MS bit
in Table 1 is used to select program memory (P1.4 = 1) or data
memory (P1.4 = 0).
EADRH and EADRL are the address registers for the microcontroller products. To program the address for byte programming,
use the command and timing sequence shown in Figure 5.
Table 2. Program Address Register Command Key
P1.4
1
P1.3
1
P1.1
0
Function
Program address register
Note that EADRL is automatically incremented following a byte
or a page program command; therefore, no manual increment
of EADRL is required for subsequent sequential programming
commands.
P1.4 TO P1.1(I)
COMMAND (0b1110)
P3 (I)
PROGRAM DATA IN
P1.6 (I)
P1.2
1
ADDRESS: (0 = EADRL/1 = EADRH)
P1.7 (I)
P1.5 (I)
P1.0 (I)
1µs MIN
1µs MIN
1µs MIN
10457-005
NOTES
1. IF P1.6 = 1, THEN EADRH IS SELECTED.
2. IF P1.6 = 0, THEN EADRL IS SELECTED.
Figure 5. Program the Address Register
Rev. 0 | Page 6 of 12
Application Note
AN-1139
READING THE ADDRESS REGISTER
Table 3. Read Address Register Command Key
EADRH and EADRL are the address registers for the microcontroller products. To read the current address, use the
command and timing sequence shown in Figure 6.
P1.4
0
P1.4 TO P1.1(I)
P1.3
1
P1.2
1
P1.1
0
Function
Read address register
COMMAND (0b0110)
DATA OUT
P3 (O)
P1.7 (I)
0µs MIN
ADDRESS: (0 = EADRL / 1 = EADRH)
P1.6 (I)
P1.5 (I)
P1.0 (I)
1µs MIN
200ns MAX
10457-006
NOTES
1. IF P1.6 = 1, THEN EADRH IS SELECTED.
2. IF P1.6 = 0, THEN EADRL IS SELECTED.
Figure 6. Read the Address Registers
Rev. 0 | Page 7 of 12
AN-1139
Application Note
ERASE ALL
To erase the NV data and program flash, use the command and timing sequence shown in Figure 7.
Table 4. Erase All Command Key
P1.3
0
P1.2
0
P1.1
0
P1.4 TO P1.1(I)
Function
Erase all (code/data plus security bits)
COMMAND (0b0000)
P1.6 (I)
P1.7 (I)
P1.5 (I)
ERASE 20ms ± 10µs
P1.0 (I)
10µs MIN
30µs MIN
1µs MIN
0µs MIN
Figure 7. Erase All
Rev. 0 | Page 8 of 12
10457-007
P1.4
0
Application Note
AN-1139
PROGRAM BYTE
To program a byte at the location given by EADRH and EADRL
(already programmed via the program address register operation,
see Figure 5), use the command and timing sequence shown
in Figure 8.
Table 5. Program Byte Command Key
P1.4
MS
P1.3
0
P1.2
1
P1.1
0
Function
Program byte
For a description of the MS bit, see the Command Functions
section and Table 1.
COMMAND (0b0010 = DATA MEMORY/0b1010 = PROGRAM MEMORY)
P1.4 TO P1.1 (I)
PROGRAM DATA IN
P3 (I)
0µs MIN
1µs MIN
P1.7 (I)
P1.6 (I)
P1.5 (I)
P1.0 (I)
30µs ± 5µs
10µs ± 1µs
Figure 8. Program a Byte
Rev. 0 | Page 9 of 12
10µs
± 1µs
10µs
MIN
1µs MIN
10457-008
60µs ± 10µs
10µs MIN
AN-1139
Application Note
PAGE PROGRAMMING
As an alternative to programming a single byte at a time, the page
programming function can be chosen by following the timing
diagram shown in Figure 9. Note that the command byte is the
same as for a byte programming function, and in fact, the page
programming function is little more than a series of consecutive
single bytes programmed in quick succession within strict timing
constraints. If for any reason, not all the timing requirements
can be met, use byte programming instead.
P1.3
0
P1.2
1
P1.1
0
Value
XXXXXXXXXX00000
XXXXXXXXXX00001
XXXXXXXXXX00010
...
XXXXXXXXXX11111
Table 8. One Page of Data Memory1
Table 6. Page Programming Command Key
P1.4
MS
Table 7. One Page of Program Memory
Address
Address 0
Address 1
Address 2
...
Address 31
Address
Address 0
Address 1
Function
Program byte
For a description of the MS bit, see the Command Functions
section and Table 1.
Value
XXXXXXXXXXXXXXX0
XXXXXXXXXXXXXXX1
1
In parallel programming mode, a page of data memory is 2 bytes, whereas in
user mode, each page is 4 bytes.
A page of program memory is 32 bytes in size, whereas a page of
data memory is only two bytes in size. For program memory,
the first address of a page ends in 0b00000 and the last address
of a page ends in 0b11111. For data memory, the first address of
a page ends in 0, and the second (that is, last) address in a page
ends in 1. This is shown in Table 7 and Table 8. Page programming
requires that all addresses in the page be programmed sequentially
within a single sequence, starting with Address 0 and ending
with Address 31 (or Address 1 for data memory).
COMMAND (0b0010 = DATA MEMORY/0b1010 = PROGRAM MEMORY)
P1.4 TO P1.1 (I)
P3 (I)
DATA0
DATA1
DATA2
DATA3
DATA31
P1.5 (I)
10µs MIN
60µs
±10µs
5µs ±1µs
P1.0 (I)
1µs MIN
10µs ±1µs
P1.6 (I)
30µs
±5µs
30µs
±5µs
P1.7 (I)
1µs MIN
10µs MIN
1µs MIN
1µs MIN
10µs MIN
1µs MIN
1µs MIN
REPEAT FOR 32 ADDRESSES FOR PROGRAM MEMORY
REPEAT FOR 2 ADDRESSES FOR DATA MEMORY
Figure 9. Page Programming
Rev. 0 | Page 10 of 12
10457-009
5µs
±1µs
Application Note
AN-1139
READ BYTE
To read the byte at address (EADRH:EADRL), use the command
and timing sequence shown in Figure 10.
Table 9. Read Byte Command Key
P1.4
MS
P1.3
0
P1.2
1
P1.1
1
Function
Read byte
For a description of the MS bit, see the Command Functions
section and Table 1.
P1.4 TO P1.1(I)
COMMAND (0b0011 = DATA MEMORY / 0b1011 = PROGRAM MEMORY)
P3 (O)
DATA OUT
0µs MIN
P1.7 (I)
P1.6 (I)
P1.5 (I)
P1.0 (I)
200µs MAX
Figure 10. Read Byte
Rev. 0 | Page 11 of 12
10457-010
1µs MIN
AN-1139
Application Note
BYTE PROGRAM/BYTE READ PROGRAM FLOW
The sequence shown in Figure 11 assumes a fully erased part. If a byte location is not in an erased state, it may not program correctly.
PROG ADDRESS
BYTE PROG/READ
≥2
1
Figure 11. Byte Program/Read Sequence
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AN10457-0-1/12(0)
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10457-011
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