ECE351 Digital Systems Design, Spring 2016
Lab 1
For all labs in ECE351:
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Use a Digilent Basys2 board with Xilinx ISE 14.7 and ADEPT 2
Set the VHDL version to 200X to agree with syntax and semantics in the text (the
default is the older VHDL-93).
Follow the general design and implementation process using Xilinx ISE
WebPACK:
1. Capture the design by schematic editor or VHDL code.
2. Create Tesh Bench VHDL code and run a debug/verify simulation.
3. Synthesis/Map maps the design onto the CLBs and other functionalities that
exist on the Spartan3E FPGA (the “FPGA architecture primitives”)
4. ISE PlanAhead lets you create your User Constraint File (.ucf) to employ the
hardwired pins on the Basys2 board for FPGA I/O including the clock
5. Place/Route figures out where on the FPGA each primitive block goes and
how to connect them (the specific CLBs to be used and what logic each must
implement, and how these CLBs must be I/O connected on the Spartan3E).
6. Generate programming file (.bit) to be uploaded to the Basys2 board via
ADEPT.
Task 1: Write VHDL code, implement on Basys2 board, and verify correctness for the
(7,4) Hamming code. (60%)
Denote the bit locations left to right in the Hamming (7,4) code by 1 through 7. In a
Hamming code, the parity bits are placed at locations 2 n for n=1,2,3… and data bits are
placed at all other locations like the following:
Hamming codes are single error-correcting codes which can detect and correct single
errors that change one bit from 0 to 1 or from 1 to 0. The efficiency is the ratio of number
of data bits to total number of bits, so the (7,4) code has the efficiency of 4/7=0.57 and
the (11,7) code has better efficiency 7/11=0.64. Parity bits are at locations that are powers
of 2. A parity bit is XOR of bits in locations with 1 in binary location number.
Example: for the (11,7) code, the parity bits are located at positions 1,2,4,8.
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P1 encodes locations 3,5,7,9,11. (the parity bit at P1 is XOR of locations
3,5,7,9,11).
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P2 encodes locations 3, 6, 7, 10, 11.
P4 encodes locations 5,6,7.
P8 encodes locations 9, 10, 11.
Implement a Hamming code encoder/decoder for the (7,4) code that has 4 data bits at
locations 3,5,6,7 and 3 parity bits at locations 1,2,4. Use Basys2 board switches 7-1 to
input data/parity bits, use switch 0 for input enc, and use LEDs 2-0 to display computed
parity bits. The following requirements should be met:
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Input enc=’1’ means encode, so compute and display the parity bits for the 4
input data bits at locations 3,5,6,7.
Input enc=’0’ means decode, so compute and display the error symdrome for the
7 input bits.
Include in-line documentation that defines all ports, signals, etc, in your design.
Task 2: Extend your (7,4)-Hamming encoder/decoder VHDL code above to use a 7segment display on the Basys2 board to display the location of an error in the decode
mode. (40%)
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If enc=’0’, then display the computed error syndrome as a single integer in the
range of 0-7 where 0 denotes “no error detected”.
If enc=’1’, then display E for “encode”.