AN ABSTRACT OF THE THESIS OF
Kevin A. Stewart for the degree of Master of Science in Electrical and Computer
Engineering presented on February 13, 2015.
Title: Al-In-Sn-O Thin-Film Transistors
Abstract approved:
John F. Wager
The aim of the research undertaken for this thesis was to develop a new highperformance amorphous oxide semiconductor (AOS) for use as a channel layer in
a thin-film transistor (TFT). AOS TFTs offer higher electron mobility than the es­
tablished amorphous silicon based technology. A new channel material comprised
of aluminum indium tin oxide (AITO) was designed and thin films were deposited
via sputtering. AITO thin films have an excellent amorphous phase stability up to
725 °C. The effect of using ultra-thin channel layers was investigated. The turn-on
voltage VON tends to strongly increase below a channel thickness of ∼12 nm, allow­
ing for the realization of enhancement-mode TFTs. Enhancement-mode TFTs with
a channel thickness of 5-10 nm and a mobility of µF E = 15 − 18 cm2 V −1 s−1 , drain
current on-to-off ratio of IDON −OF F = 107 , and a sub-threshold swing of S = 0.2 V /dec
were achieved.
©
Copyright by Kevin A. Stewart
February 13, 2015
All Rights Reserved
Al-In-Sn-O Thin-Film Transistors
by
Kevin A. Stewart
A THESIS
submitted to
Oregon State University
in partial fulfillment of
the requirements for the
degree of
Master of Science
Presented February 13, 2015
Commencement June 2015
Master of Science thesis of Kevin A. Stewart presented on February 13, 2015.
APPROVED:
Major Professor, representing Electrical and Computer Engineering
Director of the School of Electrical Engineering and Computer Science
Dean of the Graduate School
I understand that my thesis will become part of the permanent collection of Oregon
State University libraries. My signature below authorizes release of my thesis to any
reader upon request.
Kevin A. Stewart, Author
ACKNOWLEDGEMENTS
I would like to thank Dr. John Wager for giving me the opportunity to work on this
project and for the continued support and guidance during my graduate education.
This work would not have been possible without my project partner Vasily Gouliouk.
I would like to thank Vasily for the fabrication of the sputter targets, countless
XRD/XRR measurements, helping out with the device fabrication and testing, work­
ing together to create a presentation of the research results every month as well as
teaching me a tiny bit of chemistry along the way. Thanks to Dr. Douglas Keszler
for being the co-advisor on the project and bringing in new, innovative ideas.
Thank you to everyone from the Wager group for their technical contributions to
this work as well as making this a pleasant environment to work in. The same is true
for the Conley group and the other folks who work in the office and labs. No mention
of the lab can go without giving a special thanks to Chris Tasker and Rick Presley for
bringing up new tools, keeping the existing tools running and their great hands-on
training.
Finally, I would like to thank Dr. Robert Manley and Dr. Darwin Enicks of
the Thin Films Research division of Corning Incorporated and Dr. Ta-Ko Chuang,
formerly with Corning, for their support of this project.
This work was funded by Corning Incorporated.
TABLE OF CONTENTS
Page
1 Introduction
1
2 Background & Literature Review
4
2.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.1 Display Market . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.2 The Reasoning Behind High Mobility Materials . . . . . . . .
2.2 Thin-Film Transistors . .
2.2.1 Device Structure
2.2.2 Operation . . . .
2.2.3 Pixel Circuit . . .
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7
7
9
12
2.3 The Case for AOSs . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.1 Amorphous Phase . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.2 Mobility and Free Carriers . . . . . . . . . . . . . . . . . . . .
13
14
15
2.4 A Brief
2.4.1
2.4.2
2.4.3
17
17
19
20
Overview of AOSs
In-Ga-Zn-O . . .
Zn-O based . . .
In-O based . . . .
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4
4
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3 Experimental Techniques
22
3.1 Fundamentals of Vacuum Technology . . . . . . . . . . . . . . . . . . .
3.1.1 Characteristics of a Vacuum . . . . . . . . . . . . . . . . . . .
3.1.2 Vacuum Systems . . . . . . . . . . . . . . . . . . . . . . . . .
23
23
27
3.2 Thin-Film Transistor Fabrication . . . . . . . . . . . . . . . . . . . . .
3.2.1 RF Magnetron Sputtering . . . . . . . . . . . . . . . . . . . .
3.2.2 Device Fabrication . . . . . . . . . . . . . . . . . . . . . . . .
33
33
38
3.3 Electrical Device Characterization . . . . . . . . . . . . . . . . . . . . .
3.3.1 Transfer Curve Assessment . . . . . . . . . . . . . . . . . . . .
3.3.2 Output Curve Assessment . . . . . . . . . . . . . . . . . . . .
38
39
42
4 Al-In-Sn-O Thin-Film Transistors
44
4.1 Properties of Sputtered Thin Films . . . . . . . . . . . . . . . . . . . .
45
4.2 Influence of Deposition Pressure on TFT Performance . . . . . . . . . .
46
4.3 Effect of Ultra-Thin Channel Layers . . . . . . . . . . . . . . . . . . . .
49
TABLE OF CONTENTS (Continued)
Page
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
General Observations . . . . . .
Comparison with IGZO . . . . .
Ultra-Thin TFTs . . . . . . . .
Shelf Life of Ultra-Thin Channel
Oxygen Adsorption Model . . .
. . . . . . .
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Layer TFTs
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49
53
54
56
58
4.4 Evaluation of Passivation Layers . . . . . . . . . . . . . . . . . . . . . .
60
4.5 Source and Drain Metallization . . . . . . . . . . . . . . . . . . . . . .
64
5 Conclusions and Recommendations for Future Work
68
5.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
68
5.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
69
Appendices
A
Additional Al-In-Sn-O Thin Film Data . . . . . . . . . . . . . . . . . .
Bibliography
72
73
75
LIST OF FIGURES
Figure
Page
2.1 Past and estimated total market share for LTPS and Oxide TFTs.
As of 2013 the market is dominated by a-Si:H (not explicitly shown),
but LTPS and Oxide TFT technology are projected to take a growing
market share. Oxide TFT production capacity is expected to overtake
LTPS capacity by 2016. Figure reproduced from Ref. [1]. . . . . . . .
5
2.2 The four basic TFT structures commonly employed. The naming
scheme refers to the position of the gate electrode (top/bottom) and
the plane of the source and drain regions in reference to the channel
(coplanar/staggered). . . . . . . . . . . . . . . . . . . . . . . . . . . .
8
2.3 A slightly modified staggered bottom gate TFT structure which is
typically used in mass-production. Modifications include the tapered
sidewalls, etch stop layer, and passivation layer. . . . . . . . . . . . .
9
2.4 Energy band diagrams for a metal-insulator-semiconductor (M-I-S) ca­
pacitor. The n-type semiconductor is (a) initially at flat-band (ideally),
(b) depleted when a negative bias is applied, and (c) is accumulated
when a positive bias is applied. . . . . . . . . . . . . . . . . . . . . .
11
2.5 A simple circuit that can be employed in an AMOLED display. T 1 is
a switching transistor, T 2 is a driving transistor, and Cst is a storage
capacitor. Figure reproduced from Ref. [2]. . . . . . . . . . . . . . . .
12
2.6 Schematic illustration of orbitals for ionic and covalent bonding in a
crystalline and an amorphous structure. In silicon (covalent bonding)
precise alignment of bonds in a crystalline phase is required in order
to obtain enough overlap to achieve high mobility. In an AOS (ionic
bonding) there is sufficient overlap between orbitals, i.e., an electron
pathway, even in the amorphous phase. . . . . . . . . . . . . . . . . .
16
2.7 The portion of the periodic table proposed for selecting AOS cations.
As, Cd, Hg, Tl, and Pb are usually not used due to their toxicity. Ag
and Au are costly. Figure adapted from Ref. [3, 4]. . . . . . . . . . .
18
3.1 Physical mechanisms that increase the gas pressure in the system are
permeation, diffusion, and desorption (outgassing). Leaks can be cate­
gorized into internal leaks through a valve, virtual leaks, and real leaks.
Figure created with data from Ref. [5]. . . . . . . . . . . . . . . . . .
24
LIST OF FIGURES (Continued)
Figure
Page
3.2 Different stages during pumpdown. Initially, the pressure decays quickly
(pumping out the gas volume), afterwards other mechanism dominate
the gas load in the order of desorption, diffusion, and permeation. Fig­
ure reproduced from Ref. [5] with modifications. . . . . . . . . . . . . 27
3.3 Block diagram of a load-locked high vacuum system. The main cham­
ber is typically equipped with a single gun and corresponding RF gen­
erator/power supply for a sputtering system. . . . . . . . . . . . . . .
29
3.4 Pressure ranges of vacuum pumps and gauges utilized in the CPA.
The sputtering system is equipped with two rotary vane (oil-sealed
mechanical) pumps and one diffusion pump, as well as two thermo­
couple, one capacitance manometer, and one hot cathode ionization
(Bayard-Alpert) gauge. . . . . . . . . . . . . . . . . . . . . . . . . . .
30
3.5 High vacuum pump and high vacuum pressure gauge utilized in the
CPA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
32
3.6 The sputtering process. . . . . . . . . . . . . . . . . . . . . . . . . . .
34
3.7 Cross section of a magnetron sputter target. . . . . . . . . . . . . . .
37
3.8 Comparison of various carrier mobilities calculated from the same trans­
fer curve (transfer curve shown in Fig. 3.9). . . . . . . . . . . . . . .
41
3.9 Transfer curve with illustrations of VON , S, and IDON −OF F ratio. . . . .
42
3.10 Output curve of an AOS TFT fabricated in this work (corresponding
transfer curve shown in Fig. 3.9). . . . . . . . . . . . . . . . . . . . .
43
4.1 Grazing incidence x-ray diffraction (GIXRD) data for an AITO thin
film. Thin films annealed at temperatures between RT and 800 °C. .
45
4.2 Tauc plot for an AITO thin film. . . . . . . . . . . . . . . . . . . . .
46
4.3 Summary of device performance for TFTs with 20 nm thick AITO
channel deposited under a 95:5 Ar/O2 atmosphere with varied depo­
sition pressures of 1, 2.5, 5, and 8 mTorr. Each point is an average of
three TFTs on the same substrate. . . . . . . . . . . . . . . . . . . .
48
4.4 Sub-threshold swing trends for AITO TFTs. . . . . . . . . . . . . . .
50
LIST OF FIGURES (Continued)
Figure
Page
4.5 Field-effect mobility trends for AITO TFTs. . . . . . . . . . . . . . .
52
4.6 Turn-on voltage trends for AITO TFTs. . . . . . . . . . . . . . . . .
53
4.7 Comparison of AITO and IGZO TFT data for VON and S. Devices for
each AOS are processed with a fixed set of optimized process parame­
ters of 95:5 Ar/O2 and TA = 350 °C for AITO, and 90:10 Ar/O2 and
TA = 400 °C for IGZO. The IGZO data is from Ref. [6]. . . . . . . . .
54
4.8 TCAD simulation shows how a normally depletion-mode TFT can be
improved to have a near-zero turn-on voltage by decreasing the channel
thickness from that of the standard thickness of 50 nm to an ultra-thin
thickness of 5 nm. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
55
4.9 The channel layer is obtained by sputtering in pure argon and annealing
at 310 °C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
56
4.10 Unpassivated, ultra-thin TFTs stored at lab atmosphere. Transfer
curves in (a) and (b) show two starkly different behaviors on the day
of fabrication, but are very similiar, and strongly improved overall per­
formance, after aging. . . . . . . . . . . . . . . . . . . . . . . . . . . .
57
4.11 Oxygen adsorption on the back surface of an AOS TFT. . . . . . . .
58
4.12 Energy band diagram of unpassivated AITO TFTs with a channel layer
thickness of 50 and 5 nm. . . . . . . . . . . . . . . . . . . . . . . . .
59
4.13 50 nm AITO TFTs (channel annealed at 300 °C) with 100 nm passi­
vation layers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
62
4.14 Transfer curve (a) of an AITO TFT annealed at 200 °C , as well as
corresponding mobility (b) and output (c) curves. Transfer curve of a
ZTSO-passivated TFT showing the ‘break-in’ effect (d). . . . . . . . .
63
4.15 Source/drain metallization of AITO TFTs. . . . . . . . . . . . . . . .
67
LIST OF TABLES
Table
Page
3.1 Mean free path (MFP), monolayer (ML) formation time, and corre­
sponding vacuum level, range, and flow regime for three different pres­
sures. The chosen values of 760, 1 × 10−3 , and 1 × 10−7 Torr equate to
atmospheric pressure, approximately sputter deposition pressure, and
near base pressure, respectively. . . . . . . . . . . . . . . . . . . . . .
26
3.2 Summary of incremental, average, field-effect, effective, and saturation
mobility equations. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40
4.1 Summary of AITO thin film properties. . . . . . . . . . . . . . . . . .
46
4.2 Summary of deposition pressures and resulting densities of as deposited
20 nm thick thin films. The density estimate is obtained from XRR.
The ideal density of AITO is 6.84 g/mL. . . . . . . . . . . . . . . . .
47
4.3 Summary of an AITO metallization study. Six TFTs (2 substrates à
3 TFTs) for each of the metals Al, Ag, Au, Cr, AMTF, and Mo are
tested three successive times. They are tested on the day of fabrication
(day 0), four days later (stability over time), and after a 5 hour anneal
at 200 °C. Note: VON is in V and µF E is in cm2 V −1 s−1 . . . . . . . . .
66
LIST OF APPENDIX FIGURES
Figure
Page
A.1 Sputter deposition for a fixed set of process parameters (50 W, 90:10
Ar/O2 , 5 mTorr, 4 inches source-to-substrate distance) results in a
linear rate of 4 nm/min (from XRR data). . . . . . . . . . . . . . . .
73
A.2 Hall measurements with the Van der Pauw method of 80 and 200 nm
thick AITO films. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
74
A.3 Initially, the mobility (and ION ) decreases over time, but saturates
after about 30 days. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
74
Chapter 1: Introduction
The transistor is arguably the single most important device for any electronic system.
The thin-film transistor (TFT) belongs to the family of field-effect transistors. It
allows for the switching of current between two terminals, the source and drain, via
the field-effect (voltage control) by utilizing a third, capacitively coupled terminal,
the gate electrode. The adjective thin-film, in contrast to bulk, indicates that the
transistor can be fabricated on top of various substrates, notably, on glass. The key
building block of a TFT is the semiconducting channel layer, also called active layer.
One particular class of semiconductors for use as a channel layer are metal oxides.
Initially, metal oxide semiconductors elicited much interest due to their wide band-gap
making them transparent in the visible regime of the electromagnetic spectrum. The
first transparent TFTs (TTFTs) with a zinc oxide (ZnO) channel layer were reported
in 2003 [7, 8]. The ZnO layer was polycrystalline giving rise to grain boundaries
between the crystalline grains making the layer non-homogeneous. Ideally, every
TFT that is purposely fabricated the same way ends up behaving identically. In
part, this led to the development of amorphous oxide semiconductors (AOSs). The
amorphous phase has no long-range order giving AOS thin films excellent uniformity
and smoothness over a large area.
In parallel to these developments was the emergence of the flat-panel display
(FPD) industry. It has been known for some time that the current technology based
2
on hydrogenated amorphous silicon (a-Si:H) TFTs employed in active-matrix (AM)
displays would eventually provide inadequate performance, requiring its replacement.
A key performance metric is the carrier mobility of the semiconductor. For reasons
explained later in this thesis, AOSs offer a carrier mobility more than one order of
magnitude higher than that of a-Si:H. Additionally, AOS thin films can be deposited
via sputtering over a large area. Sputtering is a well established physical vapor
deposition method extensively used in all kinds of thin-film coating applications.
For these reasons, within only a few years TFTs based on AOSs became a viable
candidate for replacing a-Si:H in AM displays such as active-matrix liquid crystal
displays (AMLCDs) and active-matrix organic light emitting diode (AMOLED) dis­
plays. Today, research on AOSs is continuously advancing and first products employ­
ing AOS TFTs have been shipped [9]. The a-Si:H TFT is still the most widely used
technology, but AOSs are competing with other technologies, namely low-temperature
poly-silicon (LTPS) and to a lesser degree organic TFTs, for a larger market share in
next-generation displays.
This thesis deals with the characterization and process optimization of a novel
amorphous oxide semiconductor based on aluminum indium tin oxide (Al-In-Sn-O,
abbreviated herein as AITO). AITO TFTs have been fabricated and characterized.
Chapter 2 provides the motivation for AOS research, gives a background on TFTs,
and briefly reviews the literature related to this work. Chapter 3 describes the ex­
perimental techniques used for fabricating and characterizing thin films and TFTs.
In particular, it gives an introduction to vacuum technology, explains the sputter
deposition process, and I-V testing and parameter extraction of TFT performance
3
metrics. Chapter 4 provides results relating to AITO from initial results to opti­
mizing the processing conditions, and evaluation of potentially suitable passivation
layers and contact metals for AITO TFTs. Chapter 5 summarizes the work and gives
recommendations for future research.
4
Chapter 2: Background & Literature Review
2.1 Motivation
2.1.1 Display Market
Flat-panel displays are becoming ubiquitous in our everyday life. TVs, smartphones,
tablets, and infotainment systems are just a few of an increasing range of devices where
the display plays a central role. New displays offer larger screens, higher resolution,
higher refresh rates, higher color accuracy, and thinner form factor. The aim is for
the viewer to have an immersive viewing experience, the difference between reality
and the media content shown on the screen vanishes.
New material innovation is driven by the adoption of higher resolution AMLCDs
(4K resolution) with higher pixel density (pixel per inch, ppi) and the introduction of
AMOLED displays. The total TFT flat panel display production capacity is expected
to hit 9 million square meters in 2013, and is forecast to grow over the next few years,
as is shown in Fig. 2.1. Note that the secondary x-axis is on a different scale (x10)
meaning that the installed legacy a-Si:H manufacturing lines will keep the largest
market share for the next several years. Although a forecast such as this one is
subject to many unknown factors making it inherently uncertain, it is still worth
pointing out the significant increase in Oxide TFT capacity for the limited data
available from 2011 to 2012.
5
Figure 2.1: Past and estimated total market share for LTPS and Oxide TFTs. As of
2013 the market is dominated by a-Si:H (not explicitly shown), but LTPS and Oxide
TFT technology are projected to take a growing market share. Oxide TFT production
capacity is expected to overtake LTPS capacity by 2016. Figure reproduced from
Ref. [1].
2.1.2 The Reasoning Behind High Mobility Materials
The commonly stated lower limit for carrier mobility for AOS materials to be a
serious contender for a-Si:H replacement is between “anything higher than a-Si:H” to
approximately 10 cm2 V−1 s−1 . There is no real upper limit for the desired mobility as
the higher the mobility, the more leeway there is in designing display circuitry.
One of the key parameters of a TFT is its carrier mobility. The general square-law
relation describing the drain current of a FET is equal to
IDS
2
W
VDS
= µ COX (VGS − VON )VDS −
,
L
2
(2.1)
where µ is the carrier mobility, W is the width of the channel, L is the gate length,
COX is the gate oxide capacitance per unit area, VGS is the gate-source bias, VON is
6
the turn-on voltage of the TFT, and VDS is the drain-source bias.
The on-current ION is defined as the value of IDS in a fully biased/fully-on state.
A higher ION is always desired. The basic parameters for increasing ION are indicated
in Eq. 2.1. Namely, for a given operating voltage (VGS and VDS ) a higher ION can be
achieved by increasing µ, or by increasing the W/L ratio.
To motivate the need for a higher mobility two scenarios are described in the
following. First, the TFT has a higher mobility with all other parameters remaining
unchanged. This results in a higher ION which in turn results in faster switching and,
finally, enables faster refresh rates of the display.
The second scenario is as follows, the TFT has a higher mobility, and ION is
already sufficiently large. Therefore, the W/L ratio can be reduced. This allows the
manufacturer to make the TFT smaller which (a) is a prerequisite step for increasing
the resolution of the display, or (b) results in the TFT taking up less area in the
subpixel (higher aperture ratio, meaning less shadowing by the black matrix) which
results in a wider viewing angle and increases the brightness of the subpixel. If the
higher brightness is not desired, one can in turn dim the backlight or reduce the supply
voltage to the OLED for an AMLCD and AMOLED display, respectively, effectively
reducing power consumption. Additionally, the reduced supply voltage can increase
the lifetime of the OLED as the lifetime of the OLED is a critical issue [10].
Finally, the remaining two possibilities for increasing ION are an increase of COX ,
or a higher supply voltage (VGS and/or VDS ). COX can be increased by using a thinner
gate oxide or by employing a material with a relative dielectric constant larger than
the 3.9 of commonly used silicon dioxide. A higher applied voltage (VGS and/or VDS )
7
is usually not desired as it results in higher power consumption. This is especially a
concern for mobile devices that rely on battery power.
2.2 Thin-Film Transistors
In the following, commonly used TFT structures, the general operation of a TFT,
and their application in a pixel circuit are described. TFTs belong to the class of
field-effect transistors (FET). They are three terminal devices. Namely, the three
electrodes are gate, source, and drain. Additionally, a TFT needs a semiconducting
channel layer and a substrate (typically silicon or glass) to build the device upon. A
current flowing from source to drain can be controlled by biasing the gate electrode
(voltage control).
2.2.1 Device Structure
The four basic possible structures of a TFT are coplanar top gate, coplanar bottom
gate, staggered top gate, and staggered bottom gate, shown in Fig. 2.6. The two
bottom gate structures are sometimes referred to as inverted staggered and inverted
coplanar TFT, respectively.
Each structure has its own advantages and disadvantages. The bottom gate struc­
tures need fewer mask steps and therefore, are easier and cheaper to fabricate. Ad­
ditionally, in a coplanar or staggered bottom gate structure the gate or the gate and
source/drain electrodes, respectively, are already deposited and patterned before the
8
(a) Coplanar top gate
(b) Coplanar bottom gate
(c) Staggered top gate
(d) Staggered bottom gate
Figure 2.2: The four basic TFT structures commonly employed. The naming scheme
refers to the position of the gate electrode (top/bottom) and the plane of the source
and drain regions in reference to the channel (coplanar/staggered).
potentially delicate channel layer is deposited. This avoids exposure of the channel
material to any of the previous processing steps, e.g., the use of certain etchants,
energetic plasmas, and/or elevated temperatures. Furthermore, the channel is not in
direct contact with the glass substrate. Therefore, any negative impact the substrate
might have on device characteristics, e.g., any surface roughness or out-diffusion of
elements like sodium which is used during the glass substrate manufacturing, is miti­
gated. In a top gate structure an (oxide) buffer layer can be used as a barrier between
the substrate and the channel layer [11].
In a top gate device the channel layer is exposed on a planar surface. This is helpful
for excimer laser annealing and source/drain doping via ion-implantation which is why
the coplanar top-gate structure is typically used for LTPS TFTs.
For manufacturing and use in a commercial product, where reproducibility and
reliability are crucial, several changes need to be made to the basic TFT structure. A
9
staggered bottom gate TFT with an etch stop layer is shown in Fig. 2.3. It has tapered
sidewalls for better step coverage [12], and a passivation layer to reduce degradation
of the channel due to ambient conditions (e.g., gas adsorption). The AOS channel
layer can be very sensitive to etchants. The etch stop layer aids in protecting the
channel during source/drain patterning [13]. A TFT without an ESL is often called
a back channel etch (BCE) type structure and is typically employed in a-Si:H TFTs.
Because it is a less complex structure, saving one photolithography mask and PECVD
step, the BCE structure is a topic of current AOS TFT research [14].
Figure 2.3: A slightly modified staggered bottom gate TFT structure which is typi­
cally used in mass-production. Modifications include the tapered sidewalls, etch stop
layer, and passivation layer.
2.2.2 Operation
TFTs are accumulation-mode devices meaning the conducting channel is formed
by majority carriers, in contrast to the ubiquitous metal-oxide-semiconductor fieldeffect transistor (MOSFET) which forms an inversion channel (minority carriers).
Commonly, the desired TFT behavior for application in the display backplane is
enhancement-mode (normally-off) operation. The idealized enhancement-mode oper­
10
ation with flat-band conditions is described in the following section.
In the off-state (VGS ≤ 0) the channel is nonconducting, as shown in Fig. 2.4(a)
and 2.4(b), and no current (ideally) can flow between source and drain. By applying
a positive bias (VGS > 0) electrons are accumulated at the insulator-semiconductor
interface and a thin, conducting accumulation region forms in the semiconductor.
As a consequence, current can flow from source to drain and the transistor is in the
on-state.
For a small applied drain voltage, an increase in VDS results in a linear increase in
IDS (pre-saturation). With a further increase in VDS beyond VGS − VT , the channel
is pinched-off at the drain and IDS saturates (saturation region).
11
(a) Equilibrium (flat-band condition)
(b) Depletion
(c) Accumulation
Figure 2.4: Energy band diagrams for a metal-insulator-semiconductor (M-I-S) ca­
pacitor. The n-type semiconductor is (a) initially at flat-band (ideally), (b) depleted
when a negative bias is applied, and (c) is accumulated when a positive bias is applied.
12
2.2.3 Pixel Circuit
A prime application of a TFT is in the active-matrix (backplane) of a display. In an
AMLCD, the TFT adjusts the brightness of the pixel by controlling the orientation
of the liquid-crystal which transmits light coming from the backlight. In contrast, in
an AMOLED display the TFT adjusts the brightness of the pixel by controlling the
current passing through the OLED. Attached to each (sub)pixel is a pixel circuit. One
of the simplest circuits consisting of 2 transistors and 1 capacitor (2T1C) is shown in
Fig. 2.5.
Figure 2.5: A simple circuit that can be employed in an AMOLED display. T 1 is a
switching transistor, T 2 is a driving transistor, and Cst is a storage capacitor. Figure
reproduced from Ref. [2].
A circuit with the fewest devices and lines is almost always desired as it takes
up less area and is essential for achieving higher pixel density (ppi). However, fre­
quently more complex circuits must be used to compensate for non-uniformity and
degradation of the TFT, e.g., the use of a 5T2C circuit or even the use of an optical
feedback circuit employing a photo-transistor (photo-detector) [15]. The driving TFT
13
in an AMOLED display is particularly sensitive to non-uniformity and degradation.
A shift in the turn-on voltage can make a significant impact on the resulting drain
current that is then supplied to the OLED. With a lower current the luminescence of
the OLED is reduced, which results in brightness variation across the display.
In contrast, AMLCD operation involves a voltage-controlled technology so that
no driving TFT is required in the pixel circuit. The requirements for uniformity and
stability are not as stringent in an AMLCD as in an AMOLED display.
2.3 The Case for AOSs
AOSs have larger mobilities than that historically expected from an amorphous mate­
rial. The advantages of the amorphous structure and the contribution of larger ionic
radius metal cations to the high mobility of AOSs are discussed in more detail in the
following sections.
But first consider two advantages that can be mainly attributed to the large band
gap typically found in an AOS. The large band gap makes an AOS transparent to
the visible portion of the electromagnetic spectrum. A typical band gap of 3 eV
corresponds to a wavelength of 414 nm. Even though an AOS has a large band
gap, it is not always completely transparent. This can be attributed to absorption
in the band tail states and/or trap states, leading to a slightly opaque appearance.
Nonetheless, AOSs are very suited for transparent TFTs (TTFTs) and transparent
electronics in general [16].
Another benefit of the large band gap is the low leakage current. An AOS is a
14
unipolar material in which inversion (hole conduction) is difficult or impossible to
achieve. Thus, off-current in an AOS is very low since inversion does not occur.
The low leakage current compared to competing technologies helps in reducing power
consumption, a factor especially advantageous in battery powered mobile devices.
Additionally, engineers from Sharp Corp. [17] state that the lower leakage current
aids in higher charge retention. Thus, the pixel needs to be refreshed less often,
which means that drive signals for the TFT can be interleaved with touch detection
cycles, thereby improving the sensitivity of the touch screen that is typically a layer
above the display on a mobile device.
2.3.1 Amorphous Phase
An important advantage of an amorphous material for use as a channel layer in
a TFT compared to a polycrystalline material is the absence of grain boundaries.
Grain boundaries can be the cause of scattering during electron transport. They can
also give rise to uniformity/instability issues. An amorphous material can usually be
prepared at a lower processing temperature.
An oxide with an amorphous phase or a highly disordered microstructure can be
achieved by selecting two or more cations having different oxide crystal structures,
thereby resulting in a frustration of the lattice. Specifically, the oxides of three typ­
ically used cations, namely indium oxide (I n2 O3 ), zinc oxide (Z nO), and tin oxide
(S nO2 ), and one that is employed in this work, aluminum oxide (Al2 O3 ) all have dif­
ferent crystal structures. Their most common crystal structure (other structures are
15
possible) is cubic mineral bixbyite, hexagonal wurtzite, tetragonal rutile structure,
and mineral corundum, respectively [16, 18].
An amorphous phase is metastable. Depending on the specific system and how
it is synthesized IGZO and other AOSs remain amorphous until around 500 °C to
700 °C. Beyond that temperature, crystallization and/or phase separation starts to
occur.
2.3.2 Mobility and Free Carriers
It was stated at the beginning of this section that AOSs have a higher mobility
than what was commonly expected from an amorphous material. This expectation
stems mainly from comparison to silicon, the most prominent semiconductor. The
electron mobility of silicon decreases from about 1500 to about 1 cm2 V−1 s−1 when
going from single crystalline silicon to hydrogenated amorphous silicon. Silicon forms
covalent bonds. These bonds are formed with highly directional sp3 orbitals. It has
been established that for a high mobility there needs to be a large overlap between
orbitals. For silicon precise orbital overlap is only possible in an ordered or, more
specifically, in a crystalline structure [19].
An AOS forms more ionic bonds. Its conduction band is derived from large spher­
ical s orbitals. Directional order is not needed to have sufficient overlap between
orbitals since the ionic radius of constituent cations is so large. Bonding in a cova­
lent or an ionic semiconductor is illustrated in Fig. 2.6. It has been shown that the
mobility of crystalline and amorphous IGZO is nearly the same [20], as expected for
16
ionic bonding using cations with large ionic radiis.
(a) Crystalline covalent semiconductor
(b) Crystalline ionic semiconduc­
tor
(c) Amorphous covalent semicon­
ductor
(d) Amorphous ionic semiconduc­
tor
Figure 2.6: Schematic illustration of orbitals for ionic and covalent bonding in a crys­
talline and an amorphous structure. In silicon (covalent bonding) precise alignment
of bonds in a crystalline phase is required in order to obtain enough overlap to achieve
high mobility. In an AOS (ionic bonding) there is sufficient overlap between orbitals,
i.e., an electron pathway, even in the amorphous phase.
The conduction mechanism and the free carrier concentration in an AOS mate­
rial are strongly linked to its defect chemistry. Oxygen vacancies act as a carrier
generation site. Defect creation of an oxygen vacancy can be expressed as,
×
OO
1
VO·· + 2e + O2 (g),
2
(2.2)
17
×
is a neutrally charged oxygen on an oxygen lattice site, VO·· is a positively
where OO
charged vacancy on an oxygen site, 2e are two mobile electrons, and 12 O2 (g) is a
gaseous oxygen molecule stemming from the now unoccupied lattice site (vacancy).
The carrier concentration in an AOS channel layer needs to be tightly controlled as
it has a strong impact on the conductivity and turn-on voltage of the TFT. Incorporat­
ing elements like gallium or hafnium (less common), or increasing the oxygen partial
pressure during deposition has shown to decrease the carrier concentration [21, 22].
However, there seems to exist a trade-off between high mobility (high VO concentra­
tion) and good stability (low VO concentration).
2.4 A Brief Overview of AOSs
One of the first reports on AOSs was published by H. Hosono et al. in 1996 [23]. The
oxides AgS bO3 , C d2 GeO4 , and C d2 P bO4 were investigated. It was found that these
materials exhibited a relatively large Hall mobility, µH all ≈ 10 cm2 V −1 s−1 . TCOs are
closely related to AOSs and had been reported more than a decade earlier [24]. The
difference is that TCOs like In2 O3 :Sn (ITO) are typically polycrystalline and have
too many mobile carriers to be used as a semiconducting channel layer for a TFT.
2.4.1 In-Ga-Zn-O
Returning to the report from H. Hosono et al. [23], a part of the periodic table of
elements was suggested for selecting cations for the design of an AOS, as shown in
18
Fig. 2.7. Ga, Zn, In, and Sn are the most commonly used cations. Zn, In, and Sn are
thought of as mobility enhancers (large isotropic s orbitals - high dispersion - high
mobility). Ga is known to act as a carrier suppressor having a higher oxygen bonding
energy than the other cations thereby reducing the number of oxygen vacancies, but
at the same time Ga tends to decrease mobility.
Figure 2.7: The portion of the periodic table proposed for selecting AOS cations. As,
Cd, Hg, Tl, and Pb are usually not used due to their toxicity. Ag and Au are costly.
Figure adapted from Ref. [3, 4].
The fabrication of single-crystalline IGZO TFTs with a high on-to-off ratio of
IDON −OF F ≈ 106 and a mobility of µF E ≈ 80 cm2 V −1 s−1 was published in 2003 [25]. A
120 nm thick IGZO layer was deposited on a single-crystal yttria-stabilized zirconia
(YSZ) substrate by pulsed laser deposition (PLD). This was followed by thermal
annealing at 1400 °C for 30 min resulting in a single crystalline phase. To complete
the TFT structure an 80 nm thick amorphous HfO2 layer and an ITO layer were used
to form the gate insulator and source, drain, gate electrodes, respectively. Along
with the good electrical properties the reported TFTs had an optical transmittance
19
of > 80 %.
Only one year later, the first amorphous IGZO TFT was reported from the same
group [26]. The TFTs were fabricated on a flexible substrate (polyethylene tereph­
thalate, PET), the IGZO channel layer was deposited by PLD, and a 140 nm thick
Y2 O3 layer was used as a gate insulator. The devices exhibited an on-to-off ratio
of IDON −OF F ≈ 103 , a mobility of µF E ≈ 6 cm2 V −1 s−1 , and a threshold voltage of
VT = 1.6 V .
Since then, the research on amorphous IGZO has been a very active field of re­
search and TFTs with mobilities of µF E = 10−50 cm2 V −1 s−1 have been reported [27].
Also, successful TFTs have been made with several other channel layers using the same
class of materials such as IGO, ZTO, ITO, IZO, IZTO, or IHZO [19, 27].
2.4.2 Zn-O based
In 2003, Hoffman et al. reported on the fabrication of a crystalline ZnO transparent
TFT [7]. The ZnO channel layer was deposited via ion beam sputtering and subse­
quently annealed at 600-800 °C. Glass, ATO, and ITO were used as a substrate, gate
insulator, and source, drain and gate electrodes, respectively. The devices exhibited
an on-to-off ratio of IDON −OF F ≈ 107 , a mobility of µF E ≈ 1.4 cm2 V −1 s−1 , and a
threshold voltage of VT ≈ 15 V . In the same year there were two more publications
on ZnO TFTs with channel layers deposited by RF magnetron sputtering [28], and
mobilities as high as µF E = 7 cm2 V −1 s−1 at a lower processing temperature of <
300 °C [29]. An amorphous phase can be achieved by incorporating S n into the ZnO
20
layer with a ZnO:SnO2 molar ratio of 1:1 [30]. The ZTO TFTs showed good electrical
performance with an on-to-off ratio, mobility, and turn-on voltage of IDON −OF F ≈ 107 ,
µF E ≈ 10 cm2 V −1 s−1 , and VON ≈ 5 − 15 V , respectively, for devices annealed at
300 °C.
A new method for realizing Zn-O based AOSs was proposed by researchers from
Applied Materials in 2009 [31], with more recent work in Ref. [32]. They contend that
a barrier for electron transport may be formed in ternary and quaternary oxides such
as ZTO or IGZO. As a consequence, a single cation is used, Zn, and lattice frustration
needed for an amorphous phase is achieved on the anion side by using two cations,
oxygen and nitrogen. In 2013, ZnON devices have been reported with an on-to-off
ratio of IDON −OF F ≈ 108 , a mobility of µSAT ≈ 40 cm2 V −1 s−1 , a threshold voltage of
VT ≈ 5 V , and a sub-threshold swing of S ≈ 1.2 V /dec [33].
2.4.3 In-O based
Indium oxide (I n2 O3 ) is well known for its high conductivity and its use as a TCO.
TFTs fabricated using a polycrystalline In2 O3 [34] or ITO [35] channel layer offer a
high mobility µF E > 50 cm2 V −1 s−1 , but are depletion-mode devices with a turn-on
voltage VON < −30 V . The strongly negative VON originates from the fact that
the carrier concentration in the active layer is very high. As a result, the goal for a
suitable TFT is to keep the high mobility associated with In2 O3 , but to decrease the
carrier concentration in order to achieve a VON close to zero.
In the literature, two ways have been shown to decrease the carrier concentration.
21
One approach involves the incorporation of Ga into the channel layer, resulting in
the In-Ga-O system (oftentimes combined with a third cation such as Sn or Zn).
Secondly, the formation of a double channel layer with a thin, highly conductive layer
(e.g., ITO or IZO) and a thicker layer (e.g., IGZO or AIZO) with a lower carrier
concentration to set VON [21, 35, 36, 37]. One approach for trying to improve the
former method is to replace Ga with Al.
Aluminum has a higher oxygen bonding energy than Ga [38] and, therefore, is ex­
pected to work even better in decreasing the carrier concentration. The hope is that
a smaller content of Al (compared to Ga) is required, resulting in a minimized degra­
dation of mobility. In 2009, a group from the Korea Advanced Institute of Science
and Technology (KAIST) has demonstrated solution-processed polycrystalline AIO
TFTs with an on-to-off ratio, mobility, and sub-threshold slope of IDON −OF F ≈ 108 ,
µSAT = 19.6 cm2 V −1 s−1 , and S = 0.3 V /dec, respectively [39]. TFTs were fabricated
on a S iO2 /S i substrate and the metallorganic precursors were spin coated and an­
nealed at 350 °C for 2 h in air. Amorphous AIO TFTs annealed at 300 °C showed
significantly worse behavior with a mobility of µS AT = 1.1 cm2 V −1 s−1 . In 2010,
the same group reported on solution-processed amorphous AITO TFTs where the de­
vices with optimized Al content had an on-to-off ratio of IDON −OF F ≈ 107 , a mobility of
µF E = 13.3 cm2 V −1 s−1 , and a sub-threshold swing of 1.01 V /dec [40]. Furthermore,
reports exist of TFTs with similar cation compositions, such as amorphous ATZIO,
with excellent device characteristics [41].
22
Chapter 3: Experimental Techniques
TFTs are fabricated in a cleanroom environment at the Materials Synthesis and Char­
acterization laboratory at Oregon State University. The layer stack of the TFTs is
deposited by means of physical vapor deposition (PVD) techniques. The channel layer
and source/drain contacts are deposited via radio frequency (RF) magnetron sput­
tering and thermal evaporation, respectively. These PVD processes are conducted
under a vacuum atmosphere. Thus, a basic understanding of the characteristics of
a vacuum and the basic functioning of a vacuum system is very helpful. The first
part of this chapter deals with this. The two deposition systems employed are a CPA
sputtering system and a Veeco thermal evaporator. The general working principles
are explained in the following.
The fabrication of a TFT is followed by electrical testing. Different test setups
and settings of the tools used (e.g., the semiconductor parameter analyzer) can in­
fluence the measurement. Several key parameters (figures of merit) are calculated
to assess the device performance and to judge the capability of a novel material.
When comparing various results within the OSU group and across research groups
internationally the testing methods must be known. As a consequence, the testing
setup and the basic equations of carrier mobility, drain current on-to-off ratio, and
sub-threshold swing are described in this chapter.
23
3.1 Fundamentals of Vacuum Technology
3.1.1 Characteristics of a Vacuum
The term vacuum describes a volume void of matter. Even the most advanced vacuum
technology cannot evacuate an enclosed space to complete emptiness. Typically, the
term vacuum refers to any gas pressure below the atmospheric level. PVD methods
such as magnetron sputtering and thermal evaporation are vacuum processes. At
atmospheric pressure the source or target material would not reach the substrate,
because there are too many collisions with gas molecules from the air. Furthermore,
atmospheric gas is a potential source of contamination. Deposition under vacuum
results in a much purer film.
There are several causes that limit the lowest achievable pressure in a real vacuum
chamber, illustrated in Fig. 3.1. Permeation, diffusion, and desorption (outgassing)
are physical mechanisms. All three are sometimes collectively referred to as outgassing
in a general sense. During desorption gas detaches from the chamber walls that has
previously been adsorbed on the surface, thus increasing the pressure of the system.
Diffusion involves diffusion of gas through a material (chamber wall), followed by
desorption. Permeation is a three-stage process that consists of adsorption of a gas
molecule on the high pressure side, diffusion through the chamber wall, and finally,
desorption from the interior wall [42]. Additionally, there are leaks which can be
categorized into internal leaks, virtual leaks, and real leaks. An internal leak can
be caused by a pressure differential across an imperfect valve. Gas trapped in, e.g.,
a screw thread can result in it being slowly released (virtual leak). Lastly, there is
24
the possibility of particles moving the opposite direction, from the pump into the
chamber (backstreaming).
INTERNAL
LEAK
PERMEATION
VIRTUAL
LEAK
DIFFUSION
REAL LEAK
DESORPTION
BACKSTREAMING
PUMP
Figure 3.1: Physical mechanisms that increase the gas pressure in the system are
permeation, diffusion, and desorption (outgassing). Leaks can be categorized into
internal leaks through a valve, virtual leaks, and real leaks. Figure created with data
from Ref. [5].
A vacuum is categorized into pressure ranges of low (rough), medium, high (some­
times subdivided into high/very-high), and ultra-high vacuum. Frequently, vacuum
equipment such as pumps and pressure gauges can only cover one or two of the for­
mer mentioned vacuum levels, making it necessary to employ more than one type of
pump/gauge to cover the full range of working and base pressures for a certain appli­
cation. The working pressure refers to the pressure at which the deposition takes place
whereas the base pressure is the lowest pressure achieved in the deposition chamber
after loading the sample and pumping down for a reasonable amount of time.
25
Characteristic properties of a certain vacuum pressure are the mean free path
(MFP), monolayer (ML) formation time, flow regime, gas composition and dominat­
ing physical mechanism limiting pumpdown. The mean free path is the characteristic
length a particle moves between two consecutive scattering events. The MFP for air
at room temperature can be approximated by, [5]
1
5.1 × 10−3 (cm)
MF P = √
≈
.
P (T orr)
2 · π · d2 · n
(3.1)
The MFP at a typical sputter deposition pressure of 5 mTorr is approximately 1 cm.
Furthermore, at a target-to-substrate distance (throw distance) of 10.2 cm (4 inches)
a removed target atom undergoes, on average, 10 collisions before reaching the sub­
strate.
The monolayer formation time is the time it takes one ML to form on a pristine
surface. It is closely related to the impingement rate [43]. A layer can form on the
chamber walls and on the substrate which can cause a slowing down of the pumpdown process and be a source of contamination, respectively. Therefore, it is often
advantageous to increase the deposition rate allowing less time for foreign atoms to
be incorporated into the film. Table 3.1 shows different ML formation times in de­
pendence of pressure assuming a sticking coefficient of one (every impinging particle
sticks to the surface).
Several different flow regimes exist in a vacuum system. The gas can be in a
viscous, intermediate, or molecular state depending on the chamber or pipe diameter
and on the MFP. The length of the MFP in turn depends on the type of gas, tem­
26
Table 3.1: Mean free path (MFP), monolayer (ML) formation time, and corresponding
vacuum level, range, and flow regime for three different pressures. The chosen values
of 760, 1 × 10−3 , and 1 × 10−7 Torr equate to atmospheric pressure, approximately
sputter deposition pressure, and near base pressure, respectively.
Pressure
MFP
ML formation
Vacuum level
Range
Flow regime
760 Torr
1 × 10−3 Torr
1 × 10−7 Torr
0.67 nm
5.1 cm
510 m
2.9 ns
2.2 ms
22 s
Low (Rough)
Medium
High
760 to 1 Torr
1 to 10−3
10−3 to 10−7
Viscous
Knudson
Molecular
perature, and, especially, pressure [44]. The three flows can be distinguished by the
relation
D
,
MF P
where D is the diameter of the pipe. Frequently, the relation
D
MF P
and
the intermediate state are referred to as the Knudson number and the Knudson flow,
respectively. A Knudson number above 100, between 1 and 100, and smaller than 1
corresponds to the viscous, Knudson, and molecular flow regime, respectively [5]. As
can be seen from the Knudson number, in the viscous regime there are many more
collisions between particles compared to the molecular flow, where the MFP is large
and particles dominantly interact with the chamber walls.
Not only does the flow regime change during pumpdown from atmosphere to high
vacuum, but the composition of the gas changes as well. A vacuum system can
be equipped with a residual gas analyzer (RGA) to gather information about the gas
species present. At low vacuum the composition is mostly unaltered from atmosphere.
Going to high vacuum the gas contains an increasing amount of water vapor, up to
between 70 and 90 %, coming from exposed surfaces/chamber walls [44]. In ultra­
high vacuum, hydrogen is the dominant species. The discussed characteristics of a
vacuum: MFP, ML formation time, and flow regime are summarized in Table 3.1.
27
Finally, different gas loads tend to dominate during the pumpdown process, as is
schematically shown in Fig. 3.2. Initially, the gas volume is pumped out relatively
quickly. From there on outgassing, and leaks (not shown), limit the attainable base
pressure. This explains the fact why materials for vacuum applications are carefully
chosen after evaluation of their outgassing and gas permissibility properties.
Figure 3.2: Different stages during pumpdown. Initially, the pressure decays quickly
(pumping out the gas volume), afterwards other mechanism dominate the gas load in
the order of desorption, diffusion, and permeation. Figure reproduced from Ref. [5]
with modifications.
3.1.2 Vacuum Systems
A vacuum system consists of several components. These core components tend to be
very similar across a wide range of physical vapor deposition (PVD) and chemical
vapor deposition (CVD) tools. A block diagram of a typical PVD system is shown in
Fig. 3.3. The heart of the system is the main (or deposition) chamber where the depo­
28
sition takes place. Attached to the main chamber is a high vacuum pump separated
by a high vacuum isolation valve which also acts as a throttle valve. The throttle
valve modulates the throughput of the pump and is thus effectively controlling the
pressure in the chamber. Additionally, the working pressure is controlled by regulat­
ing the flow rate of any process gas admitted into the chamber. The high vacuum
pump will fail if the exhaust is at atmospheric pressure. Therefore, it is backed by
a medium vacuum pump connected via the foreline. The second, smaller chamber is
the load lock which can be a medium vacuum or high vacuum. It is then directly
connected to a medium vacuum pump via the roughing line or set up equivalently to
the high vacuum main chamber with a set of two pumps. The load lock acts as a dou­
ble door entry to the main chamber and prevents particles and contaminants from
getting into the main chamber from atmosphere. Furthermore, its smaller volume
allows it to be pumped down to medium/high vacuum much more efficiently after
the loading of samples at atmospheric pressure. Meanwhile, the main chamber can
stay at medium/high vacuum except for occurrences such as maintenance, change of
target material, etc.
Another essential piece of equipment is the pressure gauge. Typically, the main
chamber has three pressure gauges, one gauge which covers the range from atmo­
spheric pressure to medium vacuum, one that covers the range from medium vacuum
to high vacuum, and a third one that allows the precise pressure measurement at the
working pressure range during the deposition. Furthermore, a number of gauges are
placed at important locations, e.g., at the load lock and foreline to monitor the state
of the system.
29
CAP MAN
CONTROLLER
HI-VAC GAUGE
CONTROLLER
HI-VAC GAUGE
MED-VAC
GAUGE
CONTROLLER
MED-VAC GAUGE
MED-VAC GAUGE
MED-VAC
GAUGE
CONTROLLER
HI-VAC GAUGE
HI-VAC GAUGE
CONTROLLER
MFC
CONTROLLER
MFCs
MATCHING NW
CONTROLLER
SHUT-OFF
VALVES
VENT
VENT
LOAD LOCK CHAMBER
DEPOSITION
CHAMBER
MATCHING NW
MAGNETRON
ROUGHING VALVE
HI-VAC (TURBO)
PUMP
HI-VAC (TURBO)
PUMP
COOLING WATER LINE
RF GENERATOR
FORELINE GAUGES
FORELINE VALVES
CHILLER
FORELINE
GAUGE
CONTROLLER
MED-VAC
(MECHANICAL)
PUMP
FORELINE
GAUGE
CONTROLLER
MED-VAC
(MECHANICAL)
PUMP
Figure 3.3: Block diagram of a load-locked high vacuum system. The main chamber
is typically equipped with a single gun and corresponding RF generator/power supply
for a sputtering system.
30
The workhorse tool used to deposit the AOS thin films in this work is a circuit
processing apparatus (CPA) sputtering tool. Listed in Fig. 3.4 are the types of pumps
P u m p s
and gauges with corresponding pressure ranges specifically used in the CPA.
R O T A R Y V A N E
P re s s u re G a u g e s
V a c u u m
D IF F U S IO N
1 0
T H E R M O C O U P L E
C A P A C IT A N C E M A N O M E T E R
B A Y A R D -A L P E R T IO N IZ A T IO N
-1 0
1 0
-8
1 0
-6
1 0
-4
1 0
-2
1 0
0
1 0
2
P re s s u re (T o rr)
Figure 3.4: Pressure ranges of vacuum pumps and gauges utilized in the CPA. The
sputtering system is equipped with two rotary vane (oil-sealed mechanical) pumps
and one diffusion pump, as well as two thermocouple, one capacitance manometer,
and one hot cathode ionization (Bayard-Alpert) gauge.
The high vacuum oil diffusion pump belongs to the family of momentum transfer
pumps [42]. A schematic structure of the diffusion pump is shown in Fig. 3.5(a).
Oil is vaporized in the heating stage (5) and rises up the chimney in the center.
An oil vapor jet exists through the nozzle (3,4). Gas that diffuses into the inlet of
the pump collides with the vapor jet and receives a downward momentum. Over a
series of stages the gas gets compressed into regions of higher pressure until exiting
31
the exhaust of the pump near the bottom (7). The oil vapor condenses at the watercooled sidewalls (2) and flows downward into the heating stage (5), thus, completing a
full cycle. A major advantage of the diffusion pump is that there are no moving parts
involved. Therefore, the pump can run for a long time without needing service, and
pump maintenance is only needed to replace the oil. The main problem associated
with the diffusion pump is the possibility of oil vapor entering the vacuum chamber
(backstreaming). This can be mitigated by the use of a baffle or a cold trap in front
of the inlet of the pump where oil vapor trying to enter the chamber gets trapped by
sorption/condensation on a cold plate.
The pressure in the high vacuum region is measured with a hot cathode ionization
gauge. There are several implementations that utilize the same fundamental ioniza­
tion mechanism. The CPA is equipped with a Bayard-Alpert gauge. This configura­
tion described by Bayard and Alpert in 1950 is illustrated in Fig. 3.5(b). Electrons
generated by thermionic emission at the hot filament are accelerated towards the grid
by the applied electric field. On the way they collide with gas molecules. These
collisions ionize a fraction of the gas molecules. The positive ions are collected at the
ion collector (Fig. 3.5(b)) and produce an ion current which can be detected with an
ammeter. The ionization gauge measures the gas density and dependent on the gas
species and temperature, provides an indirect reading of the pressure.
32
1
2
3
ION COLLECTOR
4
ELECTRON COLLECTOR
(GRID)
7
5
ELECTRON SOURCE
(HOT FILAMENT)
+30 V
A
+180 V
6
(a) Diffusion pump: 1. Pump inlet; 2.
Water cooling; 3. First stage; 4. Second stage; 5. Pump oil; 6. Heater; 7.
Exhaust/Foreline. Figure reproduced
from Ref. [44].
(b) Bayard-Alpert ionization gauge. Figure re-
produced from Ref. [45].
Figure 3.5: High vacuum pump and high vacuum pressure gauge utilized in the CPA.
33
3.2 Thin-Film Transistor Fabrication
3.2.1 RF Magnetron Sputtering
Sputtering is a thin-film deposition technique and belongs to the class of physical
vapor deposition (PVD) methods [46]. Energetic argon ions (Ar+ ) are accelerated
toward a target. The ions hit the target and physically remove target atoms. The
ejected atoms travel away from the target and deposit on the substrate and chamber
walls. The process is depicted in Fig. 3.6. The argon ions are generated by a type of
plasma called glow discharge. A plasma consists of positive charges (ions), negative
charges (electrons), and neutral gas particles. If a free electron has sufficient kinetic
energy it can ionize or excite an Ar atom. In the event of ionization, an Ar+ ion and a
second electron are generated. The two free electrons can ionize additional Ar atoms
causing a cascading effect. If the energy transferred by the collision between electron
and Ar atom is less than the ionization potential, it will cause a temporarily excited
state of the Ar. When the Ar atom relaxes, it emits a photon. The emitted photon
is the cause of the characteristic glow of the plasma.
The target acts as the cathode and the substrate/chamber walls as the anode.
When a direct current (DC) bias is applied between the target and substrate, the
positively charged ions are accelerated toward the target by an electric field. The
electrons are attracted by the anode. The collection of electrons at the anode com­
pletes the circuit. More electrons need to be generated at the cathode to sustain the
current flow and therefore the plasma. If a metallic target is used, the secondary
electrons are produced during the ion bombardment of the target.
SUBSTRATE (ANODE)
TARGET (CATHODE)
34
Ar+
VRF
AOS
PLASMA
CATHODE SHEATH
ANODE SHEATH
(a) The basic mechanism during sputtering includes the power supply, target,
plasma (glow discharge), substrate, cathode/anode sheath, and process gas
(Ar). Argon ions bombard the target surface and ejected particles from an
AOS target deposit onto the substrate.
Vp
0
ANODE
Vf
CATHODE
(b) A typical voltage distribution from cathode
to anode. Vp is the plasma potential.
Figure 3.6: The sputtering process.
35
Most of the voltage is dropped across the cathode sheath. The location of the
sheaths is shown in Fig. 3.6(a) and 3.6(b). An electron, which has a light mass, is
quickly accelerated away from the cathode, whereas a much heavier ion is accelerated
comparatively slowly towards the target. Thus, the cathode sheath (or dark space)
is predominantly made up of ions and is positively charged. Due to the large electric
field in the sheath the electrons gain kinetic energy more quickly and are more likely
to ionize an Ar atom than to excite it. Therefore, there is very little glow in the
sheath explaining the synonymous term dark space.
Simple DC sputtering is suitable for conducting (metallic) target materials, but
usually not used for semiconducting or insulating targets [46]. DC sputtering with an
insulating target causes charge to build up. Ions hitting the target recombine with an
electron to return to the neutral state. In a conducting target a missing electron can
be easily replenished. However, for an insulating target this is not the case and the
missing electrons lead to positively charging the target surface. The positive charge
on the cathode (target) increases until the potential difference between the cathode
and anode is too small to sustain the glow discharge. In addition, the charge build up
can cause arcing from a charge island/particle to an uncharged region on the target
surface or from the target to ground (e.g., dark space shield) [47].
The solution to deposit semiconducting materials is RF sputtering from a ceramic
target or reactive sputtering with a metallic target. Reactive sputtering offers certain
advantages, but the process is more difficult to control. Technologies have been devel­
oped to solve issues with reactive sputtering such as feedback loop control equipment
to cope with target poisoning and mid-frequency AC, pulsed DC, dual magnetron
36
sputtering, and redundant anode sputtering techniques [48].
The RF magnetron sputtering technique is employed in this work. During one half
of the RF cycle the target has opposite polarity and electrons attracted by the target
diminish any positive charge build up. Only the electrons can move quickly enough
to follow the RF signal. In contrast the ions, because of their larger mass, remain
relatively stationary. This causes a negative self-bias voltage on the target and the
sputtering process occurs as described previously. An impedance matching network
is required to efficiently couple the power from the RF generator to the cathode/glow
discharge. The industry standard for RF sputtering is a frequency of 13.56 MHz.
Disadvantages of RF sputtering are a lower deposition rate compared to DC [49] and
the more complex and expensive RF equipment.
The addition of a magnetron significantly improves the sputtering process. A
magnetron target is shown in Fig. 3.7. Magnets are placed behind the target. The
magnetic field confines/traps electrons close to the target surface. The higher electron
density greatly increases the ionization rate. As a result, the working pressure can be
reduced by about one order of magnitude, improving the transport of the sputtered
species (longer MFP), and greatly increasing the deposition rate.
Areas of preferential sputtering exist due to the confinement of the electrons.
This circular erosion path is called racetrack. The racetrack can cause film thickness
non-uniformity and limits target utilization. The target has to be replaced before
all the material is used up. Planar targets with a scanning magnet and cylindrical,
rotary magnetron and target technologies have been developed to increase target
utilization [50].
37
RACE TRACK
e-
e- e-
e-
e- e-
B-FIELD
TARGET
BACKING
PLATE
DARK SPACE
SHIELD
S
N
S
N
S
N
RF POWER
BAR MAGNET
MAGNETIC SHUNT
Figure 3.7: Cross section of a magnetron sputter target.
A dark space shield is placed in close proximity around the target to avoid sput­
tering surfaces beside the front side of the target, shown in Fig. 3.7. The dark space
shield is grounded (at anode potential) and at a distance less than the sheath re­
gion, thereby preventing a glow discharge to form between the shield and the to be
protected area.
It is important to get rid of the excess heat from the target that develops during
sputtering. A backing plate is needed in particular for a non metallic target. In
this work an AOS target is bound to an aluminum backing plate with a silver epoxy
that is electrically and thermally conductive. The target/backing plate combination
is held in place with a magnetic keeper. Thermal paste facilitates the conductivity
between backing plate and sputter gun. The RF power connectors and the backside
of the target/backing plate are cooled by a water cooling system.
38
3.2.2 Device Fabrication
Fabrication of the thin-film transistors (TFTs) involves the following steps: cleaning
of the substrate, sputtering of the channel layer, thermal furnace annealing, and
evaporation of the S/D contacts. The substrate is a p-type Si wafer with 100 nm
thermally grown silicon dioxide acting as the gate insulator. The bottom of the Si
wafer is coated with gold acting as the gate electrode. Devices are fabricated on 10×15
mm2 coupons and the channel and S/D contacts are patterned via shadow masks.
First, the substrates are cleaned in a sequence of rinses of acetone-isopropanol-DI
water (AID) followed by nitrogen blow gun drying and dehydration on a hot plate
at 200 °C for 30 minutes. Consecutively, the AITO channel layer is deposited in
the CPA sputtering system, the channel is then annealed in a Neytech Qex furnace.
Throughout this work an annealing temperature profile of 2 °C/min ramp up - 2
hour hold at target temperature (e.g., 300 °C) - 2 °C/min ramp down is used. The
typical process for S/D contact formation is evaporated aluminum via the Veeco
Thermal Evaporator. For the thermal evaporation process a couple of aluminum
clips are placed in a wire basket and evaporated via resistive heating under a vacuum
atmosphere.
3.3 Electrical Device Characterization
This section discusses the methods used for testing the TFT and extracting TFT
figure of merits. The devices are tested in a dark box Karl Suss probe station with
a gold plated chuck (common gate contact) and two probes/micromanipulators to
39
make contact to the source and drain of the TFT. An Agilent 4155C seminconductor
parameter analyzer (SPA) is used. Based on past work the typical SPA settings used
in this work are 0.2 V steps in gate voltage, 0.1 seconds delay time, 10 seconds hold
time, and medium integration time.
3.3.1 Transfer Curve Assessment
A transfer curve is defined as the plot of drain current versus gate voltage. The
four main performance metrics of a TFT are turn-on voltage (VON ), mobility (µ),
sub-threshold swing (S), and drain current on-to-off ratio (IDON −OF F ).
The turn-on voltage is defined as the applied gate bias at which the first onset of
conduction above the off-state leakage current occurs.
The carrier mobility is an important performance metric as discussed in section
2.1.2. Several methods for extracting the carrier mobility exist and are summarized in
Table 3.2. Incremental (µI N C ) describes the incremental mobility of carriers injected
into the channel. Average (µAV G ) is the average mobility of all carriers in the chan­
nel. Notably, incremental, average, field-effect, and effective mobility are calculated
from the linear region, in contrast to saturation mobility which is extracted from the
saturation region.
Since,
gm =
∂IDS
∂ VGS
,
VDS →0
(3.2)
40
Table 3.2: Summary of incremental, average, field-effect, effective, and saturation
mobility equations.
Name
Equation
Notes
Incremental
µI N C (VGS ) =
Average
µAV G (VGS ) =
Field-Effect
µF E (VGS ) =
Effective
µE F F (VGS ) =
∂ gd (VGS )
∂ VGS
W
C
L OX
W
L
gd (VGS )
COX (VGS −VON )
gm (VGS )
COX VDS
W
L
W
L
µS AT (VGS ) =
Hoffman model [51]
VDS →0
Very common
VDS →0
gd (VGS )
COX (VGS −VT )
√
Saturation
Hoffman model [51]
VDS →0
∂ IDS
∂(VGS −VT )
1W
C
2 L OX
Common
VDS →0
2
Common; with VGS > VT
and VDS > (VGS − VT )
and
gm
∂gd (VGS )
=
,
∂ VGS
VDS
(3.3)
and under the standard assumptions of gradual channel approximation (GCA), chargesheet model, and depletion approximation the value of the incremental mobility is
equal to the field-effect mobility.
The sub-threshold swing S is the inverse of the slope in the sub-threshold region.
S is a measure of the steepness of the turn-on and defined as [52]
S=
∂ log IDS
∂ VGS
−1
.
(3.4)
A small value of S is desired. It has important implications for the circuit design
41
Figure 3.8: Comparison of various carrier mobilities calculated from the same transfer
curve (transfer curve shown in Fig. 3.9).
as well as for the scaling of the supply voltage. In a Si MOSFET the sub-threshold
current is based on diffusion. Hence, the fundamental lower value of S is limited
by thermionic emission across a potential barrier. Initially, only a small number
of carriers, those with high kinetic energy, in the exponential tail of the MaxwellBoltzmann distribution contribute to the drain current. The lower limit of S can be
derived from [52],
S = ln(10)
kT
q
1+
Cd
COX
with T = 300 K and
Cd
→ 0,
COX
(3.5)
so that
S ≈ 60 mV/dec.
(3.6)
42
To first order, this limit still holds true for an AOS TFT (i.e., conduction is not
dominated by tunneling) even though the potential barrier is not formed by a pn­
junction and there is extensive carrier trapping.
Finally, the drain current on-to-off ratio (IDON −OF F ) is defined as the ratio between
the current flow in the “off”-state and the “on”-state. The ratio is extracted from a
transfer curve with VDS biased in the saturation region.
Figure 3.9: Transfer curve with illustrations of VON , S, and IDON −OF F ratio.
3.3.2 Output Curve Assessment
An output curve is defined as a plot of drain current versus drain voltage. Typically,
a family of curves with constant steps in gate voltage is shown, such as the output
curve in Fig. 3.10. The output curve shows good saturation, meaning ID becoming
43
independent of drain voltage at VD > VDS AT . Additionally, there is a near quadratic
increase of IDS AT with increase in gate voltage showing the desired long-channel
square-law behavior. The output curve can be used to asess if the device performance
is degraded due to series resistance (e.g., a large contact resistance). In the output
curve shown in Fig. 3.10 this is not the case as there is a linear (ohmic) increase in
ID at small drain voltages.
Figure 3.10: Output curve of an AOS TFT fabricated in this work (corresponding
transfer curve shown in Fig. 3.9).
44
Chapter 4: Al-In-Sn-O Thin-Film Transistors
An Al-In-Sn-O (AITO) AOS is designed with the aim of achieving high mobility TFTs.
The cation indium and to some degree tin tends to increase the carrier mobility, but
at the same time increases the carrier concentration. Aluminum functions as a carrier
suppressor, but in turn degrades the mobility. The motivation for the 1:7:2 AITO
composition employed is given in Section 2.4.3.
An AOS target with a cation ratio of 1:7:2 Al/In/Sn is made. The chemical
formula is (Al2 O3 )(I n2 O3 )7 (S nO2 )4 . After some initial reaction/grinding/pressing
cycles with various pellet sizes, a two inch diameter target is mechanically pressed at
room temperature with a force of 10 tons. This is followed by a reaction step at 1400
°C for 24 hours. The target is regrinded and pressed. Finally, the target is sintered in
air at 1500 °C for 24 hours. The chosen temperatures are optimized for this material.
The result is a 2” × 1/4” target that is mechanically strong and has very little powder
on the surface. Before installation into the magnetron sputtering system the target
is bound to a backing plate. After installation and pump down of the main chamber
the target is conditioned in a process called burn-in. During the burn-in the applied
RF power is slowly ramped up from 35 W (enough to create a glow discharge) to 55
W (slightly above the regular deposition power of 50 W) down to 35 W again, all at
a rate of 5 W/hour.
45
4.1 Properties of Sputtered Thin Films
The properties of the sputtered thin films are analyzed. The deposition rate depends
on several parameters including applied power, process gas, pressure, and source­
to-substrate distance. For a fixed set of process parameters (50 W, 90:10 Ar/O2 , 5
mTorr, 4 inches source-to-substrate), the resulting linear deposition rate is 4 nm/min.
The amorphous phase stability is analyzed via grazing incidence x-ray diffraction
(GIXRD). The GIXRD results are shown in Fig. 4.1. The AITO thin film stays
amorphous up to 725 °C characterized by the broad humps. Beyond this crystalliza­
tion temperature (Tx ) phase separation occurs. The tin oxide peaks suggest that tin
oxide grains may form while the aluminum and indium stay in the amorphous phase.
Therefore, AITO does not form a phase-pure (poly)crystalline structure above Tx .
Notably, the amorphous phase stability up to 725 °C is higher than that of many
other reported AOS materials (for comparison, IGZO is typically ∼600 °C).
Figure 4.1: Grazing incidence x-ray diffraction (GIXRD) data for an AITO thin film.
Thin films annealed at temperatures between RT and 800 °C.
Transmission/reflectance spectroscopy is performed. A band gap of ∼3.1 eV is
46
estimated via linear extrapolation from a Tauc plot, as shown in Fig. A.1.
Figure 4.2: Tauc plot for an AITO thin film.
A summary of analytical thin film measurement results is given in Table 4.1.
Table 4.1: Summary of AITO thin film properties.
Value
Technqiue
Available Data
Sputter target
Deposition rate
Amorphous phase
Thin film density
Optical band gap
Carrier concentration
Composition Al/In/Sn
2 inch dia.
∼4 nm/min
Tx ≈ 730 °C
> 90 %
EG ≈ 3.1 eV
N < 1017 cm−3
∼1:7:2
Cold pressed powder
XRR, Profilometry
GIXRD
XRR
Spectroscopy
Hall
EDX
Appendix
Fig. 4.1
Fig. A.1
Appendix
-
4.2 Influence of Deposition Pressure on TFT Performance
The thin film density of the channel layer is an important factor for obtaining high
performance TFT characteristics. It is one of the reasons why a vapor-deposited
47
TFT typically achieves much higher performance than a solution-processed TFT, as
the density of a good PVD film often exceeds > 95 %. In 2008, Jeong et al. [53]
reported an improvement in IGZO density and µF E of 5.50 to 6.27 g/cm3 and 11.4
to 21.8 cm2 V −1 s−1 , respectively. Along with the mobility, the other performance
metrics S, IDON −OF F , and VT improved as well. The increase in density was achieved
by reducing the deposition pressure from 5 to 1 mTorr. It is argued that the lower
pressure reduces the number of scattering events, thus, increasing the kinetic energy
of the incident atoms and leading to improved densification of the film. Additionally,
the film deposited at a lower pressure is reported to have a lower surface roughness
and a smaller trap density.
Table 4.2: Summary of deposition pressures and resulting densities of as deposited 20
nm thick thin films. The density estimate is obtained from XRR. The ideal density
of AITO is 6.84 g/mL.
Pressure
(mTorr)
Density
(g/mL)
% of ideal
1
2.5
5
8
6.83
6.50
6.29
6.30
99.9
95.0
91.9
92.4
In the following, the results from a study on the influence of the deposition pressure
on the performance of AITO TFTs are discussed. The density values are obtained
via a fit to x-ray reflectivity (XRR) data. The ideal density is calculated using the
Archimedes method which is a weighted average of the (ideal) densities of the binary
oxides. From the data shown in Table 4.2, it is evident that the density increases for
a deposition pressure below 5 mTorr, agreeing with the trend seen by Jeong et al.
48
Additionally, the density stays relatively constant when increasing the pressure to 8
mTorr. However, the increase in density, as seen for the as deposited films in Table 4.2,
does not result in an improvement in device performance, for TFTs with an annealed
channel. For TFT channels deposited at 2.5, 5, and 8 mTorr, VON follows a similar
trend with an optimum (closest to zero) at 250 °C, as shown in Fig. 4.3(a). This is
consistent with a maximum in mobility at that temperature, as shown in Fig. 4.3(b).
Good behavior is also achieved at 500 °C. Overall, the TFTs processed at the standard
5 mTorr pressure are similar or slightly better than the devices fabricated at 1 mTorr.
(a) Turn-on voltage (VON ) as a function of an­
nealing temperature (TA ) with varied deposi­
tion pressure.
(b) Mobility (µF E ) as a function of annealing
temperature (TA ) with varied deposition pres­
sure.
Figure 4.3: Summary of device performance for TFTs with 20 nm thick AITO channel
deposited under a 95:5 Ar/O2 atmosphere with varied deposition pressures of 1, 2.5,
5, and 8 mTorr. Each point is an average of three TFTs on the same substrate.
Interestingly, the density increases not only with lower pressure but also with
annealing. For a 5 mTorr thin film the density increases from 91.9 to 98.1 % after an
49
anneal at 500 °C. For a 1 mTorr thin film the density stays relatively constant at 99.9
to 99.3 % after anneal (likely within the error of the measurement) as it is already
very high. This likely explains why there is not a significant improvement of annealed
TFTs fabricated at 1 mTorr. Furthermore, this confirms that the reference point of
5 mTorr (chosen based on past work at OSU) was already very good to begin with.
In conclusion, for AITO the deposition at a pressure lower than 5 mTorr does
not result in much better devices, in contrast to the publication by Jeong et al. for
IGZO TFTs. As a consequence, for the following experiments the deposition pressure
is kept at the standard pressure of 5 mTorr.
4.3 Effect of Ultra-Thin Channel Layers
4.3.1 General Observations
The effect of the channel thickness on the properties of AITO TFTs is investigated.
The standard thickness of an AOS channel is between 30 and 80 nm with 50 nm the
most commonly employed thickness. In the following, it is shown that the performance
metrics (VON , S, etc.) follow dissimilar trends when reducing the channel thickness.
By considering these effects, a pathway to higher performance ultra-thin TFTs is
discussed and experimentally confirmed.
For this experiment the annealing temperature is set between 200 and 500 °C and
the channel thickness is varied from 2.5 to 100 nm. The result is a 6 by 6 matrix of
TA vs. tAI T O with each of the 36 points consisting of an average value of 3 devices
50
(108 tested TFTs total). Figure 4.4(a) shows that the sub-threshold swing has an
(a) Contour plot of S as a function of TA and
tAI T O .
(b) Trap density (primary axis) and S (sec­
ondary axis) as a function of tAI T O at a con­
stant annealing temperature of TA = 350 °C.
Figure 4.4: Sub-threshold swing trends for AITO TFTs.
optimum region of S < 0.4 V/dec between 5 and 20 nm channel thickness, and 250
and 350 °C anneal. At a channel thickness below 10 nm, the average value of S
does not completely follow a linear trend (admittedly the variation is large at these
two points). A likely cause for this deviation is an improvement of the interface
when slightly increasing the thickness. As the first few monolayers are deposited,
incident atoms still find empty spots near the interface, reducing the interface trap
density (Dit ). After these first few nanometers are deposited, Dit is assumed to be
independent of the channel thickness.
51
The density of trap states can be extracted from S with, [54]
kB T
dVG
= ln(10)
1 + q 2 (NT t + Dit )/COX
q
d log ID
S(t)q
COX
⇒
−1
= NT t + Dit ,
q2
ln(10)kB T
S=
(4.1)
(4.2)
where kB T /q is the thermal voltage, COX is the gate oxide capacitance per unit area,
NT is the bulk-like trap density, and Dit is the number of interface trap states per unit
area. The left hand side of Eq. 4.2 can be plotted as a function of t after which NT
and Dit can be extracted as the slope and y-intercept, respectively, as a consequence
of y = mx + b. The fit equation is depicted in Fig. 4.4(b). Therefore, using this
method, the estimated trap densities in AITO are NT = 2.4 × 1017 cm−3 eV −1 and
Dit = 6.2 × 1011 cm−2 eV −1 . Trap densities of NT = 1.3 × 1018 cm−3 eV −1 and
Dit = 2.8 × 1012 cm−2 eV −1 have been reported for IGZO TFTs [55].
Figure 4.5(a) shows a maximum of the field-effect mobility (for enhancement-mode
behavior) occurring near a channel thickness of 10 nm for all anneal temperatures.
The mobility is normalized to a gate overvoltage of 15 V (µF E (VG = VON + 15 V )).
This normalization is necessary to be able to compare devices with different turn-on
voltages, because the mobility is a function of the gate voltage.
The devices processed in the dotted region, in Fig. 4.5(a), achieve the highest
mobility, but are depletion-mode. Out of the enhancement-mode devices, the TFTs
annealed at 350 °C have a peak in mobility of µF E ≈ 13 cm2 V −1 s−1 at a channel
thickness of 10 nm, as shown in Fig. 4.5(b).
Notably, the mobility sharply increases with increasing channel thickness up to
52
(a) Contour plot of µF E as a function of TA
and tAI T O .
(b) µF E as a function of tAI T O at a constant
annealing temperature of TA = 350 °C.
Figure 4.5: Field-effect mobility trends for AITO TFTs.
about 10 nm and slowly decreases again with a further increase in thickness. This nonmonotonic trend in mobility is also observed in FETs from the class of two-dimensional
materials such as (multilayer) molybdenum disulfide (M oS2 ) [56, 57]. A resistor
network model, with consideration of Thomas-Fermi charge screening theory and a
Coulomb potential arising from charges at the insulator/semiconductor interface, is
successfully used by Das and Appenzeller [56] and by Li et al. [57] to rationalize this
behavior. It is argued that there is a ∼3 nm thin ‘inactive’ layer with very low mobility
at the gate oxide/semiconductor interface which explains the initial sharp increase
in mobility beyond that thickness [57]. Because electrons are injected from a top
contact, the electrons have to travel across a resistive layer from the source through
the channel layer to reach the highly conductive accumulation layer near the bottom
interface and then again traverse the channel layer for extraction at the drain. Going
to a thicker channel layer the thickness of the accumulation layer stays the same,
53
but the resistive path through the channel becomes longer, therefore, reducing the
mobility again for a channel thicker than 10 nm.
The turn-on voltage VON is relatively constant (between -10 and +10 V) for a
channel thickness of 100 nm down to about 10-20 nm, as shown by the larger islands
of uniform blue color in Fig. 4.6(a). For an even thinner channel layer, VON shows a
strong increase, approaching a value of 50 V, as shown in Fig. 4.6(b) for an anneal
temperature of 350 °C. The critical thickness (tcrit ) is defined as the thickness where
the first onset of strong positive VON occurs. For AITO, tcrit is approximately 12 nm.
(a) Contour plot of VON as a function of TA
and tAI T O .
(b) VON as a function of tAI T O at a constant
annealing temperature of TA = 350 °C.
Figure 4.6: Turn-on voltage trends for AITO TFTs.
4.3.2 Comparison with IGZO
The AOSs AITO and IGZO show very similar trends when reducing the channel
thickness. The trends of VON vs. tchannel for AITO and IGZO, as shown in Fig. 4.7(a),
54
are almost identical with the only difference that the curve for IGZO is shifted left.
The value of tcrit for IGZO is about 9 nm, 3 nm smaller than that for AITO. For
S, again, the trend of AITO and IGZO data is very similar, evident by the parallel
trend lines in Fig. 4.7(b), but with IGZO devices having consistently lower values of
S than AITO. The fit lines and equations in Fig. 4.7 only describe the data points
with the square symbols which correspond to the regime below tcrit in Fig. 4.7(a) and
to the regime of constant Dit in Fig. 4.7(b), respectively.
(a) VON as a function of tchannel .
(b) S as a function of tchannel .
Figure 4.7: Comparison of AITO and IGZO TFT data for VON and S. Devices for
each AOS are processed with a fixed set of optimized process parameters of 95:5
Ar/O2 and TA = 350 °C for AITO, and 90:10 Ar/O2 and TA = 400 °C for IGZO.
The IGZO data is from Ref. [6].
4.3.3 Ultra-Thin TFTs
Frequently when optimizing the AOS process (i.e., TA , Ar/O2 ratio) for high mobility,
the devices become depletion-mode which is undesirable. The results in Section 4.3.1
55
show that VON can be shifted positively by reducing the channel thickness. Therefore,
a fabricated TFT with a high mobility and a high carrier concentration can achieve a
suitable zero VON by reducing the thickness below tcrit . This is supported by a TCAD
simulation for IGZO, as shown in Fig. 4.8(a). The sub-gap density of states (DOS)
profile used for the simulation is shown in Fig. 4.8(b). The exponentially decaying
acceptor (green) and donor (red) curves near the conduction and valence band are
the conduction and valance band tail states, respectively. The slope of the band tail
is called the Urbach energy. Urbach energies of 13 and 120 meV are used to model
the IGZO conduction and valence band, respectively [58]. Additionally, a Gaussian
distribution of donor states (blue) near the conduction band is incorporated as a main
contributor to establishing the free carrier concentration.
(a) Simulated transfer curves of an IGZO
TFT with a high carrier concentration of 1 ×
1018 cm−3 .
(b) Density of states (DOS) profile in the the
sub-band gap region of IGZO employed in the
TCAD model.
Figure 4.8: TCAD simulation shows how a normally depletion-mode TFT can be
improved to have a near-zero turn-on voltage by decreasing the channel thickness
from that of the standard thickness of 50 nm to an ultra-thin thickness of 5 nm.
As a result, the best overall AITO TFTs, shown in Fig. 4.9, are achieved by sput­
56
tering in a pure argon atmosphere which tends to both increase mobility and carrier
concentration. Enhancement-mode behavior is realized by reducing the channel thick­
ness to 5 nm.
However, results achieved using these process parameters are not very consistent.
Possibly, repeated sputtering in pure argon depletes the AOS target of oxygen, leading
to a drift in the process over time. Consequently, for the other experimental investi­
gations, a low oxygen partial pressure of 5 % is chosen, trading off some performance
in favor of better run-to-run repeatability.
(a) Optimized transfer curve of an ultra-thin
channel layer (5 nm) AITO TFT.
(b) Corresponding output curve of an ulta-thin
channel layer (5 nm) AITO TFT.
Figure 4.9: The channel layer is obtained by sputtering in pure argon and annealing
at 310 °C.
4.3.4 Shelf Life of Ultra-Thin Channel Layer TFTs
Even ultra-thin channel layer TFTs that display poor performance on the day of
fabrication tend to improve over time, as shown in Fig. 4.10. Particularly, Fig. 4.10(a)
57
shows a transfer curve that on day 1 exhibits a negative VON , hysteresis, and kinks.
After aging for four days the transfer curve is dramatically improved. In contrast,
Fig. 4.10(b) shows that a device with a rather positive VON also improves over time
and again VON gets closer to zero, but this time due to a left shift in VON . After this
initial shift, the transfer curves are very stable up to the end of this investigation (∼1
year). Further investigations showed that the TFT improvement over time is indeed
an aging effect, and not an artifact due to repeated transfer curve sweeps. However,
improvement of VON , hysteresis, etc. is accompanied by a slight degradation in on­
current/mobility which tends to saturate after about a month (see appendix).
(a) Initially, the transfer curve shows
depletion-mode behavior, hysteresis, and
kinks. After a few days the device improves to
near-ideal behavior and from there on exhibits
very little shift over time.
(b) On the day of fabrication the device has a
rather positve VON , but improves to near-zero
VON after four days.
Figure 4.10: Unpassivated, ultra-thin TFTs stored at lab atmosphere. Transfer curves
in (a) and (b) show two starkly different behaviors on the day of fabrication, but are
very similiar, and strongly improved overall performance, after aging.
58
4.3.5 Oxygen Adsorption Model
Finally, the question remains why AITO TFTs exhibit a dependence on channel thick­
ness, especially the strong increase in VON below tcrit . The proposed model to explain
this trend involves oxygen adsorption at the unpassivated back surface of the chan­
nel. The two-step process of molecular oxygen adsorption is illustrated in Fig. 4.11,
as described in Ref. [16] pages 157-160 and references therein. First, the oxygen is
physisorbed onto the surface (neutral acceptor charge state). Second, the oxygen
captures an electron from the conduction band of the channel layer, becoming neg­
atively charged (negative acceptor charge state), thereby depleting the back surface.
The electron capture means that the oxygen is now chemisorbed. Qualitatively, the
electron capture has a much stronger impact on a thinner channel layer than on a
thicker one.
Figure 4.11: Oxygen adsorption on the back surface of an AOS TFT.
At a channel thickness of 5 nm, the accumulation layer region is likely to extend
59
throughout the entire thickness of the channel [59]. For the TFT to turn on, an
accumulation layer needs to form (conduction band bending downward). As shown
in Fig. 4.12, the close proximity of the unpassivated channel layer surface to the
insulator/channel layer interface for the thin 5 nm thick channel layer will result in
more trap emptying at the interface and perhaps within the channel layer itself. Prior
to the formation of an accumulation layer, more trap states need to be filled compared
to a thicker channel. Thus, a larger gate voltage (VON ) is required to turn the TFT
on. This correlates well with the observed degradation of the sub-threshold swing
when the channel layer is very thin, which is also associated with a larger (empty)
trap density, as discussed in Section 4.3.1. Because the strong increase in VON is only
apparent at these very thin channel layers, it is expected that interface traps are more
responsible for this VON increase than bulk traps. However, a band of bulk traps near
the Fermi-level is expected to yield a similar increase in VON .
Figure 4.12: Energy band diagram of unpassivated AITO TFTs with a channel layer
thickness of 50 and 5 nm.
Note that if the electron capture via a thermionic emission process illustrated in
Fig. 4.12 is the rate-limiting step for the oxygen chemisorption, chemisorption will
60
terminate either when the channel layer is depleted of conduction band electrons or
when the thermionic barrier height is so large that it suppresses further thermionic
emission. Thus, oxygen chemisorption is an essentially self-regulated process, ter­
minating with electron depletion or the formation of a sufficiently large thermionic
emission barrier. The fact that VON tends to zero volts for most unpassivated AITO
TFTs exposed to air for a prolonged period of time (several days), particularly for
ultra-thin channel layer TFTs as discussed in Section 4.3.4, suggests that electron
depletion is the more likely rate-limiting mechanism.
A high-quality passivation layer should prevent the adsorption of oxygen at the
back surface. Passivated devices with varying channel thickness need to be studied
to discern whether oxygen absorption is indeed the reason for the strong increase in
VON for these ultra-thin channels.
As a result, the next section deals with the evaluation of passivation layers for the
fabrication of passivated AITO TFTs.
4.4 Evaluation of Passivation Layers
In a staggered bottom-gate structure, the top surface of the channel is exposed to
air. A passivation layer can protect the top surface from subsequent processing (e.g.,
plasma damage) and gas adsorption/desorption. A gas-impermeable passivation layer
is important for stability testing and is a necessity for further elucidating the channel
thickness dependence.
The three compounds FluorinertT M , aluminum oxide (Al2 O3 ), and zinc tin silicon
61
oxide (ZTSO) are evaluated for their use as passivation layer. FluorinertT M (chemical
formula: C15 F33 N ) by 3M is a liquid and can be dispensed on the substrate with a
pipette. After Fluorinert passivation, VON of the AITO TFT shifts negative by a few
volts, depending on the channel thickness (the 5 nm device shows a larger shift than
the 50 nm device), but otherwise retains good device characteristics. It is very easy
to passivate TFTs with Fluorinert. However, Fluorinert evaporates after a few days
at room temperature and is therefore not useful for shelf life tests. The effectiveness
of Fluorinert with respect to gas permeation is unknown. For industrial applications,
Fluorinert is deemed inadequate as a passivation layer.
Vapor-deposited Al2 O3 or ZTSO layers are expected to provide a more permanent
and higher-quality protection layer. The Al2 O3 is deposited via plasma-enhanced
atomic layer deposition (PEALD) at a substrate temperature of 200 °C. A repre­
sentative transfer curve of an Al2 O3 -passivated TFT is shown in Fig. 4.13(a). After
passivation the transfer curve shows a left-going shift in VON of > 20 V, hysteresis,
and kinks.
The ZTSO is deposited via sputtering without intentional substrate heating. A
representative transfer curve of a ZTSO-passivated TFT is shown in Fig. 4.13(b).
Directly after ZTSO deposition the device is highly conductive, presumably due to
the creation of a low resistance path at the AITO/ZTSO interface. Subsequently, the
sample is annealed at 400 °C. After the anneal, the transfer curve shows a significant
improvement, but slightly degraded compared to the pre-passivation measurement.
However, both the Al2 O3 -and ZTSO-passivated devices show an anomaly that is
particularly apparent at low drain biases by examining the extracted mobility curve.
62
(a) Al2 O3 passivation layer.
(b) ZTSO passivation layer. Post-passivation
anneal for 1 hour at 400 °C.
Figure 4.13: 50 nm AITO TFTs (channel annealed at 300 °C) with 100 nm passivation
layers.
For the ZTSO-passivated TFT, at a low drain bias (0.1 to 1 V) there is hardly any
current flow. Some of this can be cured with a higher drain voltage (10 to 30 V)
‘break-in’ sweep, as shown in Fig. 4.14(d). After this apparent break down of the
barrier, a low drain bias sweep looks nearly normal. However, the mobility is still
strongly degraded and very similar to that shown in Fig. 4.14(b) (discussed next).
For the Al2 O3 -passivated TFT, this anomalous reduction in mobility is observed as
well.
To further investigate this phenomenon, a stress anneal study is conducted. The
hypothesis is that the aluminum S/D contacts are not thermodynamically stable with
respect to AITO. The elevated temperature of the Al2 O3 /ZTSO processing may cause
the formation of a highly resistive (oxide/trapping) layer between the aluminum and
AITO, leading to a series resistance effect.
Standard 50 nm AITO TFTs with aluminum S/D contacts are subjected to an
63
Figure 4.14: Transfer curve (a) of an AITO TFT annealed at 200 °C , as well as cor­
responding mobility (b) and output (c) curves. Transfer curve of a ZTSO-passivated
TFT showing the ‘break-in’ effect (d).
64
anneal at 200 °C for 5 h. The temperature profile corresponds to a deposition of
33 nm of PEALD Al2 O3 . Indeed, the same anomaly is observed very consistently
in these devices. A representative transfer curve and mobility plot is depicted in
Fig. 4.14(a),(b). Furthermore, an output curve, shown in Fig. 4.14(c), confirms the
existence a series resistance problem.
The publication “Metallization strategies for I n2 O3 -based amorphous oxide semi­
conductor materials” by Lee et al. [60] supports the assertion of interfacial oxide
formation. Lee et al. used GIXRD to prove the presence of a titanium interface oxide
in an In-Zn-O/Ti stack after annealing at 200 °C. The existence of a very thin alu­
minum oxide interface layer (in the AITO/Al stack) would likely be amorphous and,
therefore, very difficult to detect via GIXRD. Nonetheless, GIXRD on an annealed
AITO/Al stack is performed, but no aluminum oxide layer is detected.
The results of these device passivation investigations are as follows. ZTSO and, in
particular PEALD Al2 O3 due its high quality, are promising candidates for passivation
of AITO TFTs. However, the AITO/Al stack is not stable and temperatures as low
as 200 °C severely affect device performance. As a consequence, the next section deals
with an evaluation of contact metals, with the aim of finding a more temperaturestable metal to replace the aluminum metallization scheme.
4.5 Source and Drain Metallization
The standard S/D metal in the fabriation of AITO TFTs is aluminum. As discussed
in the previous section, the AITO/Al stack is not able to withstand the temperature
65
stress of a passivation layer deposition, even at a temperature as low as 200 °C. The
alternative metals silver (Ag), gold (Au), chromium (Cr), all thermally evaporated, as
well as molybdenum (Mo), via electron beam evaporation, and an amorphous metal
thin film (AMTF), via sputtering, are evaluated. The metals are chosen based on
availability in the lab, likelihood of forming an oxide, and work function alignment.
A summary of the different contact metals investigated is shown in Table 4.3.
Overall, the other metals tend to be worse than the aluminum reference. The metals
AMTF and Mo have very negative turn-on voltages, shown in Fig. 4.15(a), which
may be due to the higher energetic deposition process used, sputtering/electron beam
compared to thermal evaporation. Earlier experiments with sputtered ITO as S/D
contact also produced a negative shift of VON relative to evaporated Al (not shown).
Adjusting process parameters is expected to help mitigate some of the negative VON
shift. In particular, reducing the channel thickness, as shown in Fig. 4.15(b), and
increasing the oxygen partial pressure during AITO deposition are likely to help.
Out of the results presented in Table 4.3, evaporated Cr may be the best candidate
to replace Al if improved temperature stability is required. Conversely, Cr seems to
require a post metal deposition anneal to realize adequate performance. Still, the
achieved mobilities of TFTs with Cr electrodes are only about half of that obtained
for the untreated Al reference samples.
Table 4.3: Summary of an AITO metallization study. Six TFTs (2 substrates à 3 TFTs) for each of the
metals Al, Ag, Au, Cr, AMTF, and Mo are tested three successive times. They are tested on the day of
fabrication (day 0), four days later (stability over time), and after a 5 hour anneal at 200 °C. Note: VON is
in V and µF E is in cm2 V −1 s−1 .
Stability Time (day 4) Stability Temperature
Deposition Initial (day 0)
Metal
VON H yst. µF E
Method
VON H yst. µF E VON H yst. µF E
Al
T. Evap.
Ag
T. Evap.
Au
T. Evap.
Cr
T. Evap.
AMTF Sputtering
Mo
E-Beam
4.8
6.7
8.0
6.7
-29
-42
-
12.5
9.3
7.8
8.8
14.3
13.3
0.6
5.3
7.1
-0.7
-32
-39
H
H
-
9.5
10.4
6.2
7.7
13.9
12.6
4.5
3.9
6.6
H
7.1
-9.2 -13.3 H
3.4
1.4
6.0
6.5
9.9
2.2
66
67
(a) Comparison of turn-on voltage (VON ) for
six different S/D metals. The devices are processed identically with 50 nm thick AITO, a
300 °C channel anneal, and the metal as de­
posited. The values are averages of six TFTs.
(b) Drastically reducing the channel thickness
shifts the VON positive by about 20 V for both
Al and Mo S/D contacts as expected.
Figure 4.15: Source/drain metallization of AITO TFTs.
68
Chapter 5: Conclusions and Recommendations for Future Work
5.1 Conclusions
The aim of the research undertaken for this thesis was to develop a new, high-mobility
AOS TFT. The display industry is asking for oxide semiconductors that perform sig­
nificantly better than a-Si:H for application in the active-matrix backplane of AMLCD
and AMOLED displays. A new channel layer material, Al-In-Sn-O, was developed
and subsequently evaluated via fabrication of discrete TFTs. AITO thin films were
deposited via sputtering and analyzed. AITO has an excellent amorphous phase sta­
bility up to 725 °C. The TFT process parameters such as annealing temperature (TA )
and Ar/O2 ratio were optimized for best performance.
To protect the exposed back surface, the compounds ZTSO and Al2 O3 were tested
for their use as a passivation layer. ZTSO and Al2 O3 processes require a maximum
temperature of 400 and 200 °C, respectively. It was found that the interface between
the AITO channel and the standard aluminum contact was not thermodynamically
stable, even at a relatively low temperature of 200 °C. Therefore, the metals Ag,
Au, Cr, Mo and an amorphous metal thin film were assessed for their application in
replacing the aluminum S/D metallization scheme. Out of the five metals, evapo­
rated Cr was identified as the most promising candidate, showing an improvement in
temperature stability over Al electrodes.
69
Most significantly, the effect of the channel thickness on the properties of AITO
TFTs was studied. Unpassivated TFTs were found to operate with a channel as
thin as ∼2.5 nm. A strong positive increase in turn-on voltage with thinner channels
was leveraged to achieve enhancement-mode behavior for high mobility TFTs with a
rather high carrier concentration. The channel layer is processed under conditions,
i.e. sputtering in pure argon and TA = 310 °C, that resulted in a high mobility, but
depletion-mode behavior for a standard 50 nm AITO TFT. The TFTs with an ultrathin channel of 5 or 10 nm result in the best enhancement-mode devices of this work,
with a maximum mobility of µF E = 15 − 18 cm2 V −1 s−1 , drain current on-to-off ratio
of IDON −OF F ≈ 107 , and a sub-threshold swing of S = 0.2 V /dec.
A model explaining the strong increase in VON with thinner channels was devel­
oped. Oxygen adsorption at the unpassivated back surface depletes the backside of
the channel. For an ultra-thin channel, the interface is in close proximity to the back
surface, causing an increase of the (empty) interface trap density. As a consequence,
a larger gate voltage (VON ) needs to be applied in order to form an accumulation
layer and, thus, turn on the TFT.
5.2 Future Work
Further experiments are needed to fully understand ultra-thin channel layer AOS
TFTs. A high-quality, gas impermeable passivation layer is needed to study the
effect of gas adsorption at the back surface.
Striving for even higher mobilities in the 50 to 60 cm2 V −1 s−1 range, several pos­
70
sible routes exist. An incremental improvement in mobility is expected by simply
further increasing the indium content in the Al-In-Sn-O system.
Possibly the most promising approach is to use a dual active layer (DAL) type
structure. In this DAL structure, typically the channel is comprised of a very thin,
high mobility layer (e.g., < 10 nm of ITO) at the gate insulator/channel interface
and then capped with a thicker AOS layer (e.g., 40 nm of IGZO) processed to have
a relatively low carrier concentration.
Besides higher mobility oxides, there are still many unanswered questions about
the fundamental physics and chemistry of AOSs. Ongoing work at OSU is aiming to
create a comprehensive model that links understanding on an atomistic level all the
way to a technology computer aided design (TCAD) device simulator level. That is,
to go from atomic structure parameters, such as coordination number and average
bond length, to an electronic density of states perspective, with more abstract, but
physics-based parameters, such as trap density and Urbach energy, which can be
plugged into a TCAD tool. Then, TCAD simulations would allow direct comparisons
to experimental transfer and output curves. In turn, one could draw conclusions on
the atomistic structure of the TFT channel layer and how processing affects the AOS
thin film without doing complex scattering experiments. Pair distribution function
(PDF) analysis of x-ray and neutron diffraction measurements can be used to gain
insight into the structure-property relationships of AOSs.
Molecular dynamics (MD) computations can be seen as an intermediate step. A
separate, computational atomic model is created and can be used to cross-check/refine
the experimental PDF results (or vice versa) and from there go to a density of states
71
model. First results have been achieved for IGZO in collaboration with the Center
for Sustainable Materials Chemistry (CSMC) [61, 62].
72
APPENDICES
73
Appendix A: Additional Al-In-Sn-O Thin Film Data
A.1 Deposition Rate
Figure A.1: Sputter deposition for a fixed set of process parameters (50 W, 90:10
Ar/O2 , 5 mTorr, 4 inches source-to-substrate distance) results in a linear rate of 4
nm/min (from XRR data).
74
A.2 Hall Measurements
(a) Carrier concentration and resistivity as
a function of TA .
(b) Hall mobility as a function of carrier
concentration showing the typical trend of
AOSs of increasing mobility at higher car­
rier concentrations.
Figure A.2: Hall measurements with the Van der Pauw method of 80 and 200 nm
thick AITO films.
A.3 Shelf life of Ultra-thin Channel Layer TFTs
Figure A.3: Initially, the mobility (and ION ) decreases over time, but saturates after
about 30 days.
75
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