REAL-TIME EMBEDDED SYSTEMS
DESIGN USING FPGAS
• An electronic system containing a CPU without an operating
system visible to the end-user.
ECE 551 Overview
• It interacts with peripheral devices within fixed time
constraints.
HDL
architecture behavior of control is
if left_paddle then
n_state <= hit_state
elsif n_state <= miss_state
end if;
SYNTHESIS
Prof. Don Bouldin, Ph.D.
SCHEMATIC
AND
AND
OR
• A minimum of resources are employed to perform the
required tasks.
PLACE & ROUTE
PHYSICAL LAYOUT
• In addition to functionality and cost, other constraints
include power management, fault tolerance, quality of
service, security, etc.
Electrical & Computer Engineering
University of Tennessee
TEL: (865)-974-5444
FAX: (865)-974-5483
dbouldin@tennessee.edu
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© 2011 -- Don Bouldin
SYSTEM FUNCTIONS ARE OFTEN SPLIT
BETWEEN THE CPU AND AN ASIC
APPLICATIONS MAY USE
STANDARD ICs or FPGAs/ASICs
Standard IC
ASIC
(off-the-shelf)
(User-specified)
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© 2011 -- Don Bouldin
• The most economical
means of implementing
logic functions is to use a
Slow Inputs
microprocessor.
SSI/MSI
LSI/VLSI
• When the microprocessor
Custom
Semicustom
is too slow or too busy to
handle some fast inputs
User-programmable
PLDs
Structured
Standard
Analog/Digital
ASICs
Library Cells
Mixed-Signal
be used to implement
© 2011 -- Don Bouldin
Compiler
Pre-Defined
Complex
Hardware
(CPU or DSP)
Fast Inputs
ASIC
Fast Outputs
high-speed concurrent
operations.
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4
© 2011 -- Don Bouldin
MICROELECTRONIC SYSTEM DESIGN
CONSISTS OF ITERATIVE REFINEMENTS
OF SYNTHESIS AND VERIFICATION
FPGAS PROVIDE PRECISE CONTROL
OF THE HARDWARE
Software (C)
Control
& Feedback
Slow
Inputs
and outputs, an ASIC can
(All Masks)
FPGAs
Slow Outputs
Microprocessor
p
Requirements
Firmware (HDL)
Architectural
Specifications
Design
Review
Behavioral
Description
Behavioral
Simulation
Logic
Synthesis
Logic-Level
Simulation
Compiler
TRENDS
Configuration
Basic Logic and
Interconnect
(FPGA)
Physical
Implementation
• CPUs have a single arithmetic unit with a fixed bit size.
• FPGAs can have multiple units with flexible bit sizes.
© 2011 -- Don Bouldin
Prototype
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Trans.-Level
Simulation
Measurement
© 2011 -- Don Bouldin
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ECE 551 & ECE 651
CUSTOM IC DESIGN FLOW
• ECE 551 (logic level; b/w):
– Pairs create project using VHDL
– Simulate pre-synthesis and post-layout
– Demonstrate using 200K-gate Xilinx FPGA
on Spartan3 Board with I/O
– Implement
I
le e t on
o screen
ee only
o l using
i
Altera
Alte
FPGA
1--SCHEMATIC
3—MANUAL LAYOUT
• ECE 651 (physical level; color):
– Perform custom IC design (but not submit for fab)
– Compare manual design vs. automated tools
– Study nanometer design issues (cross-talk, power)
© 2011 -- Don Bouldin
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SEMI-CUSTOM DESIGN FLOW OF
DIGITAL FPGAS/ASICS
1—HDL
2--PRE-LAYOUT LOGIC SIMULATION
4--POST-LAYOUT TRANS. SIMULATION
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© 2011 -- Don Bouldin
HIGH VOLUME APPLICATIONS OF FPGAS
2--PRE-SYNTHESIS SIMULATION
CASE w IS
WHEN "00" => y <= "1000" ;
WHEN "01" => y <= "0100" ;
WHEN "10" => y <= "0010" ;
WHEN OTHERS => y <= "0001";
END CASE ;
3—SYNTHESIS/AUTO LAYOUT
4--POST-LAYOUT SIMULATION
www.xilinx.com
© 2011 -- Don Bouldin
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TELECOMMUNICATIONS IS THE
LARGEST MARKET FOR FPGAS
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© 2011 -- Don Bouldin
PROGRAMMABLE LOGIC ARRAY
• Xilinx (XLNX) and Cisco (CSCO) stock prices have
tracked together for two decades.
• Any 8-row truth table can be
implemented using eight 3-input
AND gates followed by a single OR
gate with 8 inputs.
ROW
0
1
2
3
4
5
6
7
• An array of AND-OR tiles can be
programmed to implement logic.
• In this example, only two outputs
are required for row 4 and row 7:
OUT = ABC + ABC
A B C OUT
0 0 0
0
0 0 1
0
0 1 0
0
0 1 1
0
1 0 0
1
1 0 1
0
1 1 0
0
1 1 1
1
A
B
C
OUT
A
B
C
© 2011 -- Don Bouldin
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© 2011 -- Don Bouldin
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RECONFIGURABLE COMPONENTS
ARE ADAPTABLE
PLD AND CPLD
• Initially, programmable logic devices (PLDs)
consisted of an array of 8 AND-OR tiles (called
Logic Array Blocks or LABs by Altera) plus some
additional interconnecting wires and storage
elements.
The internal logic and interconnect of a reconfigurable
component (FPGA) may be specified by the user and
changed at any time.
CONTROLSIGNAL PROC.
ARITHMETIC
C
• Larger components with 128 tiles (or more)
became known as CPLDs or Complex PLDs. The
tiles can be interconnected via a wiring matrix.
= LAB
© 2011 -- Don Bouldin
www.altera.com
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HDL DESIGNS CAN BE TARGETED
TO MULTIPLE LAYOUTS
SYNOPSYS
SYNPLIFY_PRO
HDL
architecture behavior of control is
if left_paddle then
n_state <= hit_state
elsif n_state <= miss_state
end if;
AND
AND
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COURSE GOALS
This project-oriented course involves:
LIBRARIES
(1) design of field-programmable gate arrays (FPGAs)
SYNTHESIS
TECH
A
SCHEMATIC--A
TECH
A
© 2011 -- Don Bouldin
TECH
B
(2) using synthesis and automatic placement and routing software
(3) to implement the design using multiple technologies (Altera and Xilinx)
SCHEMATIC--B
OR
OR
AND
OR
(4) with local/remote access to LINUX workstations
TECH
B
(5) free use of Xilinx prototyping boards
(6) grade depending on homework, project and final exam
ALTERA
PLACE & ROUTE
XILINX
PLACE & ROUTE
PHYSICAL LAYOUT
PHYSICAL LAYOUT
(7) all presentation slides will be posted on the web:
http://web.eecs.utk.edu/~bouldin/courses/551/overview.html
© 2011 -- Don Bouldin
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© 2011 -- Don Bouldin
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