33 × 17, 3.2 Gbps
Digital Crosspoint Switch
AD8151
FEATURES
APPLICATIONS
Low cost
33 × 17, fully differential, nonblocking array
3.2 Gbps per port NRZ data rate
Wide power supply range: +3.3 V, –3.3 V
Low power
425 mA (outputs enabled)
35 mA (outputs disabled)
LV PECL- and LV ECL-compatible
CMOS/TTL-level control inputs: 3 V to 5 V
Low jitter
No heat sinks required
Drives a backplane directly
Programmable output current
Optimize termination impedance
User-controlled voltage at the load
Minimize power dissipation
Individual output disable for busing and reducing power
Double row latch
Buffered inputs
184-lead LQFP package
High speed serial backplane routing to Sonet OC-48
applications with FEC
Fiber optic network switching
Fiber channel
LVDS
FUNCTIONAL BLOCK DIAGRAM
INP
INN
CS
RE
5
A
OUTPUT
ADDRESS
DECODER
7
D
FIRST
RANK
17 ×
7-BIT
LATCH
SECOND
RANK
17 ×
7-BIT
LATCH
INPUT
DECODERS
33
33
17
OUTP
33 × 17
DIFFERENTIAL
SWITCH
MATRIX
17
OUTN
AD8151
WE
02169-001
UPDATE
RESET
Figure 1.
.
GENERAL DESCRIPTION
Its fully differential signal path reduces jitter and crosstalk,
while allowing the use of smaller, single-ended voltage swings.
The AD8151 is offered in a 184-lead LQFP package that
operates over the extended commercial temperature range
of 0°C to 85°C.
02169-002
150mV/DIV
The AD8151 1 is a member of the Xstream line of products,
offering a breakthrough in digital switching and a large switch
array (33 × 17) on very little power—typically less than 1.5 W.
It also operates at data rates in excess of 3.2 Gbps per port,
making it suitable for Sonet OC-48 applications with
8/10-bit forward-error correction (FEC). Furthermore, the
price of the AD8151 makes it affordable enough to be used for
lower data rates. The AD8151’s flexible supply voltages allow
the user to operate with either emitter-coupled logic (ECL) or
positive emitter-coupled logic (PECL) data levels, and with 3.3
V for further power reduction. The control interface is CMOS/TTL-compatible (3 V to 5 V).
70ps/DIV
Figure 2. Eye Pattern, 3.2 Gbps, PRBS 23
1
Patent pending.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
AD8151
TABLE OF CONTENTS
Features .............................................................................................. 1
Control Interface ............................................................................ 17
Applications....................................................................................... 1
Control Pin Description............................................................ 17
Functional Block Diagram .............................................................. 1
Control Interface Translators.................................................... 18
General Description ......................................................................... 1
Circuit Description......................................................................... 19
Revision History ............................................................................... 2
Applications..................................................................................... 23
Specifications..................................................................................... 3
Input and Output Busing .......................................................... 23
Absolute Maximum Ratings............................................................ 4
Evaluation Board ........................................................................ 23
Maximum Power Dissipation ..................................................... 4
Power Supplies ............................................................................ 24
ESD Caution.................................................................................. 4
Configuration Programming.................................................... 25
Pin Configuration and Function Descriptions............................. 5
Software Installation .................................................................. 25
Typical Performance Characteristics ............................................. 9
Software Operation .................................................................... 26
Control Interface Truth Tables...................................................... 13
Outline Dimensions ....................................................................... 38
Control Interface Timing Diagrams ............................................ 14
Ordering Guide .......................................................................... 38
Control Interface Programming Example .............................. 16
REVISION HISTORY
12/05—Rev. A to Rev. B
Changes to Table 1............................................................................ 3
Changes to Figure 4.......................................................................... 5
Changes to Table 3............................................................................ 6
Changes to Table 4.......................................................................... 13
Changes to Figure 51...................................................................... 35
Changes to Ordering Guide .......................................................... 38
9/05—Rev. 0 to Rev. A
Updated Format..............................................................Universal
Change to Figure 51 ................................................................... 34
Change to Ordering Guide........................................................ 37
4/01—Revision 0: Initial Version
Rev. B | Page 2 of 40
AD8151
SPECIFICATIONS
@ 25°C, VCC = 3.3 V to 5 V, VEE = 0 V, RL = 50 Ω (see Figure 26), IOUT = 16 mA, unless otherwise noted.
Table 1.
Parameter
DYNAMIC PERFORMANCE
Max Data Rate/Channel (NRZ)
Channel Jitter
RMS Channel Jitter
Propagation Delay
Propagation Delay Match
Output Rise/Fall Time
INPUT CHARACTERISTICS
Input Voltage Swing
Input Bias Current
Input Capacitance
Input VIN High
Input VIN Low
OUTPUT CHARACTERISTICS
Output Voltage Swing
Output Voltage Range
Output Current
Output Capacitance
Output VOUT High
Output VOUT Low
POWER SUPPLY
Operating Range
PECL, VCC
ECL, VEE
VDD
VSS
Quiescent Current
VDD
VEE
THERMAL CHARACTERISTICS
Operating Temperature Range
θJA
LOGIC INPUT CHARACTERISTICS
Input VIN High
Input VIN Low
Conditions
Min
Typ
2.5
3.2
52
8
650
±50
100
Data rate = 3.2 Gbps
Input to output
See Figure 23
20% to 80%
Single-ended (see Figure 18)
200
Max
±100
1000
2
2
VCC
VCC − 1.2
VCC − 2.4
Differential
(See Figure 19)
VCC − 1.4
800
VCC
25
VCC − 1.8
5
2
VCC − 1.8
VCC
VEE = 0 V
VCC = 0 V
3.0
–5.25
3
5.25
–3.0
5
0
2
425
All outputs enabled, IOUT = 16 mA
TMIN to TMAX
All outputs disabled
450
35
0
Unit
Gbps
ps p-p
ps
ps
ps
ps
mV p-p
μA
pF
V
V
mV p-p
V
mA
pF
V
V
V
V
V
V
mA
mA
mA
mA
85
°C
°C/W
VDD
0.9
V
V
30
VDD = 3 V dc to 5 V dc
1.9
0
Rev. B | Page 3 of 40
AD8151
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
MAXIMUM POWER DISSIPATION
Table 2.
The maximum power that can be safely dissipated by the
AD8151 is limited by the associated rise in junction
temperature. The maximum safe junction temperature for
plastic encapsulated devices is determined by the glass
transition temperature of the plastic, approximately 150°C.
Temporarily exceeding this limit may cause a shift in
parametric performance due to a change in the stresses exerted
on the die by the package. Exceeding a junction temperature of
175°C for an extended period can result in device failure. To
ensure proper operation, it is necessary to observe the
maximum power derating curves shown in Figure 3.
Rating
10.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
4.2 W
2.0 V
–65°C to +125°C
300°C
30°C/W
6
TJ = 150°C
5
4
3
2
1
–10
02169-003
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
MAXIMUM POWER DISSIPATION (W)
Parameter
Supply Voltage
VDD − VEE
VCC − VEE
VDD − VSS
VSS − VEE
VSS − VCC
VDD − VCC
Internal Power Dissipation
184-Lead LQFP (ST-184)
Differential Input Voltage
Storage Temperature Range
Lead Temperature (Soldering 10 sec)
Junction Temperature, θJA
0
10
20
30
40
50
60
AMBIENT TEMPERATURE (°C)
Figure 3.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 4 of 40
70
80
90
AD8151
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
180
181
182
179
138
PIN 1
INDICATOR
2
137
3
136
4
135
5
134
6
133
7
132
8
131
9
130
10
129
11
128
12
127
13
126
14
125
15
124
16
123
17
122
18
121
19
120
20
119
21
AD8151
118
22
184L LQFP
TOP VIEW
(Not to Scale)
117
23
24
116
115
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
93
68
94
46
67
95
45
66
96
44
65
97
43
64
98
42
63
99
41
62
100
40
61
101
39
60
102
38
59
103
37
58
104
36
57
105
35
56
106
34
55
107
33
54
108
32
53
109
31
52
110
30
51
111
29
50
112
28
49
113
27
48
114
26
47
25
Figure 4. Pin Configuration
Rev. B | Page 5 of 40
VEE
IN12N
IN12P
VEE
IN11N
IN11P
VEE
IN10N
IN10P
VEE
IN09N
IN09P
VEE
IN08N
IN08P
VEE
IN07N
IN07P
VEE
IN06N
IN06P
VEE
IN05N
IN05P
VEE
IN04N
IN04P
VEE
IN03N
IN03P
VEE
IN02N
IN02P
VEE
IN01N
IN01P
VEE
IN00N
IN00P
VEE
VCC
VEEA0
OUT00P
OUT00N
VEEA1
VEE
02169-004
1
VEE
OUT15N
OUT15P
VEEA15
OUT14N
OUT14P
VEEA14
OUT13N
OUT13P
VEEA13
OUT12N
OUT12P
VEEA12
OUT11N
OUT11P
VEEA11
OUT10N
OUT10P
VEEA10
OUT09N
OUT09P
VEEA9
OUT08N
OUT08P
VEEA8
OUT07N
OUT07P
VEEA7
OUT06N
OUT06P
VEEA6
OUT05N
OUT05P
VEEA5
OUT04N
OUT04P
VEEA4
OUT03N
OUT03P
VEEA3
OUT02N
OUT02P
VEEA2
OUT01N
OUT01P
VEE
VEE
IN20P
IN20N
VEE
IN21P
IN21N
VEE
IN22P
IN22N
VEE
IN23P
IN23N
VEE
IN24P
IN24N
VEE
IN25P
IN25N
VEE
IN26P
IN26N
VEE
IN27P
IN27N
VEE
IN28P
IN28N
VEE
IN29P
IN29N
VEE
IN30P
IN30N
VEE
IN31P
IN31N
VEE
IN32P
IN32N
VEE
VCC
VEE
OUT16N
OUT16P
VEEA16
VEE
183
184
VEE
IN19N
IN19P
VEE
IN18N
IN18P
VEE
IN17N
IN17P
VEE
IN16N
IN16P
VEE
VCC
VDD
RESET
CS
RE
WE
UPDATE
A0
A1
A2
A3
A4
D0
D1
D2
D3
D4
D5
D6
VSS
REF
VEEREF
VCC
VEE
IN15N
IN15P
VEE
IN14N
IN14P
VEE
IN13N
IN13P
VEE
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD8151
Table 3. Pin Function Descriptions
Pin No.
1, 4, 7, 10, 13, 16, 19, 22, 25, 28, 31,
34, 37, 40, 42, 46, 47, 92, 93, 99,
102, 105, 108, 111, 114, 117, 120,
123, 126, 129, 132, 135, 138, 139,
142, 145, 148, 172, 175, 178, 181,
184
2
3
5
6
8
9
11
12
14
15
17
18
20
21
23
24
26
27
29
30
32
33
35
36
38
39
41, 98, 149, 171
43
44
45
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
Mnemonic
VEE
Type
Power Supply
Description
Most Negative PECL Supply (Common with Other Points Labeled
VEE)
IN20P
IN20N
IN21P
IN21N
IN22P
IN22N
IN23P
IN23N
IN24P
IN24N
IN25P
IN25N
IN26P
IN26N
IN27P
IN27N
IN28P
IN28N
IN29P
IN29N
IN30P
IN30N
IN31P
IN31N
IN32P
IN32N
VCC
OUT16N
OUT16P
VEEA16
OUT15N
OUT15P
VEEA15
OUT14N
OUT14P
VEEA14
OUT13N
OUT13P
VEEA13
OUT12N
OUT12P
VEEA12
OUT11N
OUT11P
VEEA11
OUT10N
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
Power Supply
PECL/ECL
PECL/ECL
Power Supply
PECL/ECL
PECL/ECL
Power Supply
PECL/ECL
PECL/ECL
Power Supply
PECL/ECL
PECL/ECL
Power Supply
PECL/ECL
PECL/ECL
Power Supply
PECL/ECL
PECL/ECL
Power Supply
PECL/ECL
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
Most Positive PECL Supply (Common with Other Points Labeled VCC)
High Speed Output Complement
High Speed Output
Most Negative PECL Supply (Unique to this Output)
High Speed Output Complement
High Speed Output
Most Negative PECL Supply (Unique to this Output)
High Speed Output Complement
High Speed Output
Most Negative PECL Supply (Unique to this Output)
High Speed Output Complement
High Speed Output
Most Negative PECL Supply (Unique to this Output)
High Speed Output Complement
High Speed Output
Most Negative PECL Supply (Unique to this Output)
High speed Output Complement
High speed Output
Most Negative PECL Supply (Unique to this Output)
High Speed Output Complement
Rev. B | Page 6 of 40
AD8151
Pin No.
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
94
95
96
97
100
101
103
104
106
107
109
110
112
113
115
116
118
119
121
122
124
125
127
128
Mnemonic
OUT10P
VEEA10
OUT09N
OUT09P
VEEA9
OUT08N
OUT08P
VEEA8
OUT07N
OUT07P
VEEA7
OUT06N
OUT06P
VEEA6
OUT05N
OUT05P
VEEA5
OUT04N
OUT04P
VEEA4
OUT03N
OUT03P
VEEA3
OUT02N
OUT02P
VEEA2
OUT01N
OUT01
VEEA1
OUT00N
OUT00P
VEEA0
IN00P
IN00N
IN01P
IN01N
IN02P
IN02N
IN03P
IN03N
IN04P
IN04N
IN05P
IN05N
IN06P
IN06N
IN07P
IN07N
IN08P
IN08N
IN09P
IN09N
Type
PECL/ECL
Power Supply
PECL/ECL
PECL/ECL
Power Supply
PECL/ECL
PECL/ECL
Power Supply
PECL/ECL
PECL/ECL
Power Supply
PECL/ECL
PECL/ECL
Power Supply
PECL/ECL
PECL/ECL
Power Supply
PECL/ECL
PECL/ECL
Power Supply
PECL/ECL
PECL/ECL
Power Supply
PECL/ECL
PECL/ECL
Power Supply
PECL/ECL
P PECL/ECL
Power Supply
PECL/ECL
PECL/ECL
Power Supply
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
Description
High Speed Output
Most Negative PECL Supply (Unique to this Output)
High Speed Output Complement
High Speed Output
Most Negative PECL Supply (Unique to this Output)
High speed Output Complement
High Speed Output
Most Negative PECL Supply (Unique to this Output)
High Speed Output Complement
High Speed Output
Most Negative PECL Supply (Unique to this Output)
High Speed Output Complement
High Speed Output
Most Negative PECL Supply (Unique to this Output)
High Speed Output Complement
High Speed Output
Most Negative PECL Supply (Unique to this Output)
High Speed Output Complement
High Speed Output
Most Negative PECL Supply (Unique to this Output)
High Speed Output Complement
High Speed Output
Most Negative PECL Supply (Unique to this Output)
High Speed Output Complement
High Speed Output
Most Negative PECL Supply (Unique to this Output)
High Speed Output Complement
High Speed Output
Most Negative PECL Supply (Unique to this Output)
High Speed Output Complement
High Speed Output
Most Negative PECL Supply (Unique to this Output)
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
Rev. B | Page 7 of 40
AD8151
Pin No.
130
131
133
134
136
137
140
141
143
144
146
147
150
Mnemonic
IN10P
IN10N
IN11P
IN11N
IN12P
IN12N
IN13P
IN13N
IN14P
IN14N
IN15P
IN15N
VEEREF
Type
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
R Program
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
173
174
176
177
179
180
182
183
REF
VSS
D6
D5
D4
D3
D2
D1
D0
A4
A3
A2
A1
A0
UPDATE
WE
RE
CS
RESET
VDD
IN16P
IN16N
IN17P
IN17N
IN18P
IN18N
IN19P
IN19N
R Program
Power Supply
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
Power Supply
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
PECL/ECL
Description
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
Connection Point for Output Logic Pull-Down Programming Resistor
(Must be Connected to VEE)
Connection Point for Output Logic Pull-Down Programming Resistor
Most Negative Control Logic Supply
Enable/Disable Output
Bit 32—MSB Input Select
Bit 16
Bit 8
Bit 4
Bit 2
Bit 1—LSB Input Select
Bit 16—MSB Output Select
Bit 8
Bit 4
Bit 2
Bit 1—LSB Output Select
Second Rank Program
First Rank Program
Enable Readback
Enable Chip to Accept Programming
Disable All Outputs (Hi-Z)
Most Positive Control Logic Supply
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
High Speed Input
High Speed Input Complement
Rev. B | Page 8 of 40
AD8151
02169-008
02169-005
150mV/DIV
150mV/DIV
TYPICAL PERFORMANCE CHARACTERISTICS
100ps/DIV
70ps/DIV
Figure 5. Eye Pattern 2.5 Gbps, PRBS 23
Figure 8. Eye Pattern 3.2 Gbps, PRBS 23
p-p = 43ps
STD DEV = 8ps
02169-009
02169-006
150mV/DIV
150mV/DIV
p-p = 53ps
STD DEV = 8ps
20ps/DIV
20ps/DIV
Figure 9. Jitter @ 3.2 Gbps, PRBS 23
100
90
90
80
80
70
70
60
50
(CLOCK PERIOD – JITTER p-p)
% EYE WIDTH =
× 100
CLOCK PERIOD
40
60
50
30
20
20
0
0.5
1.0
1.5
2.0
2.5
DATA RATE (Gbps)
3.0
3.5
Figure 7. Eye Width vs. Data Rate, PRBS 23
(VOUT @ DATA RATE)
× 100
VOUT @ 0.5Gbps
40
30
10
% EYE HEIGHT =
02169-010
EYE HEIGHT (%)
100
02169-007
EYE WIDTH (%)
Figure 6. Jitter @ 2.5 Gbps, PRBS 23
10
0
0.5
1.0
1.5
2.0
2.5
DATA RATE (Gbps)
3.0
Figure 10. Eye Height vs. Data Rate, PRBS 23
Rev. B | Page 9 of 40
3.5
AD8151
100
90
90
80
80
70
70
60
50
JITTER (ps)
JITTER (ps)
100
PEAK-PEAK
JITTER
40
60
3.2Gbps JITTER
50
40
30
30
20
20
2.5Gbps JITTER
1.5
2.0
2.5
DATA RATE (Gbps)
3.0
02169-014
STANDARD DEVIATION
0
1.0
3.2Gbps STD DEV
02169-011
10
10
2.5Gbps STD DEV
0
3.5
0
10
20
30
40
50
60
TEMPERATURE (°C)
70
80
90
Figure 14. Jitter vs. Temperature, PRBS 23
Figure 11. Jitter vs. Data Rate, PRBS 23
p-p = 32ps
STD DEV = 4.7ps
02169-015
02169-012
150mV/DIV
150mV/DIV
p-p = 38ps
STD DEV = 7.7ps
75ps/DIV
100ps/DIV
Figure 15. Crosstalk, 3.2 Gbps, PRBS 23, Attack Signal Is Off
Figure 12. Crosstalk, 2.5 Gbps, PRBS 23, Attack Signal Is Off
p-p = 70ps
STD DEV = 9ps
75ps/DIV
100ps/DIV
Figure 16. Crosstalk, 3.2 Gbps, PRBS 23, Attack Signal Is On
Figure 13. Crosstalk, 2.5 Gbps, PRBS 23, Attack Signal Is On
Rev. B | Page 10 of 40
02169-016
02169-013
150mV/DIV
150mV/DIV
p-p = 70ps
STD DEV = 8ps
AD8151
p-p = 43ps
STD DEV = 8ps
02169-020
02169-017
150mV/DIV
150mV/DIV
p-p = 43ps
STD DEV = 8ps
1.4ns/DIV
1.1ns/DIV
Figure 20. Response, 3.2 Gbps,
32-Bit Pattern 1111 1111 0000 0000 0101 0101 0011 0011
100
100
90
90
80
80
PEAK-TO-PEAK JITTER (ps)
70
60
2.5Gbps JITTER
50
40
30
3.2Gbps JITTER
60
50
2.5Gbps
40
30
20
02169-018
20
10
0
0.2
3.2Gbps
70
0.3
0.4
0.5
0.6
0.7
INPUT AMPLITUDE (V)
0.8
0.9
02169-021
PEAK-TO-PEAK JITTER (ps)
Figure 17. Response, 2.5 Gbps,
32-Bit Pattern 1111 1111 0000 0000 0101 0101 0011 0011
10
0
–5.0
1.0
–4.8
–4.4
–4.2
–4.0 –3.8
VEE (V)
–3.6
–3.4
–3.2
–3.0
0
0.2
Figure 21. Jitter vs. Supply, PRBS 23
100
90
90
80
80
PEAK-TO-PEAK JITTER (ps)
100
70
2.5Gbps
60
3.2Gbps
50
40
30
70
3.2Gbps
60
50
2.5Gbps
40
30
10
0
–1.6 –1.4 –1.2 –1.0 –0.8 –0.6 –0.4 –0.2
VIH (V)
0
0.2
0.4
0.6
02169-022
20
20
02169-019
PEAK-TO-PEAK JITTER (ps)
Figure 18. Jitter vs. Single-Ended Input Amplitude, PRBS 23
–4.6
10
0
–1.4
–1.2
–1.0
–0.8
–0.6
VOH (V)
–0.4
–0.2
Figure 22. Jitter vs. VOH, PRBS 23, Output Amplitude = 0.4 V Single-Ended
Figure 19. Jitter vs. VIH, PRBS 23
Rev. B | Page 11 of 40
AD8151
200
100
90
150
PROPAGATION DELAY (ps)
80
FREQUENCY
70
60
50
40
30
100
50
0
–50
–100
10
0
550
570
590
610 630 650 670 690
PROPAGATION DELAY (ps)
710
730
Figure 23. Variation in Channel-to-Channel Delay, All 561 Points
–150
–200
–100
02169-025
02169-023
20
–80
–60 –40 –20
0
20
40
60
NORMALIZED TEMPERATURE (°C)
PRBS
GENERATOR
DATA OUT
1.65kΩ
49.9Ω
AD8151
P
–6dB
VTT
50Ω
105Ω
2.5Gbps
60
DATA OUT
HIGH SPEED
SAMPLING
OSCILLOSCOPE
P
70
–6dB
IN
OUT
N
N
50Ω
50
3.2Gbps
49.9Ω
1.65kΩ
40
VEE
20
10
0
5
10
15
OUTPUT CURRENT (mA)
20
VTT
VCC = 0V, VEE = –3.3V, VTT = –1.6V, VDD = 5V, VSS = 0V
RSET = 1.54kΩ, IOUT = 16mA, VOH = –0.8V, VOL = –1.2V
VIN = 0.8V p-p EXCEPT AS NOTED
25
Figure 24. Jitter vs. IOUT, PRBS 23
Figure 26. Test Circuit
Rev. B | Page 12 of 40
02169-026
VEE
30
02169-024
PEAK-TO-PEAK JITTER (ps)
VCC
VCC
80
100
Figure 25. Propagation Delay, Normalized at 25°C vs. Temperature
100
90
80
AD8151
CONTROL INTERFACE TRUTH TABLES
Table 4. Basic Control Functions
RESET
Control Pins1
CS
WE
RE
UPDATE
Function
0
1
X
1
X
X
X
X
X
X
1
0
0
1
1
1
0
1
0
1
1
0
1
1
0
1
0
0
1
0
Global Reset. Reset all second rank enable bits to zero (disable all outputs).
Control Disable. Ignore all logic (but the signal matrix still functions as programmed). D [6:0]
are high impedance.
Single Output Preprogram. Write input configuration data from Data Bus D [6:0] into first rank
of latches for the output selected by the Output Address Bus A [4:0].
Single Output Readback. Readback input configuration data from second rank of latches onto
Data Bus D [6:0] for the single output selected by the Output Address Bus A [4:0].
Global Update. Copy input configuration data from all 17 first rank latches into second rank of
latches, updating signal matrix connections for all outputs.
Transparent Write and Update. It is possible to write data directly onto rank two. This simplifies
logic when synchronous signal matrix updating is not necessary.
1
X means don’t care.
Table 5. Address/Data Examples
Input Address Pins MSB–LSB1
Output Address Pins
MSB–LSB
A4 A3 A2 A1 A0
0
0
0
0
0
Enable
Bit 1
D6/E
X
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
1
X
1
0
0
0
0
0
0
0
0
0
Binary Output Number 2
1
Binary Output Number2
1
0
0
0
1
0
X
X
X
X
X
X
Binary Input Number
X
1
X
1
0
1
1
2
0
0
1
0
Binary Input Number
0
0
0
Function
Lower Address/Data Range. Connect Output 00
(A[4:0] = 00000) to Input 00 (D[5:0] = 000000).
Upper Address/Data Range. Connect Output 16
(A[4:0] = 10000) to Input 32 (D[5:0] = 100000).
Enable Output. Connect Selected Output (A[4:0] = 0 to 16) to
Designated Input (D[5:0] = 0 to 32) and Enable Output
(D6 = 1).
Disable Output. Disable Specified Output (D6 = 0).
Broadcast Connection. Connect all 17 outputs to same
designated input and set all 17 enable bits to D6. Readback is
not possible with the broadcast address.
Reserved. Any address or data code greater or equal to these
are reserved for future expansion or factory testing.
X means don’t care.
The binary output number can also be the broadcast connection designator, 10001.
Rev. B | Page 13 of 40
AD8151
CONTROL INTERFACE TIMING DIAGRAMS
CS INPUTS
WE INPUTS
A[4:0] INPUTS
D[6:0] INPUTS
tCSW
tCHW
tASW
tAHW
tWP
02169-027
tDSW
tDHW
Figure 27. First Rank Write Cycle
Table 6. First Rank Write Cycle
Parameter
Setup Time
Hold Time
Enable Pulse
Mnemonic
tCSW
tASW
tDSW
tCHW
tAHW
tDHW
tWP
Description
Chip select to write enable
Address to write enable
Data to write enable
Chip select from write enable
Address from write enable
Data from write enable
Width of write enable pulse
Conditions
TA = 25°C
VDD = 5 V
VCC = 3.3 V
Min
0
0
15
0
0
0
15
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
CS INPUTS
UPDATE INPUTS
ENABLING
OUT[0:16][N:P]
OUTPUTS
TOGGLE
OUT[0:16][N:P]
OUTPUTS
DISABLING
OUT[0:16][N:P]
OUTPUTS
DATA FROM RANK 1
PREVIOUS RANK 2 DATA
DATA FROM RANK 1
DATA FROM RANK 2
tCSU
tUW
tCHU
tUOE
02169-028
tUOD
tUOT
Figure 28. Second Rank Update Cycle
Table 7. Second Rank Update Cycle
Parameter
Setup Time
Hold Time
Output Enable Times
Output Toggle Times
Output Disable Times
Update Pulse
Mnemonic
tCSU
tCHU
tUOE
tUOT
tUOD
tUW
Function
Chip select to update
Chip select from update
Update to output enable
Update to output reprogram
Update to output disabled
Width of update pulse
Rev. B | Page 14 of 40
Conditions
TA = 25°C
VDD = 5 V
VCC = 3.3 V
Min
0
15
Typ
Max
25
25
25
40
40
30
Unit
ns
ns
ns
ns
ns
ns
AD8151
CS INPUTS
UPDATE INPUTS
WE INPUTS
ENABLING
OUT[0:16][N:P]
OUTPUTS
INPUT {DATA 1}
INPUT {DATA 0}
INPUT {DATA 1}
tCSU
tCHU
tUW
tUOT
tWOT
tUOE
tWHU
tWOD
02169-029
DISABLING
OUT[0:16][N:P]
OUTPUTS
INPUT {DATA 2}
Figure 29. First Rank Write Cycle and Second Rank Update Cycle
Table 8. First Rank Write Cycle and Second Rank Update Cycle
Parameter
Setup Time
Hold Time
Output Enable Times
Output Toggle Times
Output Disable Times
Setup Time
Update Pulse
1
Mnemonic
tCSU
tCHU
tUOE
tWOE
tUOT
tWOT
tUOD 1
tWOD
tWHU
tUW
D
Function
Chip select to update
Chip select from update
Update to output enable
Write enable to output enable
Update to output reprogram
Write enable to output reprogram
Update to output disabled
Write enable to output disabled
Write enable to update
Width of update pulse
Conditions
TA = 25°C
VDD = 5 V
VCC = 3.3 V
Min
0
0
Typ
Max
25
25
25
25
25
25
40
40
30
30
30
30
Typ
Max
15
15
15
30
10
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Not shown.
CS INPUTS
RE INPUTS
A[4:0]
INPUTS
ADDR 1
D[6:0]
OUTPUTS
ADDR 2
DATA
{ADDR 1}
tCSR
tRDE
DATA
{ADDR 2}
tCHR
tAA
02169-030
tRHA
tRDD
Figure 30. Second Rank Readback Cycle
Table 9. Second Rank Readback Cycle
Parameter
Setup Time
Hold Time
Read Enable
Enable Time
Access Time
Release Time
Mnemonic
tCSR
tCHR
tRHA
tRDE
tAA
tRDD
Function
Chip select to read enable
Chip select from read enable
Address from read enable
Data from read enable
Data from address
Data from read enable
Rev. B | Page 15 of 40
Conditions
TA = 25°C
VDD = 5 V
VCC = 3.3 V
10 kΩ
20 pF on D[6:0]
Bus
Min
0
0
5
Unit
ns
ns
ns
ns
ns
ns
AD8151
RESET INPUTS
DISABLING
OUT[0:16][N:P]
OUTPUTS
02169-031
tTOD
tTW
Figure 31. Asynchronous Reset
Table 10. Asynchronous Reset
Parameter
Disable Time
Width of Reset Pulse
Mnemonic
tTOD
tTW
Function
Output disable from reset
Conditions
TA = 25°C
VDD = 5 V
VCC = 3.3 V
Min
Typ
25
Max
30
15
Unit
ns
ns
CONTROL INTERFACE PROGRAMMING EXAMPLE
The following conservative pattern connects all outputs to Input 7, except Output 16, which is connected to Input 32. The vector clock
period t0 is 15 ns. It is possible to accelerate the execution of this pattern by deleting Vectors 1, 4, 7, and 9.
Table 11. Basic Test Pattern
Vector No.
RESET
CS
WE
RE
UPDATE
A[4:0]
D[6:0]
Comments
0
1
2
3
4
5
6
7
8
9
10
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
xxxxx
xxxxx
10001
10001
10001
10000
10000
10000
xxxxx
xxxxx
xxxxx
xxxxxxx
xxxxxxx
1000111
1000111
1000111
1100000
1100000
1100000
xxxxxxx
xxxxxxx
xxxxxxx
Disable all outputs
Rev. B | Page 16 of 40
All outputs connected to Input 7
Write to first rank
Connects Output 16 to Input 32
Write to first rank
Transfer to second rank
Disable interface
AD8151
CONTROL INTERFACE
7
UPDATE RESET
D[0:6]
7
7
7
7
7
7
7
7
0
0
1
1
2
2
16
16
RANK 1
RANK 2
7
TO 17 × 33
SWITCH
MATRIX
33
7
7
7
33
7
7
33
7
7
33
17 ROWS OF 7-BIT
LATCHES
1 OF 33
DECODERS
To facilitate multiple chip address decoding, there is a chipselect pin. All logic signals except the reset pulse are ignored
unless the chip select pin is active. The chip select pin disables
only the control logic interface and does not change the
operation of the signal matrix. The chip select pin does not
power down any of the latches, so any data programmed in the
latches is preserved.
All control pins are level-sensitive, not edge-triggered.
CONTROL PIN DESCRIPTION
WE
A[4:0] Inputs
Output address pins. The binary encoded address applied to
these 5 input pins determines which one of the 17 outputs is
being programmed (or being read back). The most significant
bit (MSB) is A4.
A[0:4]
02169-031
1 OF 17 DECODERS
RE
Figure 32. Control Interface (Simplified Schematic)
The AD8151 control interface receives and stores the desired
connection matrix for the 33 input and 17 output signal pairs.
The interface consists of 17 rows of double-rank 7-bit latches,
1 row for each output. The 7-bit data-word stored in each of
these latches indicates to which (if any) of the 33 inputs the
output is connected.
One output at a time can be preprogrammed by addressing the
output and writing the desired connection data into the first
rank of latches. This process can be repeated until each of the
desired output changes has been preprogrammed. All output
connections can then be programmed at once by passing the
data from the first rank of latches into the second rank. The
output connections always reflect the data programmed into the
second rank of latches and do not change until the first rank of
data is passed into the second rank.
If necessary for system verification, the data in the second rank
of latches can be read back from the control interface.
At any time, a reset pulse can be applied to the control interface
to globally reset the appropriate second rank data bits, disabling
all 17 signal output pairs. This feature can be used to avoid
output bus contention on system startup. The contents of the
first rank remain unchanged.
The control interface pins are connected via logic-level translators. These translators allow programming and readback of
the control interface using logic levels different from those in
the signal matrix.
D[6:0] Inputs/Outputs
Input configuration data pins. In write mode, the binary
encoded data applied to the D pins [6:0] determines which of
33 inputs is to be connected to the output specified with the
A pins [4:0]. The MSB is D5 and the least significant bit (LSB) is
D0. Bit D6 is the enable bit, setting the specified output signal
pair to an enabled state if D6 is logic high or disabled to a high
impedance state if D6 is logic low. In readback mode, the
D pins [6:0] are low impedance outputs, indicating the dataword stored in the second rank for the output specified with the
A pins [4:0]. The readback drivers are designed to drive high
impedances only, so external drivers connected to the D
pins [6:0] should be disabled during readback mode.
WE Input
First Rank Write Enable. Forcing this pin to logic low allows the
data on the D pins [6:0] to be stored in the first rank latch for
the output specified by the A pins [4:0]. The WE pin must be
returned to a logic high state after a write cycle to avoid
overwriting the first rank data.
UPDATE Input
Second Rank Write Enable. Forcing this pin to logic low allows
the data stored in all 17 first rank latches to be transferred to the
second rank latches. The signal connection matrix is reprogrammed when the second rank data is changed. This is a
global pin, transferring all 17 rows of data at once. It is not
necessary to program the address pins. It should be noted that
after the initial power-up of the device, the first rank data is
undefined. It may be desirable to preprogram all 17 outputs
before performing the first update cycle.
Rev. B | Page 17 of 40
AD8151
RE Input
Second Rank Read-Enable. Forcing this pin to logic low enables
the output drivers on the bidirectional D pins [6:0], entering
the readback mode of operation. By selecting an output address
with the A pins [4:0] and forcing RE to logic low, the 7-bit
data stored in the second rank latch for that output address is
written to the D pins [6:0]. Data should not be written to the
D pins [6:0] externally while in readback mode.
The RE and WE pins are not exclusive, and can be used at the
same time, but data should not be written to the D pins [6:0]
from external sources while in readback mode.
CS Input
Chip-Select. This pin must be forced to logic low to program or
receive data from the logic interface, with the exception of the
RESET pin, described in the next section. This pin has no
effect on the signal pairs and does not alter any of the stored
control data.
RESET Input
It is useful to momentarily hold RESET at a logic low state when
powering up the AD8151 in a system that has multiple output
signal pairs connected together. Failure to do this can result in
several signal outputs contending after power-up. The RESET
pin is not gated by the state of the chip-select pin, CS. It should
be noted that the RESET pin does not program the first rank,
which contains undefined data after power-up.
CONTROL INTERFACE TRANSLATORS
The AD8151 control interface has two supply pins, VDD and VSS.
The potential between the positive logic supply, VDD, and the
negative logic supply, VSS, must be at least 3 V and no more than
5 V. Regardless of supply, the logic threshold is approximately
1.6 V above VSS, allowing the interface to be used with most
CMOS and TTL logic drivers. The signal matrix supplies, VCC
and VEE, can be set independently of the voltage on VDD and VSS,
with the constraints that (VDD − VEE) ≤ 10 V. These constraints
allow operation of the control interface on 3 V or 5 V, while the
signal matrix is operated on 3.3 V or 5 V PECL or –3.3 V or
–5 V ECL.
Global Output Disable Pin. Forcing the RESET pin to logic low
resets the enable bit, D6, in all 17 second rank latches,
regardless of the state of any of the other pins. This has the
effect of immediately disabling the 17 output signal pairs in the
matrix.
Rev. B | Page 18 of 40
AD8151
CIRCUIT DESCRIPTION
High Speed Data Inputs (INxxP, INxxN)
The AD8151 has 33 pairs of differential voltage-mode inputs.
The common-mode input range extends from the positive
supply voltage (VCC) down to include standard ECL or PECL
input levels (VCC – 2 V). The minimum differential input
voltage is 200 mV. Unused inputs may be connected directly to
any level within the allowed common-mode input range. A
simplified schematic of the input circuit is shown in Figure 33.
VCC
VEE
02169-033
INxxN
INxxP
Figure 33. Simplified Input Circuit
To maintain signal fidelity at the high data rates supported by
the AD8151, the input transmission lines should be terminated
as close to the input pins as possible. The preferred input
termination structure depends primarily on the application and
the output circuit of the data source. Standard ECL components
have open emitter outputs that require pull-down resistors.
Three input termination networks suitable for this type of
source are shown in Figure 34. The characteristic impedance of
the transmission line is shown as ZO. The resistors, R1 and R2,
in the Thevenin termination are chosen to synthesize a VTT
source with an output resistance of ZO and an open-circuit
output voltage equal to VCC – 2 V. The load resistors (RL) in the
differential termination scheme are needed to bias the emitter
followers of the ECL source.
VCC
VCC
VCC – 2V
ZO R1
ZO
R1
INxxN
INxxN
ZO
ZO
INxxP
ECL SOURCE
ZO
INxxP
ZO
R2
ECL SOURCE
VTT = VCC – 2V
R2
VEE
(a)
(b)
VCC
ZO
INxxN
2ZO
ZO
INxxP
RL
RL
02169-034
ECL SOURCE
VEE
(c)
Figure 34. AD8151 Input Termination from ECL/PECL Sources: (a) Parallel
Termination Using VTT Supply, (b) Thevenin Equivalent Termination,
and (c) Differential Termination
If the AD8151 is driven from a current-mode output stage such
as another AD8151, the input termination should be chosen to
accommodate that type of source, as explained in the following
section.
High speed Data Outputs (OUTyyP, OUTyyN)
The AD8151 has 17 pairs of differential current-mode outputs.
The output circuit, shown in Figure 35, is an open-collector
NPN current switch with resistor-programmable tail current
and output compliance extending from the positive supply
voltage (VCC) down to standard ECL or PECL output levels
(VCC − 2 V). The outputs can be disabled individually to permit
outputs from multiple AD8151s to be connected directly. Since
the output currents of multiple enabled output stages sum when
directly connected, care should be taken to ensure that the
output compliance limit is not exceeded at any time by disabling
the active output driver before enabling an inactive driver.
VCC
OUTyyP
OUTyyN
VCC – 2V
IOUT
DISABLE
VEE
VEE
Figure 35. Simplified Output Circuit
Rev. B | Page 19 of 40
02169-035
The AD8151 is a high speed 33 × 17 differential crosspoint
switch designed for data rates up to 3.2 Gbps per channel. The
AD8151 supports PECL-compatible input and output levels
when operated from a 5 V supply (VCC = 5 V, VEE = GND), or
ECL-compatible levels when operated from a –5 V supply
(VCC = GND, VEE = –5 V). To save power, the AD8151 can run
from a +3.3 V supply to interface with low voltage PECL
circuits or a –3.3 V supply to interface with low voltage ECL
circuits. The AD8151 utilizes differential current-mode outputs
with an individual disable control, which facilitates busing the
outputs of multiple AD8151s together to assemble larger switch
arrays. This feature also reduces system crosstalk and can
greatly reduce power dissipation in a large switch array. A single
external resistor programs the current for all enabled output
stages, allowing user control over output levels with different
output termination schemes and transmission line
characteristic impedances.
AD8151
To ensure proper operation, all outputs (including unused
output) must be pulled high using external pull-up networks to
a level within the output compliance range. If outputs from
multiple AD8151s are wired together, a single pull-up network
can be used for each output bus. The pull-up network should be
chosen to keep the output voltage levels within the output
compliance range at all times. Recommended pull-up networks
to produce PECL/ECL 100 kΩ and 10 kΩ compatible outputs
are shown in Figure 36. Alternatively, a separate supply can be
used to provide VCOM, making RCOM and DCOM unnecessary.
VCC
VCC
RCOM
VCOM
RL
AD8151
RL
OUTyyN
OUTyyN
OUTyyP
OUTyyP
VCOM
RL
RL
VOH = VCOM – (¼)IOUTRL
VOL = VCOM – (¾)IOUTRL
VSWING = VOH – VOL = (½)IOUTRL
Output Current Set Pin (REF)
A simplified schematic of the reference circuit is shown in
Figure 38. A single external resistor connected between the REF
pin and VEE determines the output current for all output stages.
This feature allows a choice of pull-up networks and transmission line characteristic impedances while still achieving a
nominal output swing of 800 mV. At low data rates, substantial
power savings can be achieved by using lower output swings
and higher load resistances.
02169-036
AD8151
DCOM
In this case, the output levels are
AD8151
IOUT/20
VCC
Figure 36. Output Pull-Up Networks for PECL/ECL: a) 100 kΩ and b) 10kΩ
RSET
VOH = VCOM
VOL = VCOM – IOUTRL
VSWING = VOH − VOL = IOUTRL
VCOM = VCC – IOUTRCOM (100 kΩ mode)
VCOM = VCC – V(DCOM) (10 kΩ mode)
VEE
Figure 38. Simplified Reference Circuit
The nominal output current is given by the following:
The common-mode adjustment element (RCOM or DCOM) can be
omitted if the input range of the receiver includes the positive
supply voltage. The bypass capacitors reduce common-mode
perturbations by providing an ac short from the common nodes
(VCOM) to ground. When busing together the outputs of
multiple AD8151s or when running at high data rates, double
termination of its outputs is recommended to mitigate the
impact of reflections due to open transmission line stubs and
the lumped capacitance of the AD8151 output pins. A possible
connection is shown in Figure 37; the bypass capacitors provide
an ac short from the common nodes of the termination resistors
to ground. To maintain signal fidelity at high data rates, the
stubs connecting the output pins to the output transmission
lines or load resistors should be as short as possible.
VCC
RCOM
AD8151
VCOM
RL
RL
OUTyyN
OUTyyP
AD8151
REF
1.2V
02169-038
The output levels are
⎛ 1.2 V ⎞
IOUT = 20⎜
⎟
⎝ RSET ⎠
The minimum set resistor is RSET, MIN = 960 Ω resulting in
IOUT, MAX = 25 mA. The maximum set resistor is RSET, MAX = 4.8 kΩ
resulting in IOUT, MIN = 5 mA. Nominal 800 mV differential
output swing can be achieved in a 50 Ω load using RSET = 1.5 kΩ
(IOUT = 16 mA), or in a doubly terminated 75 Ω load using
RSET = 1.13 kΩ (IOUT = 21.3 mA). To minimize stray capacitance
and avoid the pickup of unwanted signals, the external set
resistor should be located close to the REF pin. Bypassing the
set resistor is not recommended.
Power Supplies
There are several options for the power supply voltages for the
AD8151, as there are two separate sections of the chip that
require power supplies. These are the control logic and the high
speed data paths. Depending on the system architecture, the
voltage levels of these supplies can vary.
Logic Supplies
ZO
ZO
OUTyyN
OUTyyP
ZO
ZO
RL
RECEIVER
02169-037
RL
Figure 37. Double Termination of AD8151 Outputs
The control (programming) logic is CMOS and is designed to
interface with any of the standard single-ended logic families
(CMOS or TTL). Its supply voltage pins are VDD (Pin 170, logic
positive) and VSS (Pin 152, logic ground). In all cases the logic
ground should be connected to the system digital ground. VDD
should be supplied at between 3.3 V to 5 V to match the supply
voltage of the logic family that is used to drive the logic inputs.
VDD should be bypassed to ground with a 0.1 μF ceramic capacitor. The absolute maximum voltage from VDD to VSS is 5.5 V.
Rev. B | Page 20 of 40
AD8151
Data Path Supplies
POWER DISSIPATION
The data path supplies have more options for their voltage levels.
The choices here affect several other areas, such as power
dissipation, bypassing, and common-mode levels of the inputs
and outputs. The more positive voltage supply for the data paths
is VCC (Pin 41, Pin 98, Pin 149, and Pin 171). The more negative
supply is VEE, which appears on many pins that are not listed here.
The maximum allowable voltage across these supplies is 5.5 V.
The first choice in the data path power supplies is to decide
whether to run the device as ECL or PECL. For ECL operation,
VCC is at ground potential, while VEE is at a negative supply
between –3.3 V to –5 V. This makes the common-mode voltage
of the inputs and outputs a negative voltage (see Figure 39).
For analysis, the power dissipation of the AD8151 can be
divided into three separate parts. These are the control logic,
the data path circuits, and the (ECL or PECL) outputs, which
are part of the data path circuits but can be dealt with
separately. The control logic is CMOS technology and does not
dissipate a significant amount of power. This power is, of
course, greater when the logic supply is 5 V rather than 3 V, but
overall it is not a significant amount of power and can be
ignored for thermal analysis.
VDD
VCC
ROUT
AD8151
IOUT
GND
0.1μF
VDD
I, DATA PATH
LOGIC
VCC
VSS
AD8151
CONTROL
LOGIC
VSS
GND
DATA
PATHS
02169-039
0.1μF
(ONE FOR EVERY TWO VEE PINS)
GND
–3.3V TO –5V
Figure 39. Power Supplies and Bypassing for ECL Operation
The proper way to run the device is to dc-couple the data paths
to other ECL logic devices that use ground as the most positive
supply and use a negative voltage for VEE. However, if the part is
to be ac-coupled, it is not necessary to have the input/output
common mode at the same level as the other system circuits,
but it is probably more convenient to use the same supply rails
for all devices. For PECL operation, VEE is at ground potential
and VCC is a positive voltage from 3.3 V to 5 V. Thus, the
common mode of the inputs and outputs is at a positive voltage.
These can then be dc-coupled to other PECL operated devices.
If the data paths are ac-coupled, then the common-mode levels
do not matter (see Figure 40).
+3.3V TO +5V
0.1μF
VDD
VCC
0.1μF
(ONE FOR EACH VCC PIN,
4 REQUIRED)
AD8151
VSS
GND
DATA
PATHS
VEE
GND
02169-040
CONTROL
LOGIC
VOUT LOW – VEE
VEE
GND
Figure 41. Major Power Consumption Paths
VEE
+3.3V TO +5V
DATA
PATHS
CONTROL
LOGIC
02169-041
+3.3V TO +5V
Figure 40. Power Supplies and Bypassing for PECL Operation
The data path circuits operate between the supplies VCC and
VEE. As described in the power supply section, this voltage can
range from 3.3 V to 5 V. The current consumed by this section
is constant, so operating at a lower voltage can decrease power
dissipation by about 35 percent. The power dissipated in the
data path outputs is affected by several factors. The first is
whether the outputs are enabled or disabled. The worst case
occurs when all of the outputs are enabled. The current
consumed by the data path logic can be approximated by
ICC = 35 mA + [IOUT/20 mA × 3 mA)] × (no. of outputs enabled)
This equation states that a minimum ICC of 35 mA always flows.
ICC increases by a factor that is proportional to both the number
of enabled outputs and the programmed output current.
The power dissipated in this circuit section is simply the voltage
of this section (VCC – VEE) times the current. To calculate the
worst case, assume that VCC – VEE is 5.0 V, all outputs are
enabled, and the programmed output current is 25 mA. The
power dissipated by the data path logic is
P = 5.0 V {35 mA + [4.5 mA + (25 mA/20 mA × 3 mA)] × 17} = 876 mW
The power dissipated by the output current depends on several
factors. These are the programmed output current, the voltage
drop from a logic low output to VEE, and the number of enabled
outputs. A simplifying assumption is that one of each (enabled)
differential output pair is low and draws the full output current
(and dissipates most of the power for that output), while the
complementary output of the pair is high and draws insignificant current.
Rev. B | Page 21 of 40
AD8151
Thus, the power dissipation of the high output can be ignored and
the output power dissipation for each output can be assumed to
occur in a single static low output that sinks the full output programmed current. The voltage across which this current flows can
also vary, depending on the output circuit design and the supplies
that are used for the data path circuitry. In general, however, there
is a voltage difference between a logic low signal and VEE. This is
the drop across which the output current flows. For a worst case,
this voltage can be as high as 3.5 V. Thus, for all outputs enabled
and the programmed output current set to 25 mA, the power
dissipated by the outputs is
P = 3.5 V (25 mA) × 17 = 1.49 W
Heat Sinking
Depending on several factors in its operation, the AD8151 can
dissipate upwards of 2 W or more. The part is designed to
operate without the need for an explicit external heat sink.
However, the package design offers enhanced heat removal via
some of the package pins to the PC board traces. The VEE pins
on the input sides of the package (Pin 1 to Pin 46 and Pin 93 to
Pin 138) have finger extensions inside the package that connect
to the paddle upon which the IC chip is mounted. These pins
provide a lower thermal resistance from the IC to the VEE pins
than other pins that just have a bond wire. As a result, these
pins can be used to enhance the heat removal process from the
IC to the circuit board and ultimately to the ambient. The VEE
pins described earlier should be connected to a large area of
circuit board trace material to take the most advantage of their
lower thermal resistance. If there is a large area available on an
inner layer that is at VEE potential, then vias can be provided
from the package pin traces to this layer.
There should be no thermal-relief pattern when connecting the
vias to the inner layers for these VEE pins. Additional vias in
parallel and close to the pin leads can provide an even lower
thermal resistive path. If possible, use 2 oz copper foil to
provide better heat removal than 1 oz copper foil. The AD8151
package has a specified thermal impedance θJA of 30°C/W. This
is the worst case still-air value that can be expected when the
circuit board does not significantly enhance the heat removal
from the package. By using the concept described earlier or by
using forced-air circulation, the thermal impedance can be
lowered.
For an extreme worst case analysis, the junction temperature
increase above the ambient can be calculated assuming 2 W of
power dissipation and a θJA of 30°C/W to yield a 60°C rise above
the ambient. There are many techniques described earlier that
can mitigate this situation. Most actual circuits do not result in
this high an increase of the junction temperature above the
ambient.
Rev. B | Page 22 of 40
AD8151
APPLICATIONS
INPUT AND OUTPUT BUSING
Although the AD8151 is a digital part, in any application that
runs at high speed, analog design details have to be given very
careful consideration. At high data rates, the design of the signal
channels have a strong influence on data integrity and its
associated jitter and ultimately bit error rate (BER).
While it might be considered very helpful to have a suggested
circuit board layout for any particular system configuration, this
is not something that can be practically realized. Systems come
in all shapes, sizes, speeds, performance criteria, and cost constraints. Therefore, some general design guidelines are presented that can be used for all systems and judiciously modified
where appropriate.
High speed signals travel best, that is, they maintain their
integrity when they are carried by a uniform transmission line
that is properly terminated at either end. Any abrupt mismatches in impedance or improper termination creates
reflections that add to or subtract from parts of the desired
signal. Small amounts of this effect are unavoidable, but too
much distorts the signal to the point that the channel
BER increases. It is difficult to fully quantify these effects
because they are influenced by many factors in the overall
system design.
A constant-impedance transmission line is characterized by
having a uniform cross-section profile over its entire length. In
particular, there should be no stubs, which are branches that
intersect the main run of the transmission line. These can have
an electrical appearance that is approximated by a lumped
element, such as a capacitor, or if long enough, by another
transmission line. If stubs are unavoidable in a design, their
effect can be minimized by making them as short as possible
and as high an impedance as possible.
Figure 37 shows a differential transmission line that connects
two differential outputs from the AD8151 to a generic receiver.
A more generalized system can have more outputs bused and
more receivers on the same bus, but the same concepts apply.
The inputs of the AD8151 can also be considered as a receiver.
The transmission lines that bus the devices together are shown
with terminations at each end.
The individual outputs of the AD8151 are stubs that intersect
the main transmission line. Ideally, their current source outputs
would be infinite impedance, and they would have no effect on
signals that propagate along the transmission line. In reality,
each external pin of the AD8151 projects into the package and
has a bond wire connected to the chip inside. On-chip wiring
then connects to the collectors of the output transistors and to
ESD protection diodes.
Unlike some other high speed digital components, the AD8151
does not have on-chip terminations. While this location would
be closer to the actual end of the transmission line for some
architectures, this concept can limit system design options. In
particular, it is not possible to bus more than two inputs or
outputs on the same transmission line and it is also not possible
to change the value of these terminations to use for different
impedance transmission lines. The AD8151, with the added
ability to disable its outputs, is much more versatile in these
types of architectures.
If the external traces are kept to a bare minimum, then the
output presents a mostly lumped capacitive load of about 2 pF.
A single stub of 2 pF does not adversely affect signal integrity to
a large extent for most transmission lines, but the more of these
stubs, the greater their adverse influence.
One way to mitigate this effect is to locally reduce the capacitance of the main transmission line near the point of stub
intersection. Some practical means for doing this are to narrow
the PC board traces in the region of the stub and/or to remove
some of the ground plane(s) near this intersection. The effect of
these techniques is to locally lower the capacitance of the main
transmission line at these points, while the added capacitance of
the AD8151 outputs compensate for this reduction in capacitance. The overall intent is to create as uniform a transmission
line as possible.
In selecting the location of the termination resistors, it is
important to keep in mind that, as their name implies, they
should be placed at either end of the line. There should be
minimal or no projection of the transmission line beyond the
point where it connects to the termination resistors.
EVALUATION BOARD
An evaluation board has been designed and is available to
rapidly test the main features of the AD8151. This board allows
the user to analyze the analog performance of the AD8151
channels and easily control the configuration of the board with
a PC. The board has limited numbers of differential input/
output pairs. Each differential pair of microstrips is connected
to either top mount or side launch SMA connectors. The top
mount SMA connectors are drilled and stubbed for superior
performance. The FR4 type board contains a total of nine
outputs (all even numbered outputs) and 20 inputs (0, 2, 4, 6, 8,
10, 12, 13, 14, 15, 16, 17, 18, 20, 22, 24, 26, 28, 30, 32). It is
important to note that the shells of the SMA connectors are
attached to VCC. This makes only ECL or negative level swings
possible during testing.
Rev. B | Page 23 of 40
AD8151
POWER SUPPLIES
The AD8151 is designed to work with standard ECL logic
levels. This means that VCC is at ground and VEE is at a negative
supply. The shells of the I/O SMA connectors are at VCC
potential. Thus, when operating in the standard ECL
configuration, test equipment can be directly connected to the
board, since the test equipment also has its connector shells at
ground potential.
Operating in PECL mode requires VCC to be at a positive
voltage while VEE is at ground. Since this generates a positive
voltage at the shells of the I/O connectors, it can cause problems
when directly connecting to test equipment. Some equipment,
such as battery-operated oscilloscopes, can be floated from
ground, but care should be taken with line-powered equipment
to avoid creating a dangerous situation. Refer to the manual of
the test equipment that is being used.
The voltage difference from VCC to VEE can range from 3 V to
5 V. Power savings can be realized by operating at a lower
voltage without any compromise in performance.
A separate connection is provided for VTT, the termination
potential of the outputs. This can be at a voltage as high as VCC,
but power savings can be realized if VTT is at a voltage that is
somewhat lower.
As a practical matter, current on the evaluation board flows
from the VTT supply through the termination resistors into the
multiple outputs of the AD8151 and to the VEE supply. When
running in ECL mode, VTT should be at a negative supply.
Most power supplies do not allow a simultaneous ground
connection to VCC and a negative supply at VTT, because it
would force the source current to originate from a negative
supply, which wants to flow to the more-negative VEE. In this
case, the source current does not then return to the ground
terminal of the VTT supply. Thus, VTT should be referenced to
VEE when running in ECL mode or a true bipolar supply should
be used.
The digital supply is provided to the AD8151 by the VDD and
VSS pins. VSS should always be at ground potential to make it
compatible with standard CMOS or TTL logic. VDD can range
from 3 V to 5 V, and should be matched to the supply voltage of
the logic used to control the AD8151. However, since PCs use
5 V logic on their parallel port, VDD should be 5 V when using a
PC to program the AD8151.
There are additional higher value capacitors elsewhere on the
board for bypassing at lower frequencies. The location of these
capacitors is not as critical.
Input and Output Considerations
Each input contains a 100 Ω differential termination. Although
differential termination eases board layout due to its compact
nature, it can cause problems with the driving generator. A typical
pulse or pattern generator wants to see 50 Ω to ground (or to –2 V
in some cases). High speed probing of the input has shown that if
this type of termination is not present, input amplitudes can be
slightly off. The dc input levels can be even more affected.
Depending on the generator used, these levels can be off as much as
800 mV in either direction. A correction for this problem is to
attach a 6 dB attenuator to each P and N input. Because the
AD8151 has a large common-mode voltage range on its input
stage, it is not significantly affected by dc level errors.
On this evaluation board, all unused inputs are tied to VCC
(GND). All outputs, whether attached to connectors or not, are
tied to VTT through a 49.9 Ω resistor. The AD8151 device is on
the component side of the board, while input terminations and
output back terminations are on the circuit side. The input
signals from the circuit side transit through via holes to the
DUT’s pads. The component-side output signals connect to via
holes and to circuit-side 49.9 Ω termination resistors.
Board Construction
For this board, FR4 material was chosen over more exotic board
materials. Tests show exotic materials are unnecessary. This is a
4-layer board, so power is bused on both external and internal
layers. Test structures show microstrip performance is unaffected by the dc bias levels on the plane beneath it.
The board manufacturing process should ensure a controlled
impedance board. The board stack consists of a 5-mil-thick
layer between external and internal layers. This allows the use of
an 8-mil-wide microstrip trace running from the SMA connector to the DUT’s pads. The narrow trace eliminates the need
to reduce the trace width as the DUT’s pads are approached and
helps to control the microstrip trace impedance. The thin 5-mil
dielectric also reduces crosstalk by confining the electromagnetic fields between the trace and the plane below.
Bypassing
Most of the board’s bypass capacitors are opposite the DUT on
the solder side and are connected between VCC and VEE. This is
where they are most effective. For low inductance, use 0.01 μF
ceramic chip capacitors.
Rev. B | Page 24 of 40
AD8151
CONFIGURATION PROGRAMMING
The board is configurable by one of two methods. For ease of
use, custom software is provided that controls the AD8151
programming via the parallel port of a PC. This requires a
standard printer cable that has a DB-25 connector at one end
(parallel-port or printer-port interface) and a Centronix
connector at the other, which connects to P2 of the AD8151
evaluation board. The programming with this setup is serial, so
it is not the fastest way to configure the AD8151 matrix.
However, the user interface makes it very convenient to use this
programming method.
After running the software, the user is prompted to identify
which of three software drivers is used with the PC parallel
port. The default is LPT1, which is most commonly used.
However, some laptops commonly use the PRN driver. It is also
possible that some systems are configured with the LPT2 driver.
If it is not known which driver is used, it is best to select LPT1
and proceed to the next screen, which displays the buttons that
allow the connection of inputs to outputs of the AD8151. All of
the outputs should be in the output off state after the program
starts running. Any of the active buttons can be selected by
clicking the mouse, which sends out a burst of programming
data.
If a high speed programming interface is desired, the AD8151
address and data buses are directly available on P3. The source
of the program signals can be a piece of test equipment such as
the Tektronix HFS-9000 digital test generator or other hardware
that generates programming signals. When using the PC interface, the jumper at W1 should be installed and no connections
should be made to P3. When using the P3 interface, no jumper
is installed at W1. There are locations for termination resistors
for the address and data signals, if needed.
After the software driver has been selected, the user can
generate a steady stream of programming signals out of the
parallel port by holding down the left or right arrow key on the
keyboard. The clock test point on the AD8151 evaluation board
can be monitored with an oscilloscope for any activity (a usersupplied printer cable must be connected). If there is a squarewave present, the proper software driver is selected for the PC’s
parallel port.
If there is no signal present, select another driver by clicking
Parallel Port on the File menu. Select a different software
driver and carry out the test described previously until signal
activity is present at the clock test point.
SOFTWARE INSTALLATION
The software to operate the AD8151 is provided on two 3.5"
floppy disks. To install the software on a PC:
1.
Insert Disk 1 into the floppy disk drive.
2.
Run the setup.exe program. This program routinely installs
the software.
3.
Insert Disk 2 when prompted.
4.
Select a program directory when prompted.
Rev. B | Page 25 of 40
AD8151
SOFTWARE OPERATION
Click any button in the matrix to program the input to output
connection. This sends the proper programming sequence out
the PC parallel port. Since only one input can be programmed
to a given output at one time, clicking a button in a horizontal
row cancels the other selection that is already selected in that
row. However, any number of outputs can share the same input.
A shortcut for programming all outputs to the same input is to
use the broadcast feature. Click Broadcast Connection and a
screen appears that prompts the user to select which input
should be connected to all outputs. Type in an integer from 0 to
32 and then click OK.
This sends out the proper program data and returns to the main
screen with a full column of buttons selected under the chosen
input.
The Off column can be used to disable the desired output. To
disable all outputs, click Global Reset. This button selects a full
column of Off buttons.
Two scratch pad memories (Memory 1 and Memory 2) are
provided to conveniently save a particular configuration.
However, these registers are erased when the program is
terminated. For long term storage of configurations, the disk
storage memory should be used. The Save and Load selections
can be accessed from the File menu.
02169-042
AD8151
Figure 42. Evaluation Board Controller
Rev. B | Page 26 of 40
02169-043
AD8151
Figure 43. Component Side
Rev. B | Page 27 of 40
02169-044
AD8151
Figure 44. Circuit Side
Rev. B | Page 28 of 40
02169-045
AD8151
Figure 45. Silkscreen Top
Rev. B | Page 29 of 40
02169-046
AD8151
Figure 46. Solder Mask Top
Rev. B | Page 30 of 40
02169-047
AD8151
Figure 47. Silkscreen Bottom
Rev. B | Page 31 of 40
02169-048
AD8151
Figure 48. Solder Mask Bottom
Rev. B | Page 32 of 40
02169-049
AD8151
Figure 49. INT1 (VEE)
Rev. B | Page 33 of 40
02169-050
AD8151
Figure 50. INT2 (VCC)
Rev. B | Page 34 of 40
VEE
139
IN13N
IN13P
132
8
131
9
130
10
129
11
128
12
127
13
126
14
125
15
124
16
123
17
122
18
121
19
120
20
119
21
AD8151
118
22
184L LQFP
TOP VIEW
(Not to Scale)
117
23
24
116
115
Figure 51. Bypassing Schematic
Rev. B | Page 35 of 40
C60
0.01μF
VEE
VCC
VEEA0
OUT00P
OUT00N
VEEA1
VEE
92
91
90
89
88
87
86
85
84
83
82
81
OUT09N
OUT09P
VEEA9
OUT08N
OUT08P
VEEA8
OUT07N
OUT07P
VEEA7
OUT06N
OUT06P
VEEA6
OUT05N
OUT05P
VEEA5
OUT04N
OUT04P
VEEA4
OUT03N
OUT03P
VEEA3
OUT02N
OUT02P
VEEA2
OUT01N
OUT01P
VEE
80
93
79
94
46
78
45
77
95
76
96
44
75
97
43
74
98
42
73
99
41
72
40
71
100
70
101
39
69
102
38
68
103
37
67
104
36
66
105
35
65
106
34
64
107
33
63
108
32
62
109
31
61
110
30
60
111
29
59
112
28
58
113
27
57
114
26
56
25
VEE
IN12N
IN12P
VEE
IN11N
IN11P
VEE
IN10N
IN10P
VEE
IN09N
IN09P
VEE
IN08N
IN08P
VEE
IN07N
IN07P
VEE
IN06N
IN06P
VEE
IN05N
IN05P
VEE
IN04N
IN04P
VEE
IN03N
IN03P
VEE
IN02N
IN02P
VEE
IN01N
IN01P
VEE
IN00N
IN00P
VEE
02169-051
140
143
144
145
IN15N
IN15P
146
147
148
149
IN14N
IN14P
VEE
VSS
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
VDD
RESET
CS
RE
WE
UPDATE
A0
A1
A2
A3
A4
D0
D1
D2
D3
D4
D5
D6
169
170
171
172
173
IN16N
IN16P
174
175
176
IN17N
IN17P
177
178
179
141
VEE
VCC
VEE
180
181
IN18N
IN18P
VEE
IN19N
IN19P
182
133
7
OUT12N
OUT12P
VEEA12
OUT11N
OUT11P
VEEA11
OUT10N
OUT10P
VEEA10
OUT16N
OUT16P
C15
0.01μF VEEA16
VEE
134
55
VCC
135
6
54
VCC
VEE
137
53
VEE
C30
0.01μF
138
52
C11
0.01μF
VCC
136
51
C32
0.01μF
IN22P
IN22N
VEE
IN23P
IN23N
VEE
IN24P
IN24N
VEE
IN25P
IN25N
VEE
IN26P
IN26N
VEE
IN27P
IN27N
VEE
IN28P
IN28N
VEE
IN29P
IN29N
VEE
IN30P
IN30N
VEE
IN31P
IN31N
VEE
IN32P
IN32N
VEE
C14
0.01μF
5
50
VCC
C10
0.01μF
4
49
VEE
VDD
VCC
3
48
IN21P
IN21N
C9
0.01μF
PIN 1
INDICATOR
2
47
VEE
1
VEE
VEE
IN20P
IN20N
OUT15N
OUT15P
VEEA15
OUT14N
OUT14P
VEEA14
OUT13N
OUT13P
VEEA13
VCC
VCC
R203
1.5kΩ
VEE
C13
0.01μF
183
184
C29
0.01μF
C31
0.01μF
VCC
C7
0.01μF
C4
0.01μF
VCC
REF
VEEREF
C6
0.01μF
C5
0.01μF
VCC
C8
0.01μF
142
VCC
VEE
VCC
VCC
C12
0.01μF
VEE
VEE
VEE
VCC
VEE
AD8151
AD8151
VCC
R19
1.65kΩ
VCC
IN00P
P4
R20
105Ω
P5
IN00N
R21
1.65kΩ
R40
1.65kΩ
VCC
IN06P
VCC
IN12P
P28
P16
R39
105Ω
P17
IN06N
R38
1.65kΩ
VEE
R58
1.65kΩ
IN18P
R56
1.65kΩ
IN12N
R90
105Ω
P41
VCC
IN24P
IN24N
R92
1.65kΩ
VEE
R116
1.65kΩ
IN30P
OUT08P
R160
49.9Ω
P64
R93
105Ω
P53
IN18N
R91
1.65kΩ
VEE
R94
1.65kΩ
P52
P40
R57
105Ω
P29
VEE
VCC
R89
1.65kΩ
R117
105Ω
P65
R118
1.65kΩ
VEE
OUT08N
R162
49.9Ω
P30
VEE
OUT09P
R165
49.9Ω
R28
1.65kΩ
P8
IN02P
R27
105Ω
P9
R44
1.65kΩ
P20
IN08P
R45
105Ω
R26
1.65kΩ
IN02N
R46
1.65kΩ
VEE
P32
VCC
IN14P
R63
105Ω
P33
P21
IN08N
VCC
R85
1.65kΩ
P44
IN20P
IN14N
R84
105Ω
R175
49.9Ω
IN20N
IN26P
R99
105Ω
P34
OUT11P
R112
1.65kΩ
P68
R170
49.9Ω
IN32P
R111
105Ω
OUT11N
R172
49.9Ω
IN26N
R110
1.65kΩ
P102
VTT
OUT01P
R125
49.9Ω
OUT01N
R127
49.9Ω
OUT02P
R130
49.9Ω
VTT
P99
VTT
OUT02N
P82
R132
49.9Ω
VTT
P98
OUT12P
R185
49.9Ω
OUT03P
R135
49.9Ω
OUT03N
R133
49.9Ω
OUT04P
R140
49.9Ω
VTT
VTT
VEE
IN32N
VEE
OUT12N
R183
49.9Ω
IN15P
R66
105Ω
OUT13P
P35
IN15N
R67
1.65kΩ
P86
VTT
P69
R100
1.65kΩ
VEE
R173
49.9Ω
VCC
R65
1.65kΩ
OUT00N
R122
49.9Ω
VTT
VCC
P57
R83
1.65kΩ
VEE
R98
1.65kΩ
P56
P45
R64
1.65kΩ
VEE
OUT10P
OUT10N
VCC
R62
1.65kΩ
R121
49.9Ω
P83
VEE
VCC
R163
49.9Ω
IN13N
R61
1.65kΩ
VCC
OUT09N
IN13P
R60
105Ω
P31
P103
OUT00P
IN30N
VCC
R59
1.65kΩ
P87
R180
49.9Ω
OUT13N
R182
49.9Ω
OUT14P
R195
49.9Ω
P79
VTT
OUT04N
P78
OUT05P
VTT
R142
49.9Ω
R145
49.9Ω
OUT05N
R143
49.9Ω
OUT06P
R150
49.9Ω
P95
VTT
P94
VTT
VEE
P12
VCC
IN04P
R33
105Ω
P13
R32
1.65kΩ
VEE
IN04N
R50
1.65kΩ
P24
VCC
IN10P
R51
105Ω
P25
R52
1.65kΩ
IN10N
R68
1.65kΩ
P36
IN16P
R69
105Ω
P37
R70
1.65kΩ
VEE
VCC
IN16N
VEE
R79
1.65kΩ
P48
VCC
IN22P
P60
R78
105Ω
P49
R77
1.65kΩ
IN28P
R105
105Ω
P61
IN22N
VEE
R104
1.65kΩ
R106
1.65kΩ
IN28N
IN17P
R192
49.9Ω
OUT16P
R200
49.9Ω
IN17N
VTT
OUT06N
P74
OUT07P
VTT
OUT07N
P
IN01, IN03, IN05, IN07,
IN09, IN11, IN19, IN21,
IN23, IN25, IN27, IN29, IN31
R72
105Ω
R73
1.65kΩ
R190
49.9Ω
OUT15N
VCC
R71
1.65kΩ
P39
OUT15P
R193
49.9Ω
VEE
VCC
P38
OUT14N
P91
P75
OUT16N
VEE
R198
49.9Ω
Rev. B | Page 36 of 40
VTT
R153
49.9Ω
VCC
VTT
C82
0.01μF
VCC
VTT
P70
C83
0.01μF
VTT
Figure 52. Evaluation Board Input/Output Schematic
R155
49.9Ω
P90
C16
0.01μF
P71
VTT
N
R152
49.9Ω
VTT
VCC
02169-052
VCC
R34
1.65kΩ
AD8151
CLK
P2 5
A1
4
74HC14
VSS P2 25
5
1
A1
2
6
3
74HC14
4
5
VSS
6
7
VDD
8
9
10
VSS
20
1
19
2
18
3
17
D2
Q2
16
D3
Q3
A2
15
D4 74HC74 Q4
14
D5
Q5
13
D6
Q6
12
D7
Q7
11
CLK
GND
4
OUT_EN
VCC
D0
Q0
D1
Q1
5
OUT_EN
VCC
D0
Q0
D1
Q1
D2
Q2
D3
Q3
20
19
9
VDD
VDD
VDD
VSS
8
74HC14
A1
11
10
18
17
16
74HC14
A1
12
A3
15
D4 74HC74 Q4
7
14
D5
Q5
8
13
D6
Q6
9
12
Q7
D7
10
CLK 11
GND
6
A1
13
74HC14
A4
9
10
74HC132
A4
12
13
R7
49Ω
VSS
VSS
R1
20kΩ
VSS
VSS
A4
3
2
VSS
74HC132
P2 7
P2 3
P2 8
P2 4
P2 2
WRITE
RESET
READ
D0
A4
A3
A2
A1
A0
D6
D5
D4
D3
D2
D1
UPDATE
CHIP_SELECT
VDD
P3 13
P3 7
P3 11
P3 27
P3 25
P3 23
P3 21
P3 19
P3 17
P3 39
P3 37
P3 35
P3 33
P3 31
P3 29
P3 15
P3 9
P3 5
VSS P3 14
P3 8
P3 12
P3 28
P3 26
P3 24
P3 22
P3 20
P3 18
P3 40
P3 38
P3 36
P3 34
P3 32
P3 30
P3 16
P3 10
P3 6
VSS
4
5
157D2
R17
49Ω
VSS
A4
156D3
R16
49Ω
VSS
1
155D4
R15
49Ω
163A1
164A0
154D5
R14
49Ω
162A2
R11
49Ω
W1
READ
RESET
WRITE
UPDATE
CHIP_SELECT
VSS
R10
49Ω
VSS
153D6
R13
49Ω
161A3
R9
49Ω
VSS
VDD
VSS
158D1
R18
49Ω
6
VSS
11
74HC132
R12
49Ω
160A4
R8
49Ω
8
159D0
74HC132
TP5
TP6
TP4
TP20
TP9
TP10
TP11
TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP7
TP8
VDD
VSS
R2
49kΩ
VSS
VSS
VSS
VSS
VSS
R3
49kΩ
R4
49kΩ
R5
49kΩ
R6
49kΩ
CHIP_SELECT
168
UPDATE
165
WRITE
166
RESET
169
READ
167
VTT P1 6
+
VCC P1 1
P1 2
C1
10μF
VEE P1 3
P1 4
VDD P1 7
VSS
P1 5
P104
P105
Figure 53. Evaluation Board Logic Controls
Rev. B | Page 37 of 40
+
C3
10μF
VTT
VTT
VCC
VCC
VEE
VEE
+
VDD
C2
10μF
VSS
A1, 4 PIN 14 IS TIED TO VDD.
A1, 4 PIN 7 IS TIED TO VSS.
VDD
C86
0.1μF
C87
0.1μF
VSS
VDD
VDD
C88
0.1μF
VSS
VDD
C89
0.1μF
VSS
VSS
02169-053
3
2
74HC14
DATA
DATA
A1
1
CLK P2 6
AD8151
OUTLINE DIMENSIONS
0.75
0.60
0.45
22.20
22.00 SQ
21.80
1.60
MAX
184
1
139
138
PIN 1
20.20
20.00 SQ
19.80
TOP VIEW
(PINS DOWN)
1.45
1.40
1.35
0.15
0.05
SEATING
PLANE
0.20
0.09
7°
3.5°
0°
0.08 MAX
COPLANARITY
93
92
46
47
VIEW A
0.40
BSC
LEAD PITCH
VIEW A
0.23
0.18
0.13
ROTATED 90° CCW
Figure 54. 184-Lead Low Profile Quad Flat Package [LQFP]
(ST-184)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD8151AST
AD8151ASTZ 1
AD8151-EVAL
1
Temperature Range
0°C to 85°C
0°C to 85°C
Package Description
184-Lead LQFP
184-Lead LQFP
Evaluation Board
Z = Pb-free part.
Rev. B | Page 38 of 40
Package Option
ST-184
ST-184
AD8151
NOTES
Rev. B | Page 39 of 40
AD8151
NOTES
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C02169-0-12/05(B)
Rev. B | Page 40 of 40