Active Compensation of Current Unbalance
in Paralleled Silicon Carbide MOSFETs
Yang Xue, Junjie Lu, Zhiqiang Wang, Leon M. Tolbert, Benjamin J. Blalock, Fred Wang
Center for Ultra-wide-area Resilient Electric Energy Transmission Networks (CURENT)
Department of Electrical Engineering and Computer Science
The University of Tennessee
Knoxville, TN 37996-2250, USA
yxue5@utk.edu
Abstract- Current unbalance in paralleled power electronic
devices can affect the performance and reliability of them. In this
paper, the factors causing current unbalance in parallel connected
silicon carbide (SiC) MOSFETs are analyzed, and the threshold
mismatch is identified as the major factor. Then the distribution
and temperature dependence of SiC MOSFETs’ threshold voltage
are studied experimentally. Based on the analysis and study, an
active current balancing (ACB) scheme is presented. The scheme
directly measures the unbalance current, and eliminates it in
closed loop by varying the gate delay to each device. The turn-on
and turn-off current unbalance are sensed and independently
compensated to yield an optimal performance at both switching
transitions. The proposed scheme provides robust compensation
of current unbalance in fast-switching wide-band-gap devices
while keeping circuit complexity and cost low. The performance
of the proposed ACB scheme is verified by both simulation and
experimental results.
I.
INTRODUCTION
Wide-band-gap (WBG) devices, such as SiC MOSFETs
feature superior characteristics such as high voltage rating, fast
switching and high-temperature capability. However, the
current rating of a single WBG device is often limited by its
smaller die size compared to silicon devices, dictating parallel
connection of them in high power applications such as hybrid
electric vehicles or electric utility converters. A major problem
associated with parallelism is that current sharing in these
devices can be affected by mismatches in device parameters or
external circuits. The current unbalance can cause localized
over-temperature and over-current and impact the reliability of
the entire module.
There are two types of current unbalance. Static current
unbalance during on state due to RDSon mismatch is selflimiting in devices that have a positive temperature coefficient.
Dynamic current unbalance is the unbalance during the
switching transients, and therefore can be dominant at high
switching frequency typical of WBG device applications. It is
caused by multiple factors and therefore is hard to mitigate.
This paper will focus on dynamic unbalance.
Previous researchers [1]-[4] have studied the current sharing
performance in paralleled WBG devices, and observed current
unbalance. Different methods have been proposed to improve
the current balancing in parallel devices. Using devices from
the same manufacturing batch and screening them can help to
978-1-4799-2325-0/14/$31.00 ©2014 IEEE
reduce device mismatch according to [5]. However, this
method becomes less effective if the manufacturing spread is
large, and screening increase time and cost overhead.
Current unbalance can be reduced by keeping the layout
symmetrical for all devices [6-8]. The assumption, however, is
that the external circuit mismatch dominates, which might not
be the case in WBG device applications. Also, exact identical
layout is hard to implement if the number of devices is large.
Placing a transformer on the drains can force a balanced
current [9]. The leakage inductance of the transformer causes
voltage spikes, which needs to be suppressed by additional
snubbers. Also, the transformer hurts the system efficiency.
Digital active gate control is proposed for current balancing
in IGBT modules [10]. A DSP/FPGA board samples switching
instances and generates variable delay for the gate signal to
reduce the unbalance. Bonding inductance is proposed as
current sensing method in [11], together with an improved
compensation algorithm. The gate delay is dynamically
controlled using a complex programmable logic device
(CPLD) by switching in an extra gate resistor during the
switching transition in [12]. The digital control schemes in [1012] are easy to implement and effective for current balancing
in IGBTs. However, it would be hard for low-cost digital
controllers to achieve adequate time resolution when applied to
fast switching SiC MOSFETs.
In this paper, an active current balancing (ACB) scheme is
proposed. The variable gate delay circuit achieves continuous
tuning of gate current thus gate delay, and therefore provides
fine time resolution for fast switching WBG devices. The ACB
system employs closed loop control to sense and eliminate
current unbalance at both turn-on and turn-off transitions. It
achieves robust and accurate current balancing, and has low
complexity and cost.
The rest of this paper will be organized as follows. In
Section II, the current balancing during switching transitions is
analyzed by considering the current slope and switching delay.
The factors affecting current balancing are listed and the major
contributor is identified. In Section III, the architecure and
circuit designs of the ACB system are described in detail. The
techniques to decouple on and off transitions in both sensing
and control are discussed. The simulation results of the ACB
system are presented. In Section IV, the VTH distribution and
temperature dependence of SiC MOSFETs are measured. Then
1471
Fig. 1. Block diagram of the proposed ACB.
the performance of the proposed ACB system is verified in a
buck converter as the test platform. Finally, Section V
concludes this paper.
(a)
II. ANALYSIS OF CURRENT UNBALANCE DURING SWITCHING
TRANSITIONS
To understand the causes of current unbalance during
switching transitions, the switching current in the device need
to be derived in terms of device parameters and external
parasitics. During turn-on transition in a typical application
with clamped inductor load, the drain current reaches its
maximum before the voltage across the device starts to
decrease. During this interval, the device is in saturation and its
drain current can be expressed by
diD VCC  VTH  iD g m
,

dt
LS  RG Ciss g m
(1)
(b)
Fig. 2. (a) Schematic of the proposed DCT; (b) the DCT used in experiment
compared to a U.S. penny.
necessitates independent control for on and off transitions in
order to achieve an optimal performance.
III. PROPOSED ACTIVE CURRENT BALANCING SCHEME
where iD is the drain current; VCC is the gate driver high level
output; VTH, gm and Ciss are the device threshold voltage,
transconductance and input capacitance respectively; LS is the
source inductance common to both gate and power loop; and
RG is the gate driver resistance. It can be seen from (1) that
various factors affect the drain current, and unbalance will
occur if mismatch occurs in any of these factors. Moreover,
before the drain current starts to conduct, the turn-on delay is
given by
 VCC

(2)
td ( on )  RG Ciss ln 
.
V

V
TH 
 CC
td(on) mismatch also affects current balancing because the
device that turns on earlier will attempt to take more than its
share of the total current. Among all the parameters above, VTH
mismatch is found to be a major factor causing the current
unbalance according to both simulation and experiments. The
reasons are that VTH is in both (1) and (2), and it shows large
process variation and negative temperature coefficient (NTC),
making current balancing harder to achieve, as will be shown
in Section IV.
The equations can be derived for turn-off transition in a
similar way. Normally the unbalance level at turn-off transition
is different from that at turn-on due to different gate drive
strength and current/voltage waveforms at drain. This
As discussed above, current unbalance can be caused by
multiple factors, and is hard to predict before the actual circuit
is fabricated. In addition, the level of unbalance changes with
the operation condition, making static calibration impractical.
To solve this problem, an active current balancing (ACB)
scheme is proposed. The system architecture includes three
basic building blocks as shown in Fig. 1: 1) the current
unbalance sensing block senses the unbalanced current in the
devices; 2) the current balancing controller extracts the
unbalance at on and off transitions and generates the
corrections needed; and 3) then the active gate control varies
the gate drive signals for both transitions independently
according to the instructions from the balancing controller. The
three blocks form a negative feedback loop, which can
automatically adjust the gate drive signals to eliminate current
unbalance regardless the cause of it.
A. Current Unbalance Sensing
A differential current transformer (DCT) is proposed to
provide accurate, high-bandwidth and low-cost measurement
of current unbalance. The schematic is shown in Fig. 2(a). A
major difference and improvement compared to the normal CT
is that it has two 1-turn primary windings in opposite
directions. Therefore, it only responds to the differential
current and its output is given by Vout  RT   I/ n , whose
polarity indicates the polarity of unbalance. The proposed DCT
1472
(a)
(a)
(b)
(b)
Fig. 4. The gate voltages with different VCTL, (a) turn-on transition; (b) turn-off
transition.
(c)
Fig. 3. (a) Block diagram of the VGD circuit; (b) the VGD-ON circuit
schematic; (c) the VGD-OFF circuit schematic.
has negligible impact on the system efficiency and components
stresses because the primary windings have negligible
resistance and leakage inductance. Moreover, since only the
differential current is sensed, the proposed DCT can have a
small sized core. Also, core saturation does not affect the
accuracy of the system, since the polarity of current difference
is preserved.
B. Active Gate Control for On and Off Transitions
Dynamic current unbalance can be eliminated by proper
control of the gate signal delay. For example, by slightly
delaying the rising edge of gate signal for a device with lower
VTH, the unbalance at turn-on can be reduced. Based on this
concept, a variable gate delay (VGD) circuit is proposed as the
core of the active gate control block. The block diagram and
circuit implementations are shown in Fig. 3. Apart from the
normal gate network, the VGD circuits constitute additional
current branches whose currents are controlled by VCTL. In
order to achieve independent gate delay control for on and off
transitions, the VGD is separated into two parts, VGD-ON and
VGD-OFF, each controlled by their own VCTL. During turn-on
transition, diodes D2, D3 ensure that the VGD-ON is enabled
and VDG-OFF is disabled. Before the transition, the gate
driver output is low, and C1 is charged through R2 to VCTL-ON.
When the gate driver output goes high, D4 blocks and C1
keeps the VGS of MN1 constant (the time constant R3·C1 is
large compared to the transition time). During turn-on
transient, MN1 is in saturation and its drain current is
controlled by its VGS. Therefore, VCTL-ON controls the charging
current of the power switch gate thus its turn-on delay. The
operation at turn-off transition is similar. VGD-OFF is enabled
and C2 is charged to VCC - VCTL-OFF when the gate driver output
is high. During turn-off, VCTL-OFF determines the drain current
of MP1. As a result, VCTL-OFF controls the gate discharging
current, and thus the turn-off delay of the power switch. Fig. 4
shows the simulation results of gate voltage with different
VCTL. It can be seen that the delays at turn-on and turn-off are
independently and continuously adjustable by VCTL. With the
proposed VGD circuit, the maximum gate delay is obtained
when MN1/MP1 are off, and the gate current is determined by
the normal gate network. The minimum gate delay is achieved
when MN1 or MP1 are fully on, and the gate current is limited
only by their RDSon. Therefore, the control range can be
adjusted by changing the ratio of R2/RDSon, MN1 or R1/RDSon, MP1.
The proposed VGD circuit achieves the tuning of the gate
1473
Fig. 6. Simplified schematic of the proposed ACB system.
Fig. 5. The schematic of the proposed current balancing controller.
delay at both switching transitions with fine time resolution
and low circuit complexity and cost. More importantly, the
delay is individually adjustable while the gate driver IC is
shared among all the parallel power switches, which greatly
reduces the system cost.
C. Current Balancing Controller
The current balancing controller (CBC) receives the current
difference signal from the DCT, extracts the current
unbalances at turn-on and turn-off transitions, and generates
the VCTL-ON and VCTL-OFF for the VGD to eliminate the
unbalance. It is implemented based on two active integrators
R5/C3/OA1 and R6/C4/OA2 as shown in Fig. 5. R7, R8 set the
DC gain of the integrators. MN2 and MP2 are added to enable
integration only at correct switching transitions; the gate of
MN2 is connected to the differentiator C5/R9, and its VGS is
low for only a short time after the falling edge of the PWM
signal. During the rest of switching cycle, the VGS of MN2 is
high and the integrator input is shorted to ground so that the
DCT output is ignored. Thus, OA1 only sees the turn-off
transition. In the same way, MP2 bypasses the input of OA2
except for the turn-on transition. This configuration enables the
extraction of the current unbalance at switching transitions,
effectively decouples the turn-on unbalance from turn-off, and
removes the error due to the transformer reset voltage. As a
result, the two integrators independently generate VCTL-ON and
VCTL-OFF. In conjunction with DCT and VGD, the CBC closes
the negative feedback loop and adjusts the gate signal delay so
that the DCT output at transitions are zero, thus the current
unbalance is eliminated for both on and off transitions.
D. Active Current Balancing System and Simulation Results
The proposed ACB system is realized with the three blocks
Fig. 7. Drain currents of the parallel SiC MOSFETs, (a) before ACB
adjustment; (b) after ACB adjustment.
described above and simulated in a boost converter with two
parallel SiC MOSFETs, model CMF20120D. The simplified
schematic is shown in Fig. 6. MOSFET Ma’s VTH is decreased
by 1.5 V to simulate current unbalance due to component
mismatch. The variable gate delays are applied to Ma while
reference voltages are applied to Mb’s VGD so that the relative
delays can be both positive and negative. Fig. 7 shows the
simulation results. The brown and red traces are the VCTL-ON
and VCTL-OFF to the VGD circuit, while the blue and green
traces are the drain currents of the power switches. The drain
currents at switching transitions before the ACB adjustment are
shown in detail in Fig. 7(a). The current unbalance can be
clearly seen. As the CBC integrates the DCT output, the two
VCTL’s start to fall and the turn-on delay of Ma is increased,
while the turn-off delay is decreased to compensate for its
lower threshold. After about 200 µs, both VCTL’s reach steady
state and the drain currents at this time are shown in Fig. 7(b).
The current unbalance is greatly reduced at both turn-on and
turn-off transitions. Since the ACB scheme directly measures
the unbalance current and eliminates it by negative feedback, it
is able to remove any current unbalance, regardless of the
cause of it.
1474
SiC MOSFET 1
SiC MOSFET 2
25
100
4
VTH (V)
3.5
3
2.5
2
1.5
0
50
75
Tj (°C)
125
150
Fig. 8. VTH vs. junction temperature curve.
Fig. 10. The schematic of the ACB system test platform.
400
8
(V)
12
DS
200
V
Drain Current (A)
600
Drain Current 1
Drain Current 2
Drain Voltage
4
0
0
8.8
9
Time (sec)
-200
9.2
-6
x 10
(a)
(a)
200
(V)
400
DS
8
Eon1 = 55.60 J
Eon2 = 73.15 J
600
V
Drain Current (A)
12
Drain Current 1
Drain Current 2
Drain Voltage
4
0
0
8.7
8.8
8.9
9
9.1
Time (sec)
9.2
-200
9.3
-6
x 10
(b)
Fig. 11. The picture of the ACB system test platform. (a) top view, (b)
bottom view.
(b)
Fig. 9. Turn-on waveforms and energies of two parallel DUTs with
matched VTH, (a) Tj1 = Tj2 = 25 °C, (b) Tj1 = 25 °C, Tj2 = 135 °C.
IV. EXPERIMENTAL RESULTS
A. Statistical Distribution and Temperature Dependence of SiC
MOSFET’s VTH
As discussed in Section II, the mismatch of VTH is a major
factor causing current unbalance. Therefore, 28 SiC MOSFETs
(Cree CMF20120D) were measured for their VTH distribution.
The mean value is 3.22 V with a standard deviation of 0.3 V,
and the maximum and minimum are 3.84 V and 2.84 V,
respectively. The datasheet specifications listed suggest an
even larger variation in the worst-case scenario.
It is known that the threshold voltage of MOSFETs is
sensitive to temperature. The VTH temperature dependence of
two SiC MOSFETs samples (CMF20120D) was measured in
experiment and the results are plotted in Fig. 8. The
temperature coefficient of both devices is −9 mV/°C.
1475
Drain Current 1 200
Drain Current 2
Drain Voltage
0
0
0
100
200
300
Time (sec)
400
0
103.5
Time (sec)
3000
Eon1 = 42.18 J
Eon2 = 70 J
1500
0
103.3
103.5
Time (sec)
5
0
106.8
103.7
400
3000
200
VDS (V)
200
ID (A)
5
0
103.3
Power Loss (W)
5
VDS (V)
ID (A)
400
Power Loss (W)
10
10
400
VDS (V)
ID (A)
10
0
107
Time (sec)
107.2
Eoff1 = 25.89 J
Eoff2 = 53.68 J
1500
0
106.8
103.7
107
Time (sec)
107.2
Fig. 12. (a) The currents and voltage waveforms without ACB enabled; (b) turn-on waveforms and power loss; (c) turn-off waveforms and power
loss.
Drain Current 1 200
Drain Current 2
Drain Voltage
0
0
0
100
200
Time (sec)
300
400
0
103.5
Time (sec)
3000
Eon1 = 55.55 J
Eon2 = 54.05 J
1500
0
103.3
103.5
Time (sec)
103.7
5
0
106.8
103.7
400
3000
200
VDS (V)
200
ID (A)
5
0
103.3
Power Loss (W)
5
VDS (V)
ID (A)
400
Power Loss (W)
10
10
400
VDS (V)
ID (A)
10
0
107
Time (sec)
107.2
Eoff1 = 32.26 J
Eoff2 = 38.27 J
1500
0
106.8
107
Time (sec)
107.2
Fig. 13. (a) The currents and voltage waveforms with ACB enabled; (b) turn-on waveforms and power loss; (c) turn-off waveforms and power loss.
To evaluate the effect of this temperature dependence on
current balance, a double pulse tester setup for two parallel
devices was built. The board layout is optimized for symmetry
to exclude the effect of layout on current balance, and the drain
currents of the two devices are measured independently with
Pearson current probes. The DC bus is 500 V and the load
current is 13.2 A. The gate resistors are 10 Ω for turn-on and
4.7 Ω for turn-off.
A power resistor is attached to one of the DUTs as the
heating element, and thermocouples are used to monitor the
DUTs’ temperatures. First, two DUTs with similar VTH are
tested at room temperature, and the turn-on I/V waveforms and
energies are shown in Fig. 9(a). Then, DUT2 is heated to
135 °C by applying a DC current to the power resistor, while
DUT1 stays at room temperature. The turn-on waveforms are
plotted in Fig. 9(b). Comparing (a) and (b), the higher junction
temperature of DUT2 reduces its VTH, and thus induces current
unbalance. In real applications, a lower VTH leads to a larger
share of current during switching, and therefore larger power
loss. This temperature induced unbalance is hard to predict and
calibrate before the devices are put into operation, again
validating the value of the proposed active current balancing
scheme.
B. Active Current Balancing Test Results
To evaluate the performance of the proposed ACB system, a
buck converter with paralleled SiC MOSFETs is built as the
test platform. The schematic is shown in Fig. 10. The inverting
buck topology is chosen to reduce the power supply output
current requirement, and it also eases the gate signal
measurement by having ground-referenced power switches.
The picture of the test platform is shown in Fig. 11. Two SiC
MOSFETs (CMF20120D) are used as the power switches and
the free-wheeling diode is a SiC Schottky diode C4D40120D.
The power switches and the diode are mounted on the bottom
side of the board with heatsinks. The input DC voltage is
400 V, the output is 60 V, 12 A, and the operation frequency is
40 kHz. The drain currents are measured by current probes
with a bandwidth of 120 MHz.
In the experiment, two SiC MOSFETs with a threshold
mismatch of 1.0 V are used to generate current unbalance.
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Fig. 12 shows the measured steady-state drain currents/voltage
and switching power loss waveforms without the proposed
ACB scheme enabled. Large dynamic unbalance in the drain
currents during turn-on and turn-off transitions can be seen.
The unbalance causes the device 2 to have 66% more turn-on
loss and 107% more turn-off loss than device 1, which can
potentially lead to over temperature or over current in device 2.
Then the ACB system is enabled and the waveforms at the
same steady-state condition are measured and plotted in
Fig. 13. The current unbalance due to threshold mismatch is
significantly reduced for both turn-on and turn-off transitions,
verifying the performance of the proposed ACB system. The
resulting switching energy loss unbalance at both transitions is
greatly reduced to 3% and 19%, respectively, as indicated in
Fig. 13. The total switching energy loss unbalance is only 5%.
This leads to a more evenly distributed power loss, improving
the reliability of the system and making the thermal
management easier.
the Engineering Research Center Program of the National
Science Foundation and DOE under NSF Award Number
EEC-1041877 and the CURENT Industry Partnership
Program.
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V. CONCLUSIONS
Current unbalance in paralleled SiC MOSFETs is analyzed.
As a major factor affecting the dynamic unbalance, the
threshold voltage distribution and temperature dependence are
studied in experiment. An active current balancing scheme is
presented. It is capable of sensing the unbalance current and
adjusting the gate delay in a closed loop manner to compensate
the current unbalance at both turn-on and turn-off transitions,
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and it demonstrates a reduction of switching energy reduction
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ACKNOWLEDGEMENT
This work was partially funded by the II-VI Foundation and
Oak Ridge National Laboratory under the U.S. Department of
Energy’s Vehicle Technologies Program. This work made use
of Engineering Research Center Shared Facilities supported by
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