FEATURES
FUNCTIONAL BLOCK DIAGRAM
SPI interface
Supports daisy-chain mode
9.5 Ω on resistance at 25°C and ±15 V dual supply
1.6 Ω on-resistance flatness at 25°C and ±15 V dual supply
Fully specified at ±15 V, +12 V, ±5 V
3 V logic-compatible inputs
Rail-to-rail operation
24-lead TSSOP and 24-lead, 4 mm × 4 mm LFCSP
ADG1414
APPLICATIONS
S1
D1
S2
D2
S3
D3
S4
D4
S5
D5
S6
D6
S7
D7
S8
D8
INPUT SHIFT
REGISTER
Automatic test equipment
Data acquisition systems
Battery-powered systems
Sample-and-hold systems
Audio signal routing
Video signal routing
Communication systems
SCLK DIN SYNC
SDO
RESET/VL
08497-001
Data Sheet
9.5 Ω RON, ±15 V/+12 V/±5 V iCMOS,
Serially-Controlled Octal SPST Switches
ADG1414
Figure 1.
GENERAL DESCRIPTION
The ADG1414 is a monolithic complementary metal-oxide
semiconductor (CMOS) device containing eight independently
selectable switches designed on an industrial CMOS (iCMOS®)
process. iCMOS is a modular manufacturing process combining
high voltage CMOS and bipolar technologies. iCMOS components
can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduce the
package size.
The ADG1414 is a set of octal, single-pole, single-throw (SPST)
switches controlled via a 3-wire serial interface. On resistance is
matched closely between switches and is very flat over the full
signal range. Each switch conducts equally well in both directions
and the input signal range extends to the supplies.
The ADG1414 uses a versatile 3-wire serial interface that
operates at clock rates of up to 50 MHz and is compatible with
standard SPI, QSPI™, MICROWIRE™, and DSP interface
standards. The output of the shift register, SDO, enables a
number of these devices to be daisy chained.
At power-up, all switches are in the off condition, and the
internal registers contain all zeros.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
50 MHz serial interface.
9.5 Ω on resistance.
1.6 Ω on-resistance flatness.
24-lead TSSOP and 4 mm × 4 mm LFCSP packages.
Data is written to these devices in the form of eight bits; each
bit corresponds to one channel.
Rev. B
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ADG1414
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
ESD Caution...................................................................................9
Applications ....................................................................................... 1
Pin Configurations and Function Descriptions ......................... 10
Functional Block Diagram .............................................................. 1
Typical Performance Characteristics ........................................... 12
Product Highlights ........................................................................... 1
Test Circuits..................................................................................... 15
Revision History ............................................................................... 2
Terminology .................................................................................... 17
Specifications..................................................................................... 3
Theory of Operation ...................................................................... 18
±15 V Dual Supply ....................................................................... 3
Serial Interface ............................................................................ 18
12 V Single Supply ........................................................................ 4
Input Shift Register .................................................................... 18
±5 V Dual Supply ......................................................................... 6
Power-On Reset .......................................................................... 18
Continuous Current per Channel .............................................. 7
Daisy Chaining ........................................................................... 18
Timing Characteristics ................................................................ 8
Outline Dimensions ....................................................................... 19
Absolute Maximum Ratings ............................................................ 9
Ordering Guide .......................................................................... 19
Thermal Resistance ...................................................................... 9
REVISION HISTORY
11/15—Rev. A to Rev. B
Changes to VDD/VSS Parameter, Table 2 ......................................... 5
Updated Outline Dimensions ....................................................... 19
1/13—Rev. 0 to Rev. A
Changes to RESET/VL Pin Description Column, Table 9 ......... 11
Changes to Power-On Reset Section ............................................ 19
Updated Outline Dimensions ....................................................... 20
10/09—Revision 0: Initial Version
Rev. B | Page 2 of 19
Data Sheet
ADG1414
SPECIFICATIONS
±15 V DUAL SUPPLY
VDD = 15 V ± 10%, VSS = −15 V ± 10%, VL = 2.7 V to 5.5 V, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
+25°C
−40°C to
+85°C
VSS to VDD
9.5
11.5
0.55
14
On-Resistance Match Between Channels (ΔRON)
1
1.6
1.5
On-Resistance Flatness (RFLAT (ON))
1.9
2.15
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
±0.05
±0.15
±0.05
±1
Drain Off Leakage, ID (Off )
±0.15
±0.1
±0.3
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage (VINH)
Input Low Voltage (VINL)
Input Current
−40°C to
+125°C
16
1.7
2.3
High Impedance Leakage Current
Ω max
Ω typ
VDD = +13.5 V, VSS = −13.5 V, VS = ±10 V,
IS = −10 mA
VDD = +13.5 V, VSS = −13.5 V, VS = ±10 V,
IS = −10 mA
Ω max
VDD = +16.5 V, VSS = −16.5 V
±2
nA max
nA typ
VS = ±10 V, VD = ∓10 V; see Figure 24
±1
±2
VS = VD = ±10 V; see Figure 25
±2
±4
nA max
nA typ
nA max
V min
V max
µA typ
µA max
pF typ
VIN = VGND or VL
2.0
0.8
±0.001
4
0.4
0.6
0.001
4
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion (THD + N)
75
93
25
35
10
−73
−75
0.05
−3 dB Bandwidth
Insertion Loss
CD, CS (Off )
CD, CS (On)
256
0.55
8
32
tOFF
Ω max
Ω typ
VDD = +13.5 V, VSS = −13.5 V, VS = ±10 V,
IS = −10 mA; see Figure 23
VS = ±10 V, VD = ∓10 V; see Figure 24
±1
High Impedance Output Capacitance1
DYNAMIC CHARACTERISTICS1
tON
V
Ω typ
Test Conditions/Comments
nA typ
±0.1
Digital Input Capacitance (CIN)
LOGIC OUTPUTS (SDO)
Output Low Voltage (VOL) 1
Unit
110
120
35
35
V max
V max
µA typ
µA max
pF typ
ISINK = 3 mA
ISINK = 6 mA
ns typ
ns max
ns typ
ns max
pC typ
dB typ
dB typ
% typ
RL = 100 Ω, CL = 35 pF
VS = 10 V; see Figure 30
RL = 100 Ω, CL = 35 pF
VS = 10 V; see Figure 30
VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 31
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 26
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 27
RL = 110 Ω, 15 V p-p, f = 20 Hz to 20 kHz;
see Figure 29
RL = 50 Ω, CL = 5 pF; see Figure 28
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28
f = 1 MHz
f = 1 MHz
MHz typ
dB typ
pF typ
pF typ
Rev. B | Page 3 of 19
ADG1414
Parameter
POWER REQUIREMENTS
IDD
Data Sheet
+25°C
−40°C to
+85°C
−40°C to
+125°C
0.001
1
IL Inactive
0.3
IL Active at 30 MHz
0.26
1
IL Active at 50 MHz
ISS
0.3
0.35
0.5
0.55
0.42
0.001
1
±4.5/±16.5
VDD/VSS
1
Unit
µA typ
µA max
µA typ
µA max
mA typ
mA max
mA typ
mA max
µA typ
µA max
V min/max
Test Conditions/Comments
VDD = +16.5 V, VSS = −16.5 V
Digital inputs = 0 V or VL
Digital inputs = 0 V or VL
Digital inputs toggle between 0 V and VL
Digital inputs toggle between 0 V and VL
Digital inputs = 0 V or VL
Guaranteed by design, not subject to production test.
12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, VL = 2.7 V to 5.5 V, GND = 0 V, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
+25°C
−40°C to
+85°C
0 to VDD
18
21.5
0.55
26
On-Resistance Match Between Channels (ΔRON)
1.2
5
1.6
On-Resistance Flatness (RFLAT (ON))
6
6.9
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
Drain Off Leakage, ID (Off )
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage (VINH)
Input Low Voltage (VINL)
Input Current
−40°C to
+125°C
±0.02
±0.15
±0.02
±0.15
±0.05
±0.3
28.5
1.8
7.3
±1
±2
±1
±2
±2
±4
2.0
0.8
±0.001
±0.1
Digital Input Capacitance (CIN)
LOGIC OUTPUTS (SDO)
Output Low Voltage (VOL) 1
High Impedance Leakage Current
High Impedance Output Capacitance1
4
0.4
0.6
±1
4
Rev. B | Page 4 of 19
Unit
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Test Conditions/Comments
VDD = 10.8 V, VSS = 0 V; VS = 0 V to 10 V,
IS = −10 mA; see Figure 23
VDD = 10.8 V, VSS = 0 V; VS = 0 V to 10 V,
IS = −10 mA
VDD = 10.8 V, VSS = 0 V; VS = 0 V to 10 V,
IS = −10 mA
Ω max
nA typ
nA max
nA typ
nA max
nA typ
nA max
V min
V max
µA typ
µA max
pF typ
V max
V max
µA max
pF typ
VDD = 10.8 V
VS = 1 V/10 V, VD = 10 V/1 V; see Figure 24
VS = 1 V/10 V, VD = 10 V/1 V; see Figure 24
VS = VD = 1 V or 10 V; see Figure 25
VIN = VGND or VL
ISINK = 3 mA
ISINK = 6 mA
Data Sheet
Parameter
DYNAMIC CHARACTERISTICS1
tON
ADG1414
+25°C
−40°C to
+85°C
−40°C to
+125°C
220
240
46
46
Test Conditions/Comments
ns typ
ns max
ns typ
ns max
pC typ
dB typ
RL = 100 Ω, CL = 35 pF
VS = 8 V; see Figure 30
RL = 100 Ω, CL = 35 pF
VS = 8 V; see Figure 30
VS = 6 V, RS = 0 Ω, CL = 1 nF; see Figure 31
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 26
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 27
RL = 50 Ω, CL = 5 pF; see Figure 28
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
see Figure 28
f = 1 MHz
f = 1 MHz
VDD = +13.2 V
Digital inputs = 0 V or VL
Charge Injection
Off Isolation
145
185
35
45
8
−70
Channel-to-Channel Crosstalk
−75
dB typ
−3 dB Bandwidth
Insertion Loss
240
1.15
MHz typ
dB typ
12
33
pF typ
pF typ
tOFF
CD, CS (Off )
CD, CS (On)
POWER REQUIREMENTS
IDD
0.001
1
IL Inactive
0.3
1
IL Active at 30 MHz
IL Active at 50 MHz
ISS
VDD/VSS
1
Unit
0.26
0.3
0.35
0.5
0.55
0.42
0.001
1
5/16.5
Guaranteed by design, not subject to production test.
Rev. B | Page 5 of 19
µA typ
µA max
µA typ
µA max
mA typ
mA max
mA typ
mA max
µA typ
µA max
V min/max
Digital inputs = 0 V or VL
Digital inputs toggle between 0 V and VL
Digital inputs toggle between 0 V and VL
Digital inputs = 0 V or VL
ADG1414
Data Sheet
±5 V DUAL SUPPLY
VDD = +5 V ± 10%, VSS = −5 V ± 10%, VL = 2.7 V to VDD, GND = 0 V, unless otherwise noted.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance (RON)
On-Resistance Match Between Channels (ΔRON)
On-Resistance Flatness (RFLAT (ON))
+25°C
−40°C to
+85°C
VSS to VDD
21
25
0.6
29
1.3
5.2
6.4
1.7
1.9
7.3
7.6
LEAKAGE CURRENTS
Source Off Leakage, IS (Off )
±0.02
±1
Drain Off Leakage, ID (Off )
±0.15
±0.02
±0.15
±0.05
±0.3
Channel On Leakage, ID, IS (On)
DIGITAL INPUTS
Input High Voltage (VINH)
Input Low Voltage (VINL)
Input Current
−40°C to
+125°C
32
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
Test Conditions/Comments
VDD = +4.5 V, VSS = −4.5 V, VS = ±4.5 V,
IS = −10 mA; see Figure 23
VDD = +4.5 V, VSS = −4.5 V, VS = ±4.5V,
IS = −10 mA
VDD = +4.5 V, VSS = −4.5 V, VS = ±4.5 V;
IS = −10 mA
VDD = +5.5 V, VSS = −5.5 V
nA typ
VS = ±4.5 V, VD = ∓4.5 V; see Figure 24
±2
nA max
nA typ
VS = ±4.5 V, VD = ∓4.5 V; see Figure 24
±1
±2
VS = VD = ±4.5 V; see Figure 25
±2
±4
nA max
nA typ
nA max
V min
V max
µA typ
µA max
pF typ
VIN = VGND or VL
2.0
0.8
±0.001
±0.1
Digital Input Capacitance (CIN)
LOGIC OUTPUTS (SDO)
Output Low Voltage (VOL) 1
Unit
4
ISINK = 3 mA
ISINK = 6 mA
4
V max
V max
µA max
pF typ
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion (THD + N)
190
250
45
60
7
–70
–75
0.14
ns typ
ns max
ns typ
ns max
pC typ
dB typ
dB typ
% typ
−3 dB Bandwidth
Insertion Loss
CD, CS (Off )
CD, CS (On)
256
1
11
35
RL = 100 Ω, CL = 35 pF
VS = 3 V; see Figure 30
RL = 100 Ω, CL = 35 pF
VS = 3 V; see Figure 30
VS = 0 V, RS = 0 Ω, CL = 1 nF; see Figure 31
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 26
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 27
RL = 110 Ω, 5 V p-p, f = 20 Hz to 20 kHz;
see Figure 29
RL = 50 Ω, CL = 5 pF; see Figure 28
RL = 50 Ω, CL = 5 pF, f = 1 MHz; see Figure 28
f = 1 MHz
f = 1 MHz
High Impedance Leakage Current
High Impedance Output Capacitance1
DYNAMIC CHARACTERISTICS1
tON
tOFF
0.4
0.6
±1
290
320
65
70
MHz typ
dB typ
pF typ
pF typ
Rev. B | Page 6 of 19
Data Sheet
ADG1414
Parameter
POWER REQUIREMENTS
IDD
+25°C
−40°C to
+85°C
−40°C to
+125°C
0.001
1
IL Inactive
0.3
IL Active at 30 MHz
0.26
1
IL Active at 50 MHz
0.3
0.35
0.5
0.55
0.42
ISS
0.001
1
±4.5/±16.5
VDD/VSS
1
Unit
µA typ
µA max
µA typ
µA max
mA typ
mA max
mA typ
mA max
µA typ
µA max
V min/max
Test Conditions/Comments
VDD = +5.5 V, VSS = −5.5 V
Digital inputs = 0 V or VL
Digital inputs = 0 V or VL
Digital inputs toggle between 0 V and VL
Digital inputs toggle between 0 V and VL
Digital inputs = 0 V or VL
Guaranteed by design, not subject to production test.
CONTINUOUS CURRENT PER CHANNEL
Guaranteed by design, not subject to production test.
Table 4. Eight Channels On
Parameter
CONTINUOUS CURRENT PER CHANNEL
±15 V Dual Supply
24-Lead TSSOP (θJA = 112.6°C/W)
24-Lead LFCSP (θJA = 30.4°C/W)
12 V Single Supply
24-Lead TSSOP (θJA = 112.6°C/W)
24-Lead LFCSP (θJA = 30.4°C/W)
±5 V Dual Supply
24-Lead TSSOP (θJA = 112.6°C/W)
24-Lead LFCSP (θJA = 30.4°C/W)
25°C
85°C
125°C
Unit
67
121
46
75
31
42
mA max
mA max
64
115
44
72
30
41
mA max
mA max
48
86
35
57
22
36
mA max
mA max
Test Conditions/Comments
VDD = +13.5 V, VSS = −13.5 V
VDD = 10.8 V, VSS = 0 V
VDD = +4.5 V, VSS = −4.5 V
Guaranteed by design and characterization, not production tested.
Table 5. One Channel On
Parameter
CONTINUOUS CURRENT PER CHANNEL
±15 V Dual Supply
24-Lead TSSOP (θJA = 112.6°C/W)
24-Lead LFCSP (θJA = 30.4°C/W)
12 V Single Supply
24-Lead TSSOP (θJA = 112.6°C/W)
24-Lead LFCSP (θJA = 30.4°C/W)
±5 V Dual Supply
24-Lead TSSOP (θJA = 112.6°C/W)
24-Lead LFCSP (θJA = 30.4°C/W)
25°C
85°C
125°C
Unit
169
295
97
139
48
55
mA max
mA max
161
281
93
135
47
54
mA max
mA max
122
214
76
114
43
51
mA max
mA max
Test Conditions/Comments
VDD = +13.5 V, VSS = −13.5 V
VDD = 10.8 V, VSS = 0 V
VDD = +4.5 V, VSS = −4.5 V
Rev. B | Page 7 of 19
ADG1414
Data Sheet
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2 (see Figure 2).
VDD = 4.5 V to 16.5 V; VSS = −16.5 V to 0 V; VL = 2.7 V to 5.5 V or VDD (whichever is less); GND = 0 V; all specifications TMIN to TMAX,
unless otherwise noted. Guaranteed by design and characterization, not production tested.
Table 6.
Parameter
t11
t2
t3
t4
t5
t6
t7
t8
t9
t10
t112
t12
1
2
Limit at TMIN, TMAX
20
9
9
5
5
5
5
15
5
5
40
15
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK active edge setup time
Data setup time
Data hold time
SCLK active edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to next SCLK active edge ignored
SCLK active edge to SYNC falling edge ignored
SCLK rising edge to SDO valid
Minimum RESET pulse width
Maximum SCLK frequency is 50 MHz at VDD = 4.5 V to 16.5 V; VSS = −16.5 V to 0 V, VL = 2.7 V to 5.5 V or VDD (whichever is less); GND = 0 V.
Measured with the 1 kΩ pull-up resistor to VL and 20 pF load. t11 determines the maximum SCLK frequency in daisy-chain mode.
Timing Diagrams
t10
t1
t9
SCLK
t8
t2
t3
t4
t7
SYNC
t5
DIN
t6
DB0
DB7
08497-002
RESET
t12
Figure 2. Serial Write Operation
t1
SCLK
8
t8
t3
t4
16
t9
t2
t7
SYNC
t5
DIN
t6
DB7
DB0
DB0
DB7
INPUT WORD FOR DEVICE N + 1
INPUT WORD FOR DEVICE N
t11
DB0
DB31
UNDEFINED
INPUT WORD FOR DEVICE N
Figure 3. Daisy-Chain Timing Diagram
Rev. B | Page 8 of 19
08497-003
SDO
Data Sheet
ADG1414
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 7.
Parameter
VDD to VSS
VDD to GND
VSS to GND
VL to GND
Analog Inputs1
Digital Inputs1
Continuous Current, Sx or Dx Pins
Peak Current, Sx or Dx (Pulsed at
1 ms, 10% Duty Cycle Maximum)
TSSOP Package
LFCSP Package
Operating Temperature Range
Industrial (B Version)
Storage Temperature Range
Junction Temperature
Reflow Soldering Peak
Temperature, Pb free
Time at Peak Temperature
1
Rating
35 V
−0.3 V to +25 V
+0.3 V to −25 V
−0.3 V to +7 V
VSS − 0.3 V to VDD + 0.3 V or
30 mA, whichever occurs first
GND − 0.3 V to VL + 0.3 V or
30 mA, whichever occurs first
Table 4 specifications + 15%
300 mA
400 mA
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Only one absolute maximum rating may be applied at any one
time.
THERMAL RESISTANCE
Table 8. Thermal Resistance
Package Type
24-Lead TSSOP1
24-Lead LFCSP2
1
2
–40°C to +125°C
−65°C to +150°C
150°C
260°C
θJA
112.6
30.4
4-layer board.
4-layer board and exposed paddle soldered to VSS.
ESD CAUTION
10 sec to 40 sec
Overvoltages at the analog and digital inputs are clamped by internal
diodes. Limit the current to the maximum ratings given.
Rev. B | Page 9 of 19
θJC
50
Unit
°C/W
°C/W
ADG1414
Data Sheet
D1 6
21 VSS
ADG1414
21 SYNC
18 VSS
GND 1
20 S8
S1 2
17 S8
19 D8
D1 3
ADG1414
16 D8
18 S7
S2 4
15 S7
D2 8
17 D7
D2 5
TOP VIEW
(Not to Scale)
S3 9
16 S6
D3 10
15 D6
S4 11
14 S5
D4 12
13 D5
14 D7
S3 6
D6 12
S5 11
D5 10
D4 9
S4 8
13 S6
D3 7
TOP VIEW
(Not to Scale)
08497-004
S2 7
NOTES
1. EXPOSED PAD TIED TO SUBSTRATE, VSS.
Figure 4. TSSOP Pin Configuration
08497-005
S1 5
22 SCLK
22 SDO
GND 4
23 VDD
23 RESET/VL
DIN 3
24 DIN
24 SYNC
VDD 2
19 SDO
SCLK 1
20 RESET/VL
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 5. LFCSP Pin Configuration
Table 9. Pin Function Descriptions
TSSOP
1
Pin No.
LFCSP
22
Mnemonic
SCLK
2
3
23
24
VDD
DIN
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
GND
S1
D1
S2
D2
S3
D3
S4
D4
D5
S5
D6
S6
D7
S7
D8
S8
VSS
22
19
SDO
23
20
RESET/VL
Description
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial
clock input. Data can be transferred at rates of up to 50 MHz.
Most Positive Power Supply Potential.
Serial Data Input. This device has an 8-bit shift register. Data is clocked into the register on the
falling edge of the serial clock input.
Ground (0 V) Reference.
Source Terminal 1. This pin can be an input or an output.
Drain Terminal 1. This pin can be an input or an output.
Source Terminal 2. This pin can be an input or an output.
Drain Terminal 2. This pin can be an input or an output.
Source Terminal 3. This pin can be an input or an output.
Drain Terminal 3. This pin can be an input or an output.
Source Terminal 4. This pin can be an input or an output.
Drain Terminal 4. This pin can be an input or an output.
Drain Terminal 5. This pin can be an input or an output.
Source Terminal 5. This pin can be an input or an output.
Drain Terminal 6. This pin can be an input or an output.
Source Terminal 6. This pin can be an input or an output.
Drain Terminal 7. This pin can be an input or an output.
Source Terminal 7. This pin can be an input or an output.
Drain Terminal 8. This pin can be an input or an output.
Source Terminal 8. This pin can be an input or an output.
Most Negative Power Supply Potential. In single-supply applications, it can be connected to
ground.
Serial Data Output. This pin can be used for daisy-chaining a number of these devices together or
for reading back the data in the shift register for diagnostic purposes. The serial data is transferred
on the rising edge of SCLK and is valid on the falling edge of the clock. Pull this open-drain output
to the supply with an external resistor.
RESET/Logic Power Supply Input (VL). Under normal operation, drive the RESET/VL pin with a 2.7 V
to 5 V supply. Pull the pin low (<0.8 V) for a short period of time (15 ns is sufficient) to complete a
hardware reset. All switches are opened, and the appropriate registers are cleared to 0. When
using the RESET/VL pin to complete a hardware reset, all other SPI pins (SYNC, SCLK, and DIN)
must be driven low.
Rev. B | Page 10 of 19
Data Sheet
TSSOP
24
N/A 1
1
ADG1414
Pin No.
LFCSP
21
Mnemonic
SYNC
EP
Exposed Pad
Description
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC
goes low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is
transferred in on the falling edges of the following clocks. Taking SYNC high updates the switch
condition.
Exposed Pad. Exposed pad tied to the substrate, VSS.
N/A means not applicable.
Rev. B | Page 11 of 19
ADG1414
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
18
VDD = +10V
VSS = –10V
14
VDD = +13.5V
VSS = –13.5V
15
ON RESISTANCE (Ω)
VDD = +12V
VSS = –12V
10
8
6
VDD = +16.5V
VSS = –16.5V
VDD = +15V
VSS = –15V
4
TA = 25°C
IS = –10mA
0
–16.5 –13.5 –10.5 –7.5 –4.5
–1.5
1.5
4.5
7.5
10.5 13.5 16.5
VS, VD (V)
Figure 6. On Resistance as a Function of VD (VS), Dual Supply
(VDD = 10 V to 16.5 V and VSS = −10 V to −16.5 V)
TA = +25°C
6
TA = –40°C
0
5
10
15
VDD = +5.5V
VSS = –5.5V
10
VDD = +7V
VSS = –7V
–5
–3
1
–1
3
5
7
VS, VD (V)
TA = +85°C
15
TA = +25°C
10
5
TA = 25°C
IS = –10mA
TA = +125°C
20
0
–5
TA = –40°C
VDD = +5V
VSS = –5V
–4
–3
–2
–1
0
1
2
3
4
5
VS, VD (V)
Figure 7. On Resistance as a Function of VD (Vs), Dual Supply
(VDD = 3.0 V to 7 V and VSS = −3.0 V to −7 V)
08497-010
VDD = +5.0V
VSS = –5.0V
15
0
–7
–5
25
VDD = +4.5V
VSS = –4.5V
20
5
–10
30
ON RESISTANCE (Ω)
25
VDD = +15V
VSS = –15V
Figure 9. On Resistance as a Function of VD (VS), for Different Temperatures,
±15 V Dual Supply
08497-007
Figure 10. On Resistance as a Function of VD (VS), for Different Temperatures,
±5 V Dual Supply
25
40
VDD = +5V
VSS = 0V
35
30
20
20
VDD = +10.8V
VSS = 0V
15
ON RESISTANCE (Ω)
VDD = +8V
VSS = 0V
25
VDD = +12V
VSS = 0V
10
VDD = +15V
VSS = 0V
TA = 25°C
IS = –10mA
0
1.5
3.0
4.5
6.0
7.5
9.0
10.5
12.0 13.5
TA = +85°C
TA = +25°C
10
TA = –40°C
5
VDD = +13.2V
VSS = 0V
VDD = +12V
VSS = 0V
15.0
VS, VD (V)
Figure 8. On Resistance as a Function of VD (VS), Single Supply
0
08497-008
5
TA = +125°C
15
0
2
4
6
VS, VD (V)
8
10
12
08497-011
ON RESISTANCE (Ω)
TA = +85°C
9
VS, VD (V)
VDD = +3.0V
VSS = –3.0V
30
ON RESISTANCE (Ω)
TA = +125°C
0
–15
35
0
12
3
2
08497-006
ON RESISTANCE (Ω)
12
08497-009
16
Figure 11. On Resistance as a Function of VD (VS), for Different Temperatures,
12 V Single Supply
Rev. B | Page 12 of 19
Data Sheet
ADG1414
2.5
500
ID, IS (ON) – –
1.5
400
ID (OFF) –+
IS (OFF) +–
1.0
0.5
IDD (µA)
ID, IS (ON) ++
0
300
200
–0.5
IS (OFF) –+
–1.0
20
40
60
80
100
120
TEMPERATURE (°C)
0.5
0
1.0
80
CHARGE INJECTION (pC)
2.0
ID, IS (ON) – –
ID (OFF) –+
0.5
IS (OFF) +–
0
–0.5
–1.0
20
40
60
80
100
120
TEMPERATURE (°C)
4.0
4.5
5.0
TA = 25°C
40
20
VDD = +5V
VSS = –5V
VDD = +12V
VSS = 0V
0
VDD = +15V
VSS = –15V
–20
–60
–15
–10
–5
0
5
10
15
VS (V)
Figure 16. Charge Injection vs. Source Voltage (VS)
Figure 13. Leakage Current as a Function of Temperature,
±5 V Dual Supply
300
3.0
VDD = 12V
VSS = 0V
2.5 VBIAS = 1V/10V
ID, IS (ON) ++
250
2.0
tON (±5V)
200
1.5
ID (OFF) –+
0.5
IS (OFF) +–
TIME (ns)
ID, IS (ON) – –
1.0
tON (+12V)
150
100
0
tON (±15V)
tOFF (±5V)
50
IS (OFF) –+
0
20
40
60
80
TEMPERATURE (°C)
ID (OFF) +–
100
120
08497-015
–0.5
–1.0
3.5
–40
IS (OFF) –+
ID (OFF) +–
0
3.0
60
08497-014
LEAKAGE CURRENT (nA)
ID, IS (ON) ++
1.0
2.5
Figure 15. IDD vs. Logic Level
3.0
1.5
2.0
LOGIC LEVEL (V)
Figure 12. Leakage Current as a Function of Temperature, ±15 V Dual Supply
VDD = +5V
VSS = –5V
2.5 VBIAS = +4.5/–4.5V
1.5
08497-017
0
08497-016
VL = 2.7V
0
Figure 14. Leakage Current as a Function of Temperature, 12 V Single Supply
Rev. B | Page 13 of 19
0
–40
tOFF (+12V)
tOFF (±15V)
–20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 17. Transition Time vs. Temperature
120
08497-018
–2.0
100
ID (OFF) +–
–1.5
LEAKAGE CURRENT (nA)
IDD PER LOGIC INPUT
TA = 25°C
VL = 5.5V
08497-013
LEAKAGE CURRENT (nA)
VDD = +15V
VSS = –15V
2.0
VBIAS = +10/–10V
ADG1414
0
0.20
TA = 25°C
VDD = +15V
VSS = –15V
LOAD = 110Ω
0.18 TA = 25°C
0.16
VDD = +5V, VSS = –5V, VS = +5V p-p
0.14
–40
THD + N (%)
OFF ISOLATION (dB)
–20
Data Sheet
–60
–80
0.12
0.10
0.08
VDD = +15V, VSS = –15V, VS = +10V p-p
0.06
0.04
–100
100k
1M
10M
100M
1G
FREQUENCY (Hz)
0
08497-019
10k
0
10,000
15,000
20,000
FREQUENCY (Hz)
Figure 18. Off Isolation vs. Frequency
Figure 21. THD + N vs. Frequency, ±15 V Dual Supply
0
0
TA = 25°C
VDD = +15V
VSS = –15V
–0.5
–20
TA = 25°C
VDD = +15V
VSS = –15V
–1.0
–40
–1.5
ACPSRR (dB)
INSERTION LOSS (dB)
5000
08497-023
0.02
–120
1k
–2.0
–2.5
NO DECOUPLING
CAPACITORS
–60
DECOUPLING
CAPACITORS
–80
–3.0
10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
08497-012
–4.0
1k
Figure 19. On Response vs. Frequency
0
TA = 25°C
VDD = +15V
VSS = –15V
–40
–60
–80
–100
–120
10k
100k
1M
10M
100M
FREQUENCY (Hz)
10k
100k
1M
FREQUENCY (Hz)
Figure 22. ACPSRR vs. Frequency
1G
08497-021
CROSSTALK (dB)
–20
–120
1k
Figure 20. Crosstalk vs. Frequency
Rev. B | Page 14 of 19
10M
08497-025
–100
–3.5
Data Sheet
ADG1414
TEST CIRCUITS
IDS
VDD
VSS
0.1µF
0.1µF
V1
NETWORK
ANALYZER
RL
50Ω
S2
S
D
GND
ID (OFF)
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
A
VDD
Figure 24. Off Leakage
NC
D
NC = NO CONNECT
VSS
0.1µF
ID (ON)
0.1µF
VDD
A
NETWORK
ANALYZER
VSS
S
VD
50Ω
IN
08497-028
S
VS
D
Figure 25. On Leakage
VIN
RL
50Ω
GND
VOUT
VSS
0.1µF
0.1µF
INSERTION LOSS = 20 log
NETWORK
ANALYZER
VSS
S
50Ω
50Ω
IN
Figure 28. Insertion Loss
VDD
VS
D
VIN
RL
50Ω
GND
VSS
0.1µF
0.1µF
VOUT
VDD
AUDIO PRECISION
VSS
RS
Figure 26. Off Isolation
VOUT
VS
08497-032
OFF ISOLATION = 20 log
S
IN
VS
V p-p
D
VIN
GND
RL
10kΩ
Figure 29. THD + Noise
Rev. B | Page 15 of 19
VOUT
08497-035
VDD
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
08497-034
VDD
VOUT
VS
Figure 27. Channel-to-Channel Crosstalk
08497-027
VD
VS
R
50Ω
VS
Figure 23. On Resistance
A
VSS
D
RON = V1/IDS
IS (OFF)
VDD
S1
08497-026
VS
VOUT
D
08497-033
S
ADG1414
Data Sheet
VDD
VSS
0.1µF
0.1µF
VSS
S
VOUT
D
VS
INPUT LOGIC
RL
300Ω
CL
35pF
SYNC
50%
50%
90%
90%
VOUT
GND
tON
tOFF
08497-029
VDD
Figure 30. Switching Times
3V
SYNC
RS
VDD
VSS
VDD
VSS
S
D
QINJ = CL × ∆VOUT
INPUT LOGIC
∆VOUT
SWITCH OFF
SWITCH ON
Figure 31. Charge Injection
Rev. B | Page 16 of 19
GND
08497-031
VOUT
VOUT
CL
1nF
VS
Data Sheet
ADG1414
TERMINOLOGY
IDD
The positive supply current.
CD, CS (On)
The on switch capacitance, measured with reference to ground.
ISS
The negative supply current.
CIN
The digital input capacitance.
VD (VS)
The analog voltage on Terminal Dx or Terminal Sx.
tON
The delay between applying the digital control input and the
output switching on. See Figure 30.
RON
The ohmic resistance between Terminal Dx and Terminal Sx.
ΔRON
The difference between the RON of any two channels.
RFLAT (ON)
Flatness is defined as the difference between the maximum and
minimum value of on resistance, as measured over the specified
analog signal range.
IS (Off)
The source leakage current with the switch off.
tOFF
The delay between applying the digital control input and the
output switching off. See Figure 30.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
Off Isolation
A measure of unwanted signal coupling through an off switch.
Crosstalk
A measure of unwanted signal that is coupled through from one
channel to another as a result of parasitic capacitance.
ID (Off)
The drain leakage current with the switch off.
Bandwidth
The frequency at which the output is attenuated by 3 dB.
ID, IS (On)
The channel leakage current with the switch on.
On Response
The frequency response of the on switch.
VINL
The maximum input voltage for Logic 0.
VINH
The minimum input voltage for Logic 1.
Insertion Loss
The loss due to the on resistance of the switch.
IINL (IINH)
The input current of the digital input.
THD + N
The ratio of the harmonic amplitude plus noise of the signal to
the fundamental.
CS (Off)
The off switch source capacitance, measured with reference
to ground.
CD (Off)
The off switch drain capacitance, measured with reference to
ground.
AC Power Supply Rejection Ratio (ACPSRR)
A measure of the ability of a device to avoid coupling noise and
spurious signals that appear on the supply voltage pin to the
output of the switch. The dc voltage on the device is modulated
by a sine wave of 0.62 V p-p. The ratio of the amplitude of
signal on the output to the amplitude of the modulation is the
ACPSRR.
Rev. B | Page 17 of 19
ADG1414
Data Sheet
THEORY OF OPERATION
The ADG1414 is a set of serially controlled, octal SPST switches.
Each of the eight bits of the 8-bit write corresponds to one
switch of the device. A Logic 1 in the particular bit position
turns the switch on, whereas a Logic 0 turns the switch off.
Because an individual bit independently controls each switch, this
independence provides the option of having any, all, or none of
the switches turned on.
SERIAL INTERFACE
The ADG1414 has a 3-wire serial interface (SYNC, SCLK, and
DIN pins) that is compatible with SPI, QSPI, and MICROWIRE
interface standards, as well as most DSPs. See Figure 2 for a
timing diagram of a typical write sequence.
The write sequence begins by bringing the SYNC line low,
which enables the input shift register. Data from the DIN line is
clocked into the 8-bit input shift register on the falling edge of
SCLK. The serial clock frequency can be as high as 50 MHz,
making the ADG1414 compatible with high speed DSPs.
Data can be written to the shift register in more or less than
eight bits. In each case, the shift register retains the last eight
bits that were written. When all eight bits have been written
into the shift register, the SYNC line is brought high again. The
switches are updated with the new configuration, and the input
shift register is disabled. With SYNC held high, the input shift
register is disabled; therefore, further data or noise on the DIN
line has no effect on the shift register.
Data appears on the SDO pin on the rising edge of SCLK
suitable for daisy chaining or readback, delayed by eight bits.
INPUT SHIFT REGISTER
The input shift register is eight bits wide (see Table 10). Each bit
controls one switch. These data bits are transferred to the switch
register on the rising edge of SYNC.
Table 10. ADG1414 Input Shift Register Bit Map1
MSB
DB7
S8
1
DB6
S7
DB5
S6
DB4
S5
DB3
S4
Logic 0 = switch off, and Logic 1 = switch on.
DB2
S3
DB1
S2
LSB
DB0
S1
POWER-ON RESET
The ADG1414 contains a power-on reset circuit. On power-up
of the device, all switches are in the off condition and the internal
shift register is filled with zeros and remains so until a valid
write takes place.
The device also has a RESET/VL pin. Under normal operation,
drive the RESET/VL pin with a 2.7 V to 5 V supply and pull the
pin low for short period of time (15 ns is sufficient) to complete
the hardware reset.
When using the RESET/VL pin to do a hardware reset, drive all
other SPI pins (SYNC, SCLK, and DIN) low. This is to prevent
current flow due to ESD protection diodes on the VL pin to the
SPI pins.
When the RESET/VL pin is low, all switches are off and the
appropriate registers are cleared to 0.
DAISY CHAINING
For systems that contain several switches, the SDO pin can be
used to daisy-chain several devices together. The SDO pin can
also be used for diagnostic purposes and provide serial readback,
wherein the user can read back the switch contents.
SDO is an open-drain output that must be pulled to the VL
supply with an external resistor.
The SCLK is continuously applied to the input shift register
when SYNC is low. If more than eight clock pulses are applied,
the data ripples out of the shift register and appears on the SDO
line. This data is clocked out on the rising edge of SCLK and is
valid on the falling edge. By connecting this line to the DIN
input on the next device in the chain, a multiswitch interface is
constructed. Each device in the system requires eight clock
pulses; therefore, the total number of clock cycles must equal
8N, where N is the total number of devices in the chain.
When the serial transfer to all devices is complete, SYNC is
taken high. This prevents any further data from being clocked
into the input shift register.
The serial clock can be a continuous or a gated clock. A continuous
SCLK source can be used only if SYNC can be held low for the
correct number of clock cycles. In gated clock mode, a burst
clock containing the exact number of clock cycles must be used,
and SYNC must be taken high after the final clock to latch the
data. Gated clock mode reduces power consumption by
reducing the active clock time.
Rev. B | Page 18 of 19
Data Sheet
ADG1414
OUTLINE DIMENSIONS
7.90
7.80
7.70
24
13
4.50
4.40
4.30
1
6.40 BSC
12
PIN 1
0.65
BSC
0.15
0.05
0.30
0.19
1.20
MAX
0.20
0.09
SEATING
PLANE
0.10 COPLANARITY
0.75
0.60
0.45
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AD
Figure 32. 24-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-24)
Dimensions shown in millimeters
0.30
0.25
0.18
0.50
BSC
PIN 1
INDICATOR
24
19
18
1
2.65
2.50 SQ
2.45
EXPOSED
PAD
13
0.50
0.40
0.30
TOP VIEW
0.80
0.75
0.70
6
12
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SEATING
PLANE
7
0.25 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.20 REF
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD.
03-11-2013-A
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
Figure 33. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-24-7)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADG1414BRUZ
ADG1414BRUZ-REEL7
ADG1414BCPZ-REEL7
1
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Package Description
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Thin Shrink Small Outline Package [TSSOP]
24-Lead Lead Frame Chip Scale Package [LFCSP]
Z = RoHS Compliant Part.
©2009–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08497-0-11/15(B)
Rev. B | Page 19 of 19
Package Option
RU-24
RU-24
CP-24-7